1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_HW_CATALOG_H 8 #define _DPU_HW_CATALOG_H 9 10 #include <linux/kernel.h> 11 #include <linux/bug.h> 12 #include <linux/bitmap.h> 13 #include <linux/err.h> 14 15 /** 16 * Max hardware block count: For ex: max 12 SSPP pipes or 17 * 5 ctl paths. In all cases, it can have max 12 hardware blocks 18 * based on current design 19 */ 20 #define MAX_BLOCKS 12 21 22 #define DPU_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28) |\ 23 ((MINOR & 0xFFF) << 16) |\ 24 (STEP & 0xFFFF)) 25 26 #define DPU_HW_MAJOR(rev) ((rev) >> 28) 27 #define DPU_HW_MINOR(rev) (((rev) >> 16) & 0xFFF) 28 #define DPU_HW_STEP(rev) ((rev) & 0xFFFF) 29 #define DPU_HW_MAJOR_MINOR(rev) ((rev) >> 16) 30 31 #define IS_DPU_MAJOR_MINOR_SAME(rev1, rev2) \ 32 (DPU_HW_MAJOR_MINOR((rev1)) == DPU_HW_MAJOR_MINOR((rev2))) 33 34 #define DPU_HW_VER_170 DPU_HW_VER(1, 7, 0) /* 8996 v1.0 */ 35 #define DPU_HW_VER_171 DPU_HW_VER(1, 7, 1) /* 8996 v2.0 */ 36 #define DPU_HW_VER_172 DPU_HW_VER(1, 7, 2) /* 8996 v3.0 */ 37 #define DPU_HW_VER_300 DPU_HW_VER(3, 0, 0) /* 8998 v1.0 */ 38 #define DPU_HW_VER_301 DPU_HW_VER(3, 0, 1) /* 8998 v1.1 */ 39 #define DPU_HW_VER_400 DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */ 40 #define DPU_HW_VER_401 DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */ 41 #define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */ 42 #define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sm8150 v1.0 */ 43 #define DPU_HW_VER_501 DPU_HW_VER(5, 0, 1) /* sm8150 v2.0 */ 44 #define DPU_HW_VER_510 DPU_HW_VER(5, 1, 1) /* sc8180 */ 45 #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */ 46 #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ 47 #define DPU_HW_VER_630 DPU_HW_VER(6, 3, 0) /* sm6115|sm4250 */ 48 #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ 49 #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ 50 51 #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) 52 #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) 53 #define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400) 54 #define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410) 55 #define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500) 56 #define IS_SC7180_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_620) 57 #define IS_SC7280_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_720) 58 59 #define DPU_HW_BLK_NAME_LEN 16 60 61 #define MAX_IMG_WIDTH 0x3fff 62 #define MAX_IMG_HEIGHT 0x3fff 63 64 #define CRTC_DUAL_MIXERS 2 65 66 #define MAX_XIN_COUNT 16 67 68 /** 69 * Supported UBWC feature versions 70 */ 71 enum { 72 DPU_HW_UBWC_VER_10 = 0x100, 73 DPU_HW_UBWC_VER_20 = 0x200, 74 DPU_HW_UBWC_VER_30 = 0x300, 75 DPU_HW_UBWC_VER_40 = 0x400, 76 }; 77 78 /** 79 * MDP TOP BLOCK features 80 * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe 81 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats 82 * @DPU_MDP_BWC, MDSS HW supports Bandwidth compression. 83 * @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth 84 * compression initial revision 85 * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 86 * @DPU_MDP_MAX Maximum value 87 88 */ 89 enum { 90 DPU_MDP_PANIC_PER_PIPE = 0x1, 91 DPU_MDP_10BIT_SUPPORT, 92 DPU_MDP_BWC, 93 DPU_MDP_UBWC_1_0, 94 DPU_MDP_UBWC_1_5, 95 DPU_MDP_AUDIO_SELECT, 96 DPU_MDP_MAX 97 }; 98 99 /** 100 * SSPP sub-blocks/features 101 * @DPU_SSPP_SRC Src and fetch part of the pipes, 102 * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support 103 * @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support 104 * @DPU_SSPP_SCALER_QSEED3LITE, QSEED3 Lite alogorithm support 105 * @DPU_SSPP_SCALER_QSEED4, QSEED4 algorithm support 106 * @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes 107 * @DPU_SSPP_CSC, Support of Color space converion 108 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion 109 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer 110 * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq 111 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control 112 * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect 113 * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support 114 * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support 115 * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper 116 * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec 117 * @DPU_SSPP_CDP Supports client driven prefetch 118 * @DPU_SSPP_INLINE_ROTATION Support inline rotation 119 * @DPU_SSPP_MAX maximum value 120 */ 121 enum { 122 DPU_SSPP_SRC = 0x1, 123 DPU_SSPP_SCALER_QSEED2, 124 DPU_SSPP_SCALER_QSEED3, 125 DPU_SSPP_SCALER_QSEED3LITE, 126 DPU_SSPP_SCALER_QSEED4, 127 DPU_SSPP_SCALER_RGB, 128 DPU_SSPP_CSC, 129 DPU_SSPP_CSC_10BIT, 130 DPU_SSPP_CURSOR, 131 DPU_SSPP_QOS, 132 DPU_SSPP_QOS_8LVL, 133 DPU_SSPP_EXCL_RECT, 134 DPU_SSPP_SMART_DMA_V1, 135 DPU_SSPP_SMART_DMA_V2, 136 DPU_SSPP_TS_PREFILL, 137 DPU_SSPP_TS_PREFILL_REC1, 138 DPU_SSPP_CDP, 139 DPU_SSPP_INLINE_ROTATION, 140 DPU_SSPP_MAX 141 }; 142 143 /* 144 * MIXER sub-blocks/features 145 * @DPU_MIXER_LAYER Layer mixer layer blend configuration, 146 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration 147 * @DPU_MIXER_GC Gamma correction block 148 * @DPU_DIM_LAYER Layer mixer supports dim layer 149 * @DPU_MIXER_COMBINED_ALPHA Layer mixer has combined alpha register 150 * @DPU_MIXER_MAX maximum value 151 */ 152 enum { 153 DPU_MIXER_LAYER = 0x1, 154 DPU_MIXER_SOURCESPLIT, 155 DPU_MIXER_GC, 156 DPU_DIM_LAYER, 157 DPU_MIXER_COMBINED_ALPHA, 158 DPU_MIXER_MAX 159 }; 160 161 /** 162 * DSPP sub-blocks 163 * @DPU_DSPP_PCC Panel color correction block 164 * @DPU_DSPP_GC Gamma correction block 165 */ 166 enum { 167 DPU_DSPP_PCC = 0x1, 168 DPU_DSPP_GC, 169 DPU_DSPP_MAX 170 }; 171 172 /** 173 * PINGPONG sub-blocks 174 * @DPU_PINGPONG_TE Tear check block 175 * @DPU_PINGPONG_TE2 Additional tear check block for split pipes 176 * @DPU_PINGPONG_SPLIT PP block supports split fifo 177 * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo 178 * @DPU_PINGPONG_DITHER, Dither blocks 179 * @DPU_PINGPONG_MAX 180 */ 181 enum { 182 DPU_PINGPONG_TE = 0x1, 183 DPU_PINGPONG_TE2, 184 DPU_PINGPONG_SPLIT, 185 DPU_PINGPONG_SLAVE, 186 DPU_PINGPONG_DITHER, 187 DPU_PINGPONG_MAX 188 }; 189 190 /** 191 * CTL sub-blocks 192 * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display 193 * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) 194 * @DPU_CTL_VM_CFG: CTL config to support multiple VMs 195 * @DPU_CTL_MAX 196 */ 197 enum { 198 DPU_CTL_SPLIT_DISPLAY = 0x1, 199 DPU_CTL_ACTIVE_CFG, 200 DPU_CTL_FETCH_ACTIVE, 201 DPU_CTL_VM_CFG, 202 DPU_CTL_MAX 203 }; 204 205 /** 206 * INTF sub-blocks 207 * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which 208 * pixel data arrives to this INTF 209 * @DPU_INTF_TE INTF block has TE configuration support 210 * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate 211 than video timing 212 * @DPU_INTF_MAX 213 */ 214 enum { 215 DPU_INTF_INPUT_CTRL = 0x1, 216 DPU_INTF_TE, 217 DPU_DATA_HCTL_EN, 218 DPU_INTF_MAX 219 }; 220 221 /** 222 * WB sub-blocks and features 223 * @DPU_WB_LINE_MODE Writeback module supports line/linear mode 224 * @DPU_WB_BLOCK_MODE Writeback module supports block mode read 225 * @DPU_WB_CHROMA_DOWN, Writeback chroma down block, 226 * @DPU_WB_DOWNSCALE, Writeback integer downscaler, 227 * @DPU_WB_DITHER, Dither block 228 * @DPU_WB_TRAFFIC_SHAPER, Writeback traffic shaper bloc 229 * @DPU_WB_UBWC, Writeback Universal bandwidth compression 230 * @DPU_WB_YUV_CONFIG Writeback supports output of YUV colorspace 231 * @DPU_WB_PIPE_ALPHA Writeback supports pipe alpha 232 * @DPU_WB_XY_ROI_OFFSET Writeback supports x/y-offset of out ROI in 233 * the destination image 234 * @DPU_WB_QOS, Writeback supports QoS control, danger/safe/creq 235 * @DPU_WB_QOS_8LVL, Writeback supports 8-level QoS control 236 * @DPU_WB_CDP Writeback supports client driven prefetch 237 * @DPU_WB_INPUT_CTRL Writeback supports from which pp block input pixel 238 * data arrives. 239 * @DPU_WB_CROP CWB supports cropping 240 * @DPU_WB_MAX maximum value 241 */ 242 enum { 243 DPU_WB_LINE_MODE = 0x1, 244 DPU_WB_BLOCK_MODE, 245 DPU_WB_UBWC, 246 DPU_WB_YUV_CONFIG, 247 DPU_WB_PIPE_ALPHA, 248 DPU_WB_XY_ROI_OFFSET, 249 DPU_WB_QOS, 250 DPU_WB_QOS_8LVL, 251 DPU_WB_CDP, 252 DPU_WB_INPUT_CTRL, 253 DPU_WB_CROP, 254 DPU_WB_MAX 255 }; 256 257 /** 258 * VBIF sub-blocks and features 259 * @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit 260 * @DPU_VBIF_QOS_REMAP VBIF supports QoS priority remap 261 * @DPU_VBIF_MAX maximum value 262 */ 263 enum { 264 DPU_VBIF_QOS_OTLIM = 0x1, 265 DPU_VBIF_QOS_REMAP, 266 DPU_VBIF_MAX 267 }; 268 269 /** 270 * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU 271 * @name: string name for debug purposes 272 * @id: enum identifying this block 273 * @base: register base offset to mdss 274 * @len: length of hardware block 275 * @features bit mask identifying sub-blocks/features 276 */ 277 #define DPU_HW_BLK_INFO \ 278 char name[DPU_HW_BLK_NAME_LEN]; \ 279 u32 id; \ 280 u32 base; \ 281 u32 len; \ 282 unsigned long features 283 284 /** 285 * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU 286 * @name: string name for debug purposes 287 * @id: enum identifying this sub-block 288 * @base: offset of this sub-block relative to the block 289 * offset 290 * @len register block length of this sub-block 291 */ 292 #define DPU_HW_SUBBLK_INFO \ 293 char name[DPU_HW_BLK_NAME_LEN]; \ 294 u32 id; \ 295 u32 base; \ 296 u32 len 297 298 /** 299 * struct dpu_src_blk: SSPP part of the source pipes 300 * @info: HW register and features supported by this sub-blk 301 */ 302 struct dpu_src_blk { 303 DPU_HW_SUBBLK_INFO; 304 }; 305 306 /** 307 * struct dpu_scaler_blk: Scaler information 308 * @info: HW register and features supported by this sub-blk 309 * @version: qseed block revision 310 */ 311 struct dpu_scaler_blk { 312 DPU_HW_SUBBLK_INFO; 313 u32 version; 314 }; 315 316 struct dpu_csc_blk { 317 DPU_HW_SUBBLK_INFO; 318 }; 319 320 /** 321 * struct dpu_pp_blk : Pixel processing sub-blk information 322 * @info: HW register and features supported by this sub-blk 323 * @version: HW Algorithm version 324 */ 325 struct dpu_pp_blk { 326 DPU_HW_SUBBLK_INFO; 327 u32 version; 328 }; 329 330 /** 331 * enum dpu_qos_lut_usage - define QoS LUT use cases 332 */ 333 enum dpu_qos_lut_usage { 334 DPU_QOS_LUT_USAGE_LINEAR, 335 DPU_QOS_LUT_USAGE_MACROTILE, 336 DPU_QOS_LUT_USAGE_NRT, 337 DPU_QOS_LUT_USAGE_MAX, 338 }; 339 340 /** 341 * struct dpu_qos_lut_entry - define QoS LUT table entry 342 * @fl: fill level, or zero on last entry to indicate default lut 343 * @lut: lut to use if equal to or less than fill level 344 */ 345 struct dpu_qos_lut_entry { 346 u32 fl; 347 u64 lut; 348 }; 349 350 /** 351 * struct dpu_qos_lut_tbl - define QoS LUT table 352 * @nentry: number of entry in this table 353 * @entries: Pointer to table entries 354 */ 355 struct dpu_qos_lut_tbl { 356 u32 nentry; 357 const struct dpu_qos_lut_entry *entries; 358 }; 359 360 /** 361 * struct dpu_rotation_cfg - define inline rotation config 362 * @rot_maxheight: max pre rotated height allowed for rotation 363 * @rot_num_formats: number of elements in @rot_format_list 364 * @rot_format_list: list of supported rotator formats 365 */ 366 struct dpu_rotation_cfg { 367 u32 rot_maxheight; 368 size_t rot_num_formats; 369 const u32 *rot_format_list; 370 }; 371 372 /** 373 * struct dpu_caps - define DPU capabilities 374 * @max_mixer_width max layer mixer line width support. 375 * @max_mixer_blendstages max layer mixer blend stages or 376 * supported z order 377 * @qseed_type qseed2 or qseed3 support. 378 * @smart_dma_rev Supported version of SmartDMA feature. 379 * @ubwc_version UBWC feature version (0x0 for not supported) 380 * @has_src_split source split feature status 381 * @has_dim_layer dim layer feature status 382 * @has_idle_pc indicate if idle power collapse feature is supported 383 * @has_3d_merge indicate if 3D merge is supported 384 * @max_linewidth max linewidth for sspp 385 * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes 386 * @max_hdeci_exp max horizontal decimation supported (max is 2^value) 387 * @max_vdeci_exp max vertical decimation supported (max is 2^value) 388 */ 389 struct dpu_caps { 390 u32 max_mixer_width; 391 u32 max_mixer_blendstages; 392 u32 qseed_type; 393 u32 smart_dma_rev; 394 u32 ubwc_version; 395 bool has_src_split; 396 bool has_dim_layer; 397 bool has_idle_pc; 398 bool has_3d_merge; 399 /* SSPP limits */ 400 u32 max_linewidth; 401 u32 pixel_ram_size; 402 u32 max_hdeci_exp; 403 u32 max_vdeci_exp; 404 }; 405 406 /** 407 * struct dpu_sspp_sub_blks : SSPP sub-blocks 408 * common: Pointer to common configurations shared by sub blocks 409 * @creq_vblank: creq priority during vertical blanking 410 * @danger_vblank: danger priority during vertical blanking 411 * @maxdwnscale: max downscale ratio supported(without DECIMATION) 412 * @maxupscale: maxupscale ratio supported 413 * @smart_dma_priority: hw priority of rect1 of multirect pipe 414 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps 415 * @qseed_ver: qseed version 416 * @src_blk: 417 * @scaler_blk: 418 * @csc_blk: 419 * @hsic: 420 * @memcolor: 421 * @pcc_blk: 422 * @igc_blk: 423 * @format_list: Pointer to list of supported formats 424 * @num_formats: Number of supported formats 425 * @virt_format_list: Pointer to list of supported formats for virtual planes 426 * @virt_num_formats: Number of supported formats for virtual planes 427 * @dpu_rotation_cfg: inline rotation configuration 428 */ 429 struct dpu_sspp_sub_blks { 430 u32 creq_vblank; 431 u32 danger_vblank; 432 u32 maxdwnscale; 433 u32 maxupscale; 434 u32 smart_dma_priority; 435 u32 max_per_pipe_bw; 436 u32 qseed_ver; 437 struct dpu_src_blk src_blk; 438 struct dpu_scaler_blk scaler_blk; 439 struct dpu_pp_blk csc_blk; 440 struct dpu_pp_blk hsic_blk; 441 struct dpu_pp_blk memcolor_blk; 442 struct dpu_pp_blk pcc_blk; 443 struct dpu_pp_blk igc_blk; 444 445 const u32 *format_list; 446 u32 num_formats; 447 const u32 *virt_format_list; 448 u32 virt_num_formats; 449 const struct dpu_rotation_cfg *rotation_cfg; 450 }; 451 452 /** 453 * struct dpu_lm_sub_blks: information of mixer block 454 * @maxwidth: Max pixel width supported by this mixer 455 * @maxblendstages: Max number of blend-stages supported 456 * @blendstage_base: Blend-stage register base offset 457 * @gc: gamma correction block 458 */ 459 struct dpu_lm_sub_blks { 460 u32 maxwidth; 461 u32 maxblendstages; 462 u32 blendstage_base[MAX_BLOCKS]; 463 struct dpu_pp_blk gc; 464 }; 465 466 /** 467 * struct dpu_dspp_sub_blks: Information of DSPP block 468 * @gc : gamma correction block 469 * @pcc: pixel color correction block 470 */ 471 struct dpu_dspp_sub_blks { 472 struct dpu_pp_blk gc; 473 struct dpu_pp_blk pcc; 474 }; 475 476 struct dpu_pingpong_sub_blks { 477 struct dpu_pp_blk te; 478 struct dpu_pp_blk te2; 479 struct dpu_pp_blk dither; 480 }; 481 482 /** 483 * dpu_clk_ctrl_type - Defines top level clock control signals 484 */ 485 enum dpu_clk_ctrl_type { 486 DPU_CLK_CTRL_NONE, 487 DPU_CLK_CTRL_VIG0, 488 DPU_CLK_CTRL_VIG1, 489 DPU_CLK_CTRL_VIG2, 490 DPU_CLK_CTRL_VIG3, 491 DPU_CLK_CTRL_VIG4, 492 DPU_CLK_CTRL_RGB0, 493 DPU_CLK_CTRL_RGB1, 494 DPU_CLK_CTRL_RGB2, 495 DPU_CLK_CTRL_RGB3, 496 DPU_CLK_CTRL_DMA0, 497 DPU_CLK_CTRL_DMA1, 498 DPU_CLK_CTRL_DMA2, 499 DPU_CLK_CTRL_DMA3, 500 DPU_CLK_CTRL_CURSOR0, 501 DPU_CLK_CTRL_CURSOR1, 502 DPU_CLK_CTRL_INLINE_ROT0_SSPP, 503 DPU_CLK_CTRL_REG_DMA, 504 DPU_CLK_CTRL_WB2, 505 DPU_CLK_CTRL_MAX, 506 }; 507 508 /* struct dpu_clk_ctrl_reg : Clock control register 509 * @reg_off: register offset 510 * @bit_off: bit offset 511 */ 512 struct dpu_clk_ctrl_reg { 513 u32 reg_off; 514 u32 bit_off; 515 }; 516 517 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info 518 * @id: index identifying this block 519 * @base: register base offset to mdss 520 * @features bit mask identifying sub-blocks/features 521 * @highest_bank_bit: UBWC parameter 522 * @ubwc_static: ubwc static configuration 523 * @ubwc_swizzle: ubwc default swizzle setting 524 * @clk_ctrls clock control register definition 525 */ 526 struct dpu_mdp_cfg { 527 DPU_HW_BLK_INFO; 528 u32 highest_bank_bit; 529 u32 ubwc_swizzle; 530 struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; 531 }; 532 533 /* struct dpu_ctl_cfg : MDP CTL instance info 534 * @id: index identifying this block 535 * @base: register base offset to mdss 536 * @features bit mask identifying sub-blocks/features 537 * @intr_start: interrupt index for CTL_START 538 */ 539 struct dpu_ctl_cfg { 540 DPU_HW_BLK_INFO; 541 s32 intr_start; 542 }; 543 544 /** 545 * struct dpu_sspp_cfg - information of source pipes 546 * @id: index identifying this block 547 * @base register offset of this block 548 * @features bit mask identifying sub-blocks/features 549 * @sblk: SSPP sub-blocks information 550 * @xin_id: bus client identifier 551 * @clk_ctrl clock control identifier 552 * @type sspp type identifier 553 */ 554 struct dpu_sspp_cfg { 555 DPU_HW_BLK_INFO; 556 const struct dpu_sspp_sub_blks *sblk; 557 u32 xin_id; 558 enum dpu_clk_ctrl_type clk_ctrl; 559 u32 type; 560 }; 561 562 /** 563 * struct dpu_lm_cfg - information of layer mixer blocks 564 * @id: index identifying this block 565 * @base register offset of this block 566 * @features bit mask identifying sub-blocks/features 567 * @sblk: LM Sub-blocks information 568 * @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported 569 * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL 570 */ 571 struct dpu_lm_cfg { 572 DPU_HW_BLK_INFO; 573 const struct dpu_lm_sub_blks *sblk; 574 u32 pingpong; 575 u32 dspp; 576 unsigned long lm_pair_mask; 577 }; 578 579 /** 580 * struct dpu_dspp_cfg - information of DSPP blocks 581 * @id enum identifying this block 582 * @base register offset of this block 583 * @features bit mask identifying sub-blocks/features 584 * supported by this block 585 * @sblk sub-blocks information 586 */ 587 struct dpu_dspp_cfg { 588 DPU_HW_BLK_INFO; 589 const struct dpu_dspp_sub_blks *sblk; 590 }; 591 592 /** 593 * struct dpu_pingpong_cfg - information of PING-PONG blocks 594 * @id enum identifying this block 595 * @base register offset of this block 596 * @features bit mask identifying sub-blocks/features 597 * @intr_done: index for PINGPONG done interrupt 598 * @intr_rdptr: index for PINGPONG readpointer done interrupt 599 * @sblk sub-blocks information 600 */ 601 struct dpu_pingpong_cfg { 602 DPU_HW_BLK_INFO; 603 u32 merge_3d; 604 s32 intr_done; 605 s32 intr_rdptr; 606 const struct dpu_pingpong_sub_blks *sblk; 607 }; 608 609 /** 610 * struct dpu_merge_3d_cfg - information of DSPP blocks 611 * @id enum identifying this block 612 * @base register offset of this block 613 * @features bit mask identifying sub-blocks/features 614 * supported by this block 615 * @sblk sub-blocks information 616 */ 617 struct dpu_merge_3d_cfg { 618 DPU_HW_BLK_INFO; 619 const struct dpu_merge_3d_sub_blks *sblk; 620 }; 621 622 /** 623 * struct dpu_dsc_cfg - information of DSC blocks 624 * @id enum identifying this block 625 * @base register offset of this block 626 * @features bit mask identifying sub-blocks/features 627 */ 628 struct dpu_dsc_cfg { 629 DPU_HW_BLK_INFO; 630 }; 631 632 /** 633 * struct dpu_intf_cfg - information of timing engine blocks 634 * @id enum identifying this block 635 * @base register offset of this block 636 * @features bit mask identifying sub-blocks/features 637 * @type: Interface type(DSI, DP, HDMI) 638 * @controller_id: Controller Instance ID in case of multiple of intf type 639 * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch 640 * @intr_underrun: index for INTF underrun interrupt 641 * @intr_vsync: index for INTF VSYNC interrupt 642 */ 643 struct dpu_intf_cfg { 644 DPU_HW_BLK_INFO; 645 u32 type; /* interface type*/ 646 u32 controller_id; 647 u32 prog_fetch_lines_worst_case; 648 s32 intr_underrun; 649 s32 intr_vsync; 650 }; 651 652 /** 653 * struct dpu_wb_cfg - information of writeback blocks 654 * @DPU_HW_BLK_INFO: refer to the description above for DPU_HW_BLK_INFO 655 * @vbif_idx: vbif client index 656 * @maxlinewidth: max line width supported by writeback block 657 * @xin_id: bus client identifier 658 * @intr_wb_done: interrupt index for WB_DONE 659 * @format_list: list of formats supported by this writeback block 660 * @num_formats: number of formats supported by this writeback block 661 * @clk_ctrl: clock control identifier 662 */ 663 struct dpu_wb_cfg { 664 DPU_HW_BLK_INFO; 665 u8 vbif_idx; 666 u32 maxlinewidth; 667 u32 xin_id; 668 s32 intr_wb_done; 669 const u32 *format_list; 670 u32 num_formats; 671 enum dpu_clk_ctrl_type clk_ctrl; 672 }; 673 674 /** 675 * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting 676 * @pps pixel per seconds 677 * @ot_limit OT limit to use up to specified pixel per second 678 */ 679 struct dpu_vbif_dynamic_ot_cfg { 680 u64 pps; 681 u32 ot_limit; 682 }; 683 684 /** 685 * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table 686 * @count length of cfg 687 * @cfg pointer to array of configuration settings with 688 * ascending requirements 689 */ 690 struct dpu_vbif_dynamic_ot_tbl { 691 u32 count; 692 const struct dpu_vbif_dynamic_ot_cfg *cfg; 693 }; 694 695 /** 696 * struct dpu_vbif_qos_tbl - QoS priority table 697 * @npriority_lvl num of priority level 698 * @priority_lvl pointer to array of priority level in ascending order 699 */ 700 struct dpu_vbif_qos_tbl { 701 u32 npriority_lvl; 702 const u32 *priority_lvl; 703 }; 704 705 /** 706 * struct dpu_vbif_cfg - information of VBIF blocks 707 * @id enum identifying this block 708 * @base register offset of this block 709 * @features bit mask identifying sub-blocks/features 710 * @ot_rd_limit default OT read limit 711 * @ot_wr_limit default OT write limit 712 * @xin_halt_timeout maximum time (in usec) for xin to halt 713 * @qos_rp_remap_size size of VBIF_XINL_QOS_RP_REMAP register space 714 * @dynamic_ot_rd_tbl dynamic OT read configuration table 715 * @dynamic_ot_wr_tbl dynamic OT write configuration table 716 * @qos_rt_tbl real-time QoS priority table 717 * @qos_nrt_tbl non-real-time QoS priority table 718 * @memtype_count number of defined memtypes 719 * @memtype array of xin memtype definitions 720 */ 721 struct dpu_vbif_cfg { 722 DPU_HW_BLK_INFO; 723 u32 default_ot_rd_limit; 724 u32 default_ot_wr_limit; 725 u32 xin_halt_timeout; 726 u32 qos_rp_remap_size; 727 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl; 728 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl; 729 struct dpu_vbif_qos_tbl qos_rt_tbl; 730 struct dpu_vbif_qos_tbl qos_nrt_tbl; 731 u32 memtype_count; 732 u32 memtype[MAX_XIN_COUNT]; 733 }; 734 /** 735 * struct dpu_reg_dma_cfg - information of lut dma blocks 736 * @id enum identifying this block 737 * @base register offset of this block 738 * @features bit mask identifying sub-blocks/features 739 * @version version of lutdma hw block 740 * @trigger_sel_off offset to trigger select registers of lutdma 741 */ 742 struct dpu_reg_dma_cfg { 743 DPU_HW_BLK_INFO; 744 u32 version; 745 u32 trigger_sel_off; 746 u32 xin_id; 747 enum dpu_clk_ctrl_type clk_ctrl; 748 }; 749 750 /** 751 * Define CDP use cases 752 * @DPU_PERF_CDP_UDAGE_RT: real-time use cases 753 * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD 754 */ 755 enum { 756 DPU_PERF_CDP_USAGE_RT, 757 DPU_PERF_CDP_USAGE_NRT, 758 DPU_PERF_CDP_USAGE_MAX 759 }; 760 761 /** 762 * struct dpu_perf_cdp_cfg - define CDP use case configuration 763 * @rd_enable: true if read pipe CDP is enabled 764 * @wr_enable: true if write pipe CDP is enabled 765 */ 766 struct dpu_perf_cdp_cfg { 767 bool rd_enable; 768 bool wr_enable; 769 }; 770 771 /** 772 * struct dpu_perf_cfg - performance control settings 773 * @max_bw_low low threshold of maximum bandwidth (kbps) 774 * @max_bw_high high threshold of maximum bandwidth (kbps) 775 * @min_core_ib minimum bandwidth for core (kbps) 776 * @min_core_ib minimum mnoc ib vote in kbps 777 * @min_llcc_ib minimum llcc ib vote in kbps 778 * @min_dram_ib minimum dram ib vote in kbps 779 * @undersized_prefill_lines undersized prefill in lines 780 * @xtra_prefill_lines extra prefill latency in lines 781 * @dest_scale_prefill_lines destination scaler latency in lines 782 * @macrotile_perfill_lines macrotile latency in lines 783 * @yuv_nv12_prefill_lines yuv_nv12 latency in lines 784 * @linear_prefill_lines linear latency in lines 785 * @downscaling_prefill_lines downscaling latency in lines 786 * @amortizable_theshold minimum y position for traffic shaping prefill 787 * @min_prefill_lines minimum pipeline latency in lines 788 * @clk_inefficiency_factor DPU src clock inefficiency factor 789 * @bw_inefficiency_factor DPU axi bus bw inefficiency factor 790 * @safe_lut_tbl: LUT tables for safe signals 791 * @danger_lut_tbl: LUT tables for danger signals 792 * @qos_lut_tbl: LUT tables for QoS signals 793 * @cdp_cfg cdp use case configurations 794 */ 795 struct dpu_perf_cfg { 796 u32 max_bw_low; 797 u32 max_bw_high; 798 u32 min_core_ib; 799 u32 min_llcc_ib; 800 u32 min_dram_ib; 801 u32 undersized_prefill_lines; 802 u32 xtra_prefill_lines; 803 u32 dest_scale_prefill_lines; 804 u32 macrotile_prefill_lines; 805 u32 yuv_nv12_prefill_lines; 806 u32 linear_prefill_lines; 807 u32 downscaling_prefill_lines; 808 u32 amortizable_threshold; 809 u32 min_prefill_lines; 810 u32 clk_inefficiency_factor; 811 u32 bw_inefficiency_factor; 812 u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 813 u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 814 struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 815 struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX]; 816 }; 817 818 /** 819 * struct dpu_mdss_cfg - information of MDSS HW 820 * This is the main catalog data structure representing 821 * this HW version. Contains number of instances, 822 * register offsets, capabilities of the all MDSS HW sub-blocks. 823 * 824 * @dma_formats Supported formats for dma pipe 825 * @cursor_formats Supported formats for cursor pipe 826 * @vig_formats Supported formats for vig pipe 827 * @mdss_irqs: Bitmap with the irqs supported by the target 828 */ 829 struct dpu_mdss_cfg { 830 const struct dpu_caps *caps; 831 832 u32 mdp_count; 833 const struct dpu_mdp_cfg *mdp; 834 835 u32 ctl_count; 836 const struct dpu_ctl_cfg *ctl; 837 838 u32 sspp_count; 839 const struct dpu_sspp_cfg *sspp; 840 841 u32 mixer_count; 842 const struct dpu_lm_cfg *mixer; 843 844 u32 pingpong_count; 845 const struct dpu_pingpong_cfg *pingpong; 846 847 u32 merge_3d_count; 848 const struct dpu_merge_3d_cfg *merge_3d; 849 850 u32 dsc_count; 851 struct dpu_dsc_cfg *dsc; 852 853 u32 intf_count; 854 const struct dpu_intf_cfg *intf; 855 856 u32 vbif_count; 857 const struct dpu_vbif_cfg *vbif; 858 859 u32 wb_count; 860 const struct dpu_wb_cfg *wb; 861 862 u32 reg_dma_count; 863 const struct dpu_reg_dma_cfg *dma_cfg; 864 865 u32 ad_count; 866 867 u32 dspp_count; 868 const struct dpu_dspp_cfg *dspp; 869 870 /* Add additional block data structures here */ 871 872 const struct dpu_perf_cfg *perf; 873 const struct dpu_format_extended *dma_formats; 874 const struct dpu_format_extended *cursor_formats; 875 const struct dpu_format_extended *vig_formats; 876 877 unsigned long mdss_irqs; 878 }; 879 880 struct dpu_mdss_hw_cfg_handler { 881 u32 hw_rev; 882 const struct dpu_mdss_cfg *dpu_cfg; 883 }; 884 885 /** 886 * dpu_hw_catalog_init - dpu hardware catalog init API retrieves 887 * hardcoded target specific catalog information in config structure 888 * @hw_rev: caller needs provide the hardware revision. 889 * 890 * Return: dpu config structure 891 */ 892 const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev); 893 894 #endif /* _DPU_HW_CATALOG_H */ 895