1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_HW_CATALOG_H 8 #define _DPU_HW_CATALOG_H 9 10 #include <linux/kernel.h> 11 #include <linux/bug.h> 12 #include <linux/bitmap.h> 13 #include <linux/err.h> 14 15 /** 16 * Max hardware block count: For ex: max 12 SSPP pipes or 17 * 5 ctl paths. In all cases, it can have max 12 hardware blocks 18 * based on current design 19 */ 20 #define MAX_BLOCKS 12 21 22 #define DPU_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28) |\ 23 ((MINOR & 0xFFF) << 16) |\ 24 (STEP & 0xFFFF)) 25 26 #define DPU_HW_MAJOR(rev) ((rev) >> 28) 27 #define DPU_HW_MINOR(rev) (((rev) >> 16) & 0xFFF) 28 #define DPU_HW_STEP(rev) ((rev) & 0xFFFF) 29 #define DPU_HW_MAJOR_MINOR(rev) ((rev) >> 16) 30 31 #define IS_DPU_MAJOR_MINOR_SAME(rev1, rev2) \ 32 (DPU_HW_MAJOR_MINOR((rev1)) == DPU_HW_MAJOR_MINOR((rev2))) 33 34 #define DPU_HW_VER_170 DPU_HW_VER(1, 7, 0) /* 8996 v1.0 */ 35 #define DPU_HW_VER_171 DPU_HW_VER(1, 7, 1) /* 8996 v2.0 */ 36 #define DPU_HW_VER_172 DPU_HW_VER(1, 7, 2) /* 8996 v3.0 */ 37 #define DPU_HW_VER_300 DPU_HW_VER(3, 0, 0) /* 8998 v1.0 */ 38 #define DPU_HW_VER_301 DPU_HW_VER(3, 0, 1) /* 8998 v1.1 */ 39 #define DPU_HW_VER_400 DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */ 40 #define DPU_HW_VER_401 DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */ 41 #define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */ 42 #define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sm8150 v1.0 */ 43 #define DPU_HW_VER_501 DPU_HW_VER(5, 0, 1) /* sm8150 v2.0 */ 44 #define DPU_HW_VER_510 DPU_HW_VER(5, 1, 1) /* sc8180 */ 45 #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */ 46 #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ 47 #define DPU_HW_VER_650 DPU_HW_VER(6, 5, 0) /* qcm2290|sm4125 */ 48 #define DPU_HW_VER_720 DPU_HW_VER(7, 2, 0) /* sc7280 */ 49 50 #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) 51 #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) 52 #define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400) 53 #define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410) 54 #define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500) 55 #define IS_SC7180_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_620) 56 #define IS_SC7280_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_720) 57 58 #define DPU_HW_BLK_NAME_LEN 16 59 60 #define MAX_IMG_WIDTH 0x3fff 61 #define MAX_IMG_HEIGHT 0x3fff 62 63 #define CRTC_DUAL_MIXERS 2 64 65 #define MAX_XIN_COUNT 16 66 67 /** 68 * Supported UBWC feature versions 69 */ 70 enum { 71 DPU_HW_UBWC_VER_10 = 0x100, 72 DPU_HW_UBWC_VER_20 = 0x200, 73 DPU_HW_UBWC_VER_30 = 0x300, 74 DPU_HW_UBWC_VER_40 = 0x400, 75 }; 76 77 /** 78 * MDP TOP BLOCK features 79 * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe 80 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats 81 * @DPU_MDP_BWC, MDSS HW supports Bandwidth compression. 82 * @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth 83 * compression initial revision 84 * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 85 * @DPU_MDP_MAX Maximum value 86 87 */ 88 enum { 89 DPU_MDP_PANIC_PER_PIPE = 0x1, 90 DPU_MDP_10BIT_SUPPORT, 91 DPU_MDP_BWC, 92 DPU_MDP_UBWC_1_0, 93 DPU_MDP_UBWC_1_5, 94 DPU_MDP_AUDIO_SELECT, 95 DPU_MDP_MAX 96 }; 97 98 /** 99 * SSPP sub-blocks/features 100 * @DPU_SSPP_SRC Src and fetch part of the pipes, 101 * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support 102 * @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support 103 * @DPU_SSPP_SCALER_QSEED3LITE, QSEED3 Lite alogorithm support 104 * @DPU_SSPP_SCALER_QSEED4, QSEED4 algorithm support 105 * @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes 106 * @DPU_SSPP_CSC, Support of Color space converion 107 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion 108 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer 109 * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq 110 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control 111 * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect 112 * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support 113 * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support 114 * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper 115 * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec 116 * @DPU_SSPP_CDP Supports client driven prefetch 117 * @DPU_SSPP_INLINE_ROTATION Support inline rotation 118 * @DPU_SSPP_MAX maximum value 119 */ 120 enum { 121 DPU_SSPP_SRC = 0x1, 122 DPU_SSPP_SCALER_QSEED2, 123 DPU_SSPP_SCALER_QSEED3, 124 DPU_SSPP_SCALER_QSEED3LITE, 125 DPU_SSPP_SCALER_QSEED4, 126 DPU_SSPP_SCALER_RGB, 127 DPU_SSPP_CSC, 128 DPU_SSPP_CSC_10BIT, 129 DPU_SSPP_CURSOR, 130 DPU_SSPP_QOS, 131 DPU_SSPP_QOS_8LVL, 132 DPU_SSPP_EXCL_RECT, 133 DPU_SSPP_SMART_DMA_V1, 134 DPU_SSPP_SMART_DMA_V2, 135 DPU_SSPP_TS_PREFILL, 136 DPU_SSPP_TS_PREFILL_REC1, 137 DPU_SSPP_CDP, 138 DPU_SSPP_INLINE_ROTATION, 139 DPU_SSPP_MAX 140 }; 141 142 /* 143 * MIXER sub-blocks/features 144 * @DPU_MIXER_LAYER Layer mixer layer blend configuration, 145 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration 146 * @DPU_MIXER_GC Gamma correction block 147 * @DPU_DIM_LAYER Layer mixer supports dim layer 148 * @DPU_MIXER_COMBINED_ALPHA Layer mixer has combined alpha register 149 * @DPU_MIXER_MAX maximum value 150 */ 151 enum { 152 DPU_MIXER_LAYER = 0x1, 153 DPU_MIXER_SOURCESPLIT, 154 DPU_MIXER_GC, 155 DPU_DIM_LAYER, 156 DPU_MIXER_COMBINED_ALPHA, 157 DPU_MIXER_MAX 158 }; 159 160 /** 161 * DSPP sub-blocks 162 * @DPU_DSPP_PCC Panel color correction block 163 * @DPU_DSPP_GC Gamma correction block 164 */ 165 enum { 166 DPU_DSPP_PCC = 0x1, 167 DPU_DSPP_GC, 168 DPU_DSPP_MAX 169 }; 170 171 /** 172 * PINGPONG sub-blocks 173 * @DPU_PINGPONG_TE Tear check block 174 * @DPU_PINGPONG_TE2 Additional tear check block for split pipes 175 * @DPU_PINGPONG_SPLIT PP block supports split fifo 176 * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo 177 * @DPU_PINGPONG_DITHER, Dither blocks 178 * @DPU_PINGPONG_MAX 179 */ 180 enum { 181 DPU_PINGPONG_TE = 0x1, 182 DPU_PINGPONG_TE2, 183 DPU_PINGPONG_SPLIT, 184 DPU_PINGPONG_SLAVE, 185 DPU_PINGPONG_DITHER, 186 DPU_PINGPONG_MAX 187 }; 188 189 /** 190 * CTL sub-blocks 191 * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display 192 * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) 193 * @DPU_CTL_VM_CFG: CTL config to support multiple VMs 194 * @DPU_CTL_MAX 195 */ 196 enum { 197 DPU_CTL_SPLIT_DISPLAY = 0x1, 198 DPU_CTL_ACTIVE_CFG, 199 DPU_CTL_FETCH_ACTIVE, 200 DPU_CTL_VM_CFG, 201 DPU_CTL_MAX 202 }; 203 204 /** 205 * INTF sub-blocks 206 * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which 207 * pixel data arrives to this INTF 208 * @DPU_INTF_TE INTF block has TE configuration support 209 * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate 210 than video timing 211 * @DPU_INTF_MAX 212 */ 213 enum { 214 DPU_INTF_INPUT_CTRL = 0x1, 215 DPU_INTF_TE, 216 DPU_DATA_HCTL_EN, 217 DPU_INTF_MAX 218 }; 219 220 /** 221 * WB sub-blocks and features 222 * @DPU_WB_LINE_MODE Writeback module supports line/linear mode 223 * @DPU_WB_BLOCK_MODE Writeback module supports block mode read 224 * @DPU_WB_CHROMA_DOWN, Writeback chroma down block, 225 * @DPU_WB_DOWNSCALE, Writeback integer downscaler, 226 * @DPU_WB_DITHER, Dither block 227 * @DPU_WB_TRAFFIC_SHAPER, Writeback traffic shaper bloc 228 * @DPU_WB_UBWC, Writeback Universal bandwidth compression 229 * @DPU_WB_YUV_CONFIG Writeback supports output of YUV colorspace 230 * @DPU_WB_PIPE_ALPHA Writeback supports pipe alpha 231 * @DPU_WB_XY_ROI_OFFSET Writeback supports x/y-offset of out ROI in 232 * the destination image 233 * @DPU_WB_QOS, Writeback supports QoS control, danger/safe/creq 234 * @DPU_WB_QOS_8LVL, Writeback supports 8-level QoS control 235 * @DPU_WB_CDP Writeback supports client driven prefetch 236 * @DPU_WB_INPUT_CTRL Writeback supports from which pp block input pixel 237 * data arrives. 238 * @DPU_WB_CROP CWB supports cropping 239 * @DPU_WB_MAX maximum value 240 */ 241 enum { 242 DPU_WB_LINE_MODE = 0x1, 243 DPU_WB_BLOCK_MODE, 244 DPU_WB_UBWC, 245 DPU_WB_YUV_CONFIG, 246 DPU_WB_PIPE_ALPHA, 247 DPU_WB_XY_ROI_OFFSET, 248 DPU_WB_QOS, 249 DPU_WB_QOS_8LVL, 250 DPU_WB_CDP, 251 DPU_WB_INPUT_CTRL, 252 DPU_WB_CROP, 253 DPU_WB_MAX 254 }; 255 256 /** 257 * VBIF sub-blocks and features 258 * @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit 259 * @DPU_VBIF_QOS_REMAP VBIF supports QoS priority remap 260 * @DPU_VBIF_MAX maximum value 261 */ 262 enum { 263 DPU_VBIF_QOS_OTLIM = 0x1, 264 DPU_VBIF_QOS_REMAP, 265 DPU_VBIF_MAX 266 }; 267 268 /** 269 * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU 270 * @name: string name for debug purposes 271 * @id: enum identifying this block 272 * @base: register base offset to mdss 273 * @len: length of hardware block 274 * @features bit mask identifying sub-blocks/features 275 */ 276 #define DPU_HW_BLK_INFO \ 277 char name[DPU_HW_BLK_NAME_LEN]; \ 278 u32 id; \ 279 u32 base; \ 280 u32 len; \ 281 unsigned long features 282 283 /** 284 * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU 285 * @name: string name for debug purposes 286 * @id: enum identifying this sub-block 287 * @base: offset of this sub-block relative to the block 288 * offset 289 * @len register block length of this sub-block 290 */ 291 #define DPU_HW_SUBBLK_INFO \ 292 char name[DPU_HW_BLK_NAME_LEN]; \ 293 u32 id; \ 294 u32 base; \ 295 u32 len 296 297 /** 298 * struct dpu_src_blk: SSPP part of the source pipes 299 * @info: HW register and features supported by this sub-blk 300 */ 301 struct dpu_src_blk { 302 DPU_HW_SUBBLK_INFO; 303 }; 304 305 /** 306 * struct dpu_scaler_blk: Scaler information 307 * @info: HW register and features supported by this sub-blk 308 * @version: qseed block revision 309 */ 310 struct dpu_scaler_blk { 311 DPU_HW_SUBBLK_INFO; 312 u32 version; 313 }; 314 315 struct dpu_csc_blk { 316 DPU_HW_SUBBLK_INFO; 317 }; 318 319 /** 320 * struct dpu_pp_blk : Pixel processing sub-blk information 321 * @info: HW register and features supported by this sub-blk 322 * @version: HW Algorithm version 323 */ 324 struct dpu_pp_blk { 325 DPU_HW_SUBBLK_INFO; 326 u32 version; 327 }; 328 329 /** 330 * enum dpu_qos_lut_usage - define QoS LUT use cases 331 */ 332 enum dpu_qos_lut_usage { 333 DPU_QOS_LUT_USAGE_LINEAR, 334 DPU_QOS_LUT_USAGE_MACROTILE, 335 DPU_QOS_LUT_USAGE_NRT, 336 DPU_QOS_LUT_USAGE_MAX, 337 }; 338 339 /** 340 * struct dpu_qos_lut_entry - define QoS LUT table entry 341 * @fl: fill level, or zero on last entry to indicate default lut 342 * @lut: lut to use if equal to or less than fill level 343 */ 344 struct dpu_qos_lut_entry { 345 u32 fl; 346 u64 lut; 347 }; 348 349 /** 350 * struct dpu_qos_lut_tbl - define QoS LUT table 351 * @nentry: number of entry in this table 352 * @entries: Pointer to table entries 353 */ 354 struct dpu_qos_lut_tbl { 355 u32 nentry; 356 const struct dpu_qos_lut_entry *entries; 357 }; 358 359 /** 360 * struct dpu_rotation_cfg - define inline rotation config 361 * @rot_maxheight: max pre rotated height allowed for rotation 362 * @rot_num_formats: number of elements in @rot_format_list 363 * @rot_format_list: list of supported rotator formats 364 */ 365 struct dpu_rotation_cfg { 366 u32 rot_maxheight; 367 size_t rot_num_formats; 368 const u32 *rot_format_list; 369 }; 370 371 /** 372 * struct dpu_caps - define DPU capabilities 373 * @max_mixer_width max layer mixer line width support. 374 * @max_mixer_blendstages max layer mixer blend stages or 375 * supported z order 376 * @qseed_type qseed2 or qseed3 support. 377 * @smart_dma_rev Supported version of SmartDMA feature. 378 * @ubwc_version UBWC feature version (0x0 for not supported) 379 * @has_src_split source split feature status 380 * @has_dim_layer dim layer feature status 381 * @has_idle_pc indicate if idle power collapse feature is supported 382 * @has_3d_merge indicate if 3D merge is supported 383 * @max_linewidth max linewidth for sspp 384 * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes 385 * @max_hdeci_exp max horizontal decimation supported (max is 2^value) 386 * @max_vdeci_exp max vertical decimation supported (max is 2^value) 387 */ 388 struct dpu_caps { 389 u32 max_mixer_width; 390 u32 max_mixer_blendstages; 391 u32 qseed_type; 392 u32 smart_dma_rev; 393 u32 ubwc_version; 394 bool has_src_split; 395 bool has_dim_layer; 396 bool has_idle_pc; 397 bool has_3d_merge; 398 /* SSPP limits */ 399 u32 max_linewidth; 400 u32 pixel_ram_size; 401 u32 max_hdeci_exp; 402 u32 max_vdeci_exp; 403 }; 404 405 /** 406 * struct dpu_sspp_sub_blks : SSPP sub-blocks 407 * common: Pointer to common configurations shared by sub blocks 408 * @creq_vblank: creq priority during vertical blanking 409 * @danger_vblank: danger priority during vertical blanking 410 * @maxdwnscale: max downscale ratio supported(without DECIMATION) 411 * @maxupscale: maxupscale ratio supported 412 * @smart_dma_priority: hw priority of rect1 of multirect pipe 413 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps 414 * @qseed_ver: qseed version 415 * @src_blk: 416 * @scaler_blk: 417 * @csc_blk: 418 * @hsic: 419 * @memcolor: 420 * @pcc_blk: 421 * @igc_blk: 422 * @format_list: Pointer to list of supported formats 423 * @num_formats: Number of supported formats 424 * @virt_format_list: Pointer to list of supported formats for virtual planes 425 * @virt_num_formats: Number of supported formats for virtual planes 426 * @dpu_rotation_cfg: inline rotation configuration 427 */ 428 struct dpu_sspp_sub_blks { 429 u32 creq_vblank; 430 u32 danger_vblank; 431 u32 maxdwnscale; 432 u32 maxupscale; 433 u32 smart_dma_priority; 434 u32 max_per_pipe_bw; 435 u32 qseed_ver; 436 struct dpu_src_blk src_blk; 437 struct dpu_scaler_blk scaler_blk; 438 struct dpu_pp_blk csc_blk; 439 struct dpu_pp_blk hsic_blk; 440 struct dpu_pp_blk memcolor_blk; 441 struct dpu_pp_blk pcc_blk; 442 struct dpu_pp_blk igc_blk; 443 444 const u32 *format_list; 445 u32 num_formats; 446 const u32 *virt_format_list; 447 u32 virt_num_formats; 448 const struct dpu_rotation_cfg *rotation_cfg; 449 }; 450 451 /** 452 * struct dpu_lm_sub_blks: information of mixer block 453 * @maxwidth: Max pixel width supported by this mixer 454 * @maxblendstages: Max number of blend-stages supported 455 * @blendstage_base: Blend-stage register base offset 456 * @gc: gamma correction block 457 */ 458 struct dpu_lm_sub_blks { 459 u32 maxwidth; 460 u32 maxblendstages; 461 u32 blendstage_base[MAX_BLOCKS]; 462 struct dpu_pp_blk gc; 463 }; 464 465 /** 466 * struct dpu_dspp_sub_blks: Information of DSPP block 467 * @gc : gamma correction block 468 * @pcc: pixel color correction block 469 */ 470 struct dpu_dspp_sub_blks { 471 struct dpu_pp_blk gc; 472 struct dpu_pp_blk pcc; 473 }; 474 475 struct dpu_pingpong_sub_blks { 476 struct dpu_pp_blk te; 477 struct dpu_pp_blk te2; 478 struct dpu_pp_blk dither; 479 }; 480 481 /** 482 * dpu_clk_ctrl_type - Defines top level clock control signals 483 */ 484 enum dpu_clk_ctrl_type { 485 DPU_CLK_CTRL_NONE, 486 DPU_CLK_CTRL_VIG0, 487 DPU_CLK_CTRL_VIG1, 488 DPU_CLK_CTRL_VIG2, 489 DPU_CLK_CTRL_VIG3, 490 DPU_CLK_CTRL_VIG4, 491 DPU_CLK_CTRL_RGB0, 492 DPU_CLK_CTRL_RGB1, 493 DPU_CLK_CTRL_RGB2, 494 DPU_CLK_CTRL_RGB3, 495 DPU_CLK_CTRL_DMA0, 496 DPU_CLK_CTRL_DMA1, 497 DPU_CLK_CTRL_DMA2, 498 DPU_CLK_CTRL_DMA3, 499 DPU_CLK_CTRL_CURSOR0, 500 DPU_CLK_CTRL_CURSOR1, 501 DPU_CLK_CTRL_INLINE_ROT0_SSPP, 502 DPU_CLK_CTRL_REG_DMA, 503 DPU_CLK_CTRL_WB2, 504 DPU_CLK_CTRL_MAX, 505 }; 506 507 /* struct dpu_clk_ctrl_reg : Clock control register 508 * @reg_off: register offset 509 * @bit_off: bit offset 510 */ 511 struct dpu_clk_ctrl_reg { 512 u32 reg_off; 513 u32 bit_off; 514 }; 515 516 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info 517 * @id: index identifying this block 518 * @base: register base offset to mdss 519 * @features bit mask identifying sub-blocks/features 520 * @highest_bank_bit: UBWC parameter 521 * @ubwc_static: ubwc static configuration 522 * @ubwc_swizzle: ubwc default swizzle setting 523 * @clk_ctrls clock control register definition 524 */ 525 struct dpu_mdp_cfg { 526 DPU_HW_BLK_INFO; 527 u32 highest_bank_bit; 528 u32 ubwc_swizzle; 529 struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; 530 }; 531 532 /* struct dpu_ctl_cfg : MDP CTL instance info 533 * @id: index identifying this block 534 * @base: register base offset to mdss 535 * @features bit mask identifying sub-blocks/features 536 * @intr_start: interrupt index for CTL_START 537 */ 538 struct dpu_ctl_cfg { 539 DPU_HW_BLK_INFO; 540 s32 intr_start; 541 }; 542 543 /** 544 * struct dpu_sspp_cfg - information of source pipes 545 * @id: index identifying this block 546 * @base register offset of this block 547 * @features bit mask identifying sub-blocks/features 548 * @sblk: SSPP sub-blocks information 549 * @xin_id: bus client identifier 550 * @clk_ctrl clock control identifier 551 * @type sspp type identifier 552 */ 553 struct dpu_sspp_cfg { 554 DPU_HW_BLK_INFO; 555 const struct dpu_sspp_sub_blks *sblk; 556 u32 xin_id; 557 enum dpu_clk_ctrl_type clk_ctrl; 558 u32 type; 559 }; 560 561 /** 562 * struct dpu_lm_cfg - information of layer mixer blocks 563 * @id: index identifying this block 564 * @base register offset of this block 565 * @features bit mask identifying sub-blocks/features 566 * @sblk: LM Sub-blocks information 567 * @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported 568 * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL 569 */ 570 struct dpu_lm_cfg { 571 DPU_HW_BLK_INFO; 572 const struct dpu_lm_sub_blks *sblk; 573 u32 pingpong; 574 u32 dspp; 575 unsigned long lm_pair_mask; 576 }; 577 578 /** 579 * struct dpu_dspp_cfg - information of DSPP blocks 580 * @id enum identifying this block 581 * @base register offset of this block 582 * @features bit mask identifying sub-blocks/features 583 * supported by this block 584 * @sblk sub-blocks information 585 */ 586 struct dpu_dspp_cfg { 587 DPU_HW_BLK_INFO; 588 const struct dpu_dspp_sub_blks *sblk; 589 }; 590 591 /** 592 * struct dpu_pingpong_cfg - information of PING-PONG blocks 593 * @id enum identifying this block 594 * @base register offset of this block 595 * @features bit mask identifying sub-blocks/features 596 * @intr_done: index for PINGPONG done interrupt 597 * @intr_rdptr: index for PINGPONG readpointer done interrupt 598 * @sblk sub-blocks information 599 */ 600 struct dpu_pingpong_cfg { 601 DPU_HW_BLK_INFO; 602 u32 merge_3d; 603 s32 intr_done; 604 s32 intr_rdptr; 605 const struct dpu_pingpong_sub_blks *sblk; 606 }; 607 608 /** 609 * struct dpu_merge_3d_cfg - information of DSPP blocks 610 * @id enum identifying this block 611 * @base register offset of this block 612 * @features bit mask identifying sub-blocks/features 613 * supported by this block 614 * @sblk sub-blocks information 615 */ 616 struct dpu_merge_3d_cfg { 617 DPU_HW_BLK_INFO; 618 const struct dpu_merge_3d_sub_blks *sblk; 619 }; 620 621 /** 622 * struct dpu_dsc_cfg - information of DSC blocks 623 * @id enum identifying this block 624 * @base register offset of this block 625 * @features bit mask identifying sub-blocks/features 626 */ 627 struct dpu_dsc_cfg { 628 DPU_HW_BLK_INFO; 629 }; 630 631 /** 632 * struct dpu_intf_cfg - information of timing engine blocks 633 * @id enum identifying this block 634 * @base register offset of this block 635 * @features bit mask identifying sub-blocks/features 636 * @type: Interface type(DSI, DP, HDMI) 637 * @controller_id: Controller Instance ID in case of multiple of intf type 638 * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch 639 * @intr_underrun: index for INTF underrun interrupt 640 * @intr_vsync: index for INTF VSYNC interrupt 641 */ 642 struct dpu_intf_cfg { 643 DPU_HW_BLK_INFO; 644 u32 type; /* interface type*/ 645 u32 controller_id; 646 u32 prog_fetch_lines_worst_case; 647 s32 intr_underrun; 648 s32 intr_vsync; 649 }; 650 651 /** 652 * struct dpu_wb_cfg - information of writeback blocks 653 * @DPU_HW_BLK_INFO: refer to the description above for DPU_HW_BLK_INFO 654 * @vbif_idx: vbif client index 655 * @maxlinewidth: max line width supported by writeback block 656 * @xin_id: bus client identifier 657 * @intr_wb_done: interrupt index for WB_DONE 658 * @format_list: list of formats supported by this writeback block 659 * @num_formats: number of formats supported by this writeback block 660 * @clk_ctrl: clock control identifier 661 */ 662 struct dpu_wb_cfg { 663 DPU_HW_BLK_INFO; 664 u8 vbif_idx; 665 u32 maxlinewidth; 666 u32 xin_id; 667 s32 intr_wb_done; 668 const u32 *format_list; 669 u32 num_formats; 670 enum dpu_clk_ctrl_type clk_ctrl; 671 }; 672 673 /** 674 * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting 675 * @pps pixel per seconds 676 * @ot_limit OT limit to use up to specified pixel per second 677 */ 678 struct dpu_vbif_dynamic_ot_cfg { 679 u64 pps; 680 u32 ot_limit; 681 }; 682 683 /** 684 * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table 685 * @count length of cfg 686 * @cfg pointer to array of configuration settings with 687 * ascending requirements 688 */ 689 struct dpu_vbif_dynamic_ot_tbl { 690 u32 count; 691 const struct dpu_vbif_dynamic_ot_cfg *cfg; 692 }; 693 694 /** 695 * struct dpu_vbif_qos_tbl - QoS priority table 696 * @npriority_lvl num of priority level 697 * @priority_lvl pointer to array of priority level in ascending order 698 */ 699 struct dpu_vbif_qos_tbl { 700 u32 npriority_lvl; 701 const u32 *priority_lvl; 702 }; 703 704 /** 705 * struct dpu_vbif_cfg - information of VBIF blocks 706 * @id enum identifying this block 707 * @base register offset of this block 708 * @features bit mask identifying sub-blocks/features 709 * @ot_rd_limit default OT read limit 710 * @ot_wr_limit default OT write limit 711 * @xin_halt_timeout maximum time (in usec) for xin to halt 712 * @qos_rp_remap_size size of VBIF_XINL_QOS_RP_REMAP register space 713 * @dynamic_ot_rd_tbl dynamic OT read configuration table 714 * @dynamic_ot_wr_tbl dynamic OT write configuration table 715 * @qos_rt_tbl real-time QoS priority table 716 * @qos_nrt_tbl non-real-time QoS priority table 717 * @memtype_count number of defined memtypes 718 * @memtype array of xin memtype definitions 719 */ 720 struct dpu_vbif_cfg { 721 DPU_HW_BLK_INFO; 722 u32 default_ot_rd_limit; 723 u32 default_ot_wr_limit; 724 u32 xin_halt_timeout; 725 u32 qos_rp_remap_size; 726 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl; 727 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl; 728 struct dpu_vbif_qos_tbl qos_rt_tbl; 729 struct dpu_vbif_qos_tbl qos_nrt_tbl; 730 u32 memtype_count; 731 u32 memtype[MAX_XIN_COUNT]; 732 }; 733 /** 734 * struct dpu_reg_dma_cfg - information of lut dma blocks 735 * @id enum identifying this block 736 * @base register offset of this block 737 * @features bit mask identifying sub-blocks/features 738 * @version version of lutdma hw block 739 * @trigger_sel_off offset to trigger select registers of lutdma 740 */ 741 struct dpu_reg_dma_cfg { 742 DPU_HW_BLK_INFO; 743 u32 version; 744 u32 trigger_sel_off; 745 u32 xin_id; 746 enum dpu_clk_ctrl_type clk_ctrl; 747 }; 748 749 /** 750 * Define CDP use cases 751 * @DPU_PERF_CDP_UDAGE_RT: real-time use cases 752 * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD 753 */ 754 enum { 755 DPU_PERF_CDP_USAGE_RT, 756 DPU_PERF_CDP_USAGE_NRT, 757 DPU_PERF_CDP_USAGE_MAX 758 }; 759 760 /** 761 * struct dpu_perf_cdp_cfg - define CDP use case configuration 762 * @rd_enable: true if read pipe CDP is enabled 763 * @wr_enable: true if write pipe CDP is enabled 764 */ 765 struct dpu_perf_cdp_cfg { 766 bool rd_enable; 767 bool wr_enable; 768 }; 769 770 /** 771 * struct dpu_perf_cfg - performance control settings 772 * @max_bw_low low threshold of maximum bandwidth (kbps) 773 * @max_bw_high high threshold of maximum bandwidth (kbps) 774 * @min_core_ib minimum bandwidth for core (kbps) 775 * @min_core_ib minimum mnoc ib vote in kbps 776 * @min_llcc_ib minimum llcc ib vote in kbps 777 * @min_dram_ib minimum dram ib vote in kbps 778 * @undersized_prefill_lines undersized prefill in lines 779 * @xtra_prefill_lines extra prefill latency in lines 780 * @dest_scale_prefill_lines destination scaler latency in lines 781 * @macrotile_perfill_lines macrotile latency in lines 782 * @yuv_nv12_prefill_lines yuv_nv12 latency in lines 783 * @linear_prefill_lines linear latency in lines 784 * @downscaling_prefill_lines downscaling latency in lines 785 * @amortizable_theshold minimum y position for traffic shaping prefill 786 * @min_prefill_lines minimum pipeline latency in lines 787 * @clk_inefficiency_factor DPU src clock inefficiency factor 788 * @bw_inefficiency_factor DPU axi bus bw inefficiency factor 789 * @safe_lut_tbl: LUT tables for safe signals 790 * @danger_lut_tbl: LUT tables for danger signals 791 * @qos_lut_tbl: LUT tables for QoS signals 792 * @cdp_cfg cdp use case configurations 793 */ 794 struct dpu_perf_cfg { 795 u32 max_bw_low; 796 u32 max_bw_high; 797 u32 min_core_ib; 798 u32 min_llcc_ib; 799 u32 min_dram_ib; 800 u32 undersized_prefill_lines; 801 u32 xtra_prefill_lines; 802 u32 dest_scale_prefill_lines; 803 u32 macrotile_prefill_lines; 804 u32 yuv_nv12_prefill_lines; 805 u32 linear_prefill_lines; 806 u32 downscaling_prefill_lines; 807 u32 amortizable_threshold; 808 u32 min_prefill_lines; 809 u32 clk_inefficiency_factor; 810 u32 bw_inefficiency_factor; 811 u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 812 u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 813 struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 814 struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX]; 815 }; 816 817 /** 818 * struct dpu_mdss_cfg - information of MDSS HW 819 * This is the main catalog data structure representing 820 * this HW version. Contains number of instances, 821 * register offsets, capabilities of the all MDSS HW sub-blocks. 822 * 823 * @dma_formats Supported formats for dma pipe 824 * @cursor_formats Supported formats for cursor pipe 825 * @vig_formats Supported formats for vig pipe 826 * @mdss_irqs: Bitmap with the irqs supported by the target 827 */ 828 struct dpu_mdss_cfg { 829 const struct dpu_caps *caps; 830 831 u32 mdp_count; 832 const struct dpu_mdp_cfg *mdp; 833 834 u32 ctl_count; 835 const struct dpu_ctl_cfg *ctl; 836 837 u32 sspp_count; 838 const struct dpu_sspp_cfg *sspp; 839 840 u32 mixer_count; 841 const struct dpu_lm_cfg *mixer; 842 843 u32 pingpong_count; 844 const struct dpu_pingpong_cfg *pingpong; 845 846 u32 merge_3d_count; 847 const struct dpu_merge_3d_cfg *merge_3d; 848 849 u32 dsc_count; 850 struct dpu_dsc_cfg *dsc; 851 852 u32 intf_count; 853 const struct dpu_intf_cfg *intf; 854 855 u32 vbif_count; 856 const struct dpu_vbif_cfg *vbif; 857 858 u32 wb_count; 859 const struct dpu_wb_cfg *wb; 860 861 u32 reg_dma_count; 862 const struct dpu_reg_dma_cfg *dma_cfg; 863 864 u32 ad_count; 865 866 u32 dspp_count; 867 const struct dpu_dspp_cfg *dspp; 868 869 /* Add additional block data structures here */ 870 871 const struct dpu_perf_cfg *perf; 872 const struct dpu_format_extended *dma_formats; 873 const struct dpu_format_extended *cursor_formats; 874 const struct dpu_format_extended *vig_formats; 875 876 unsigned long mdss_irqs; 877 }; 878 879 struct dpu_mdss_hw_cfg_handler { 880 u32 hw_rev; 881 const struct dpu_mdss_cfg *dpu_cfg; 882 }; 883 884 /** 885 * dpu_hw_catalog_init - dpu hardware catalog init API retrieves 886 * hardcoded target specific catalog information in config structure 887 * @hw_rev: caller needs provide the hardware revision. 888 * 889 * Return: dpu config structure 890 */ 891 const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev); 892 893 #endif /* _DPU_HW_CATALOG_H */ 894