1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 */ 4 5 #ifndef _DPU_HW_CATALOG_H 6 #define _DPU_HW_CATALOG_H 7 8 #include <linux/kernel.h> 9 #include <linux/bug.h> 10 #include <linux/bitmap.h> 11 #include <linux/err.h> 12 13 /** 14 * Max hardware block count: For ex: max 12 SSPP pipes or 15 * 5 ctl paths. In all cases, it can have max 12 hardware blocks 16 * based on current design 17 */ 18 #define MAX_BLOCKS 12 19 20 #define DPU_HW_VER(MAJOR, MINOR, STEP) (((MAJOR & 0xF) << 28) |\ 21 ((MINOR & 0xFFF) << 16) |\ 22 (STEP & 0xFFFF)) 23 24 #define DPU_HW_MAJOR(rev) ((rev) >> 28) 25 #define DPU_HW_MINOR(rev) (((rev) >> 16) & 0xFFF) 26 #define DPU_HW_STEP(rev) ((rev) & 0xFFFF) 27 #define DPU_HW_MAJOR_MINOR(rev) ((rev) >> 16) 28 29 #define IS_DPU_MAJOR_MINOR_SAME(rev1, rev2) \ 30 (DPU_HW_MAJOR_MINOR((rev1)) == DPU_HW_MAJOR_MINOR((rev2))) 31 32 #define DPU_HW_VER_170 DPU_HW_VER(1, 7, 0) /* 8996 v1.0 */ 33 #define DPU_HW_VER_171 DPU_HW_VER(1, 7, 1) /* 8996 v2.0 */ 34 #define DPU_HW_VER_172 DPU_HW_VER(1, 7, 2) /* 8996 v3.0 */ 35 #define DPU_HW_VER_300 DPU_HW_VER(3, 0, 0) /* 8998 v1.0 */ 36 #define DPU_HW_VER_301 DPU_HW_VER(3, 0, 1) /* 8998 v1.1 */ 37 #define DPU_HW_VER_400 DPU_HW_VER(4, 0, 0) /* sdm845 v1.0 */ 38 #define DPU_HW_VER_401 DPU_HW_VER(4, 0, 1) /* sdm845 v2.0 */ 39 #define DPU_HW_VER_410 DPU_HW_VER(4, 1, 0) /* sdm670 v1.0 */ 40 #define DPU_HW_VER_500 DPU_HW_VER(5, 0, 0) /* sm8150 v1.0 */ 41 #define DPU_HW_VER_501 DPU_HW_VER(5, 0, 1) /* sm8150 v2.0 */ 42 #define DPU_HW_VER_600 DPU_HW_VER(6, 0, 0) /* sm8250 */ 43 #define DPU_HW_VER_620 DPU_HW_VER(6, 2, 0) /* sc7180 v1.0 */ 44 45 46 #define IS_MSM8996_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_170) 47 #define IS_MSM8998_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_300) 48 #define IS_SDM845_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_400) 49 #define IS_SDM670_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_410) 50 #define IS_SDM855_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_500) 51 #define IS_SC7180_TARGET(rev) IS_DPU_MAJOR_MINOR_SAME((rev), DPU_HW_VER_620) 52 53 54 #define DPU_HW_BLK_NAME_LEN 16 55 56 #define MAX_IMG_WIDTH 0x3fff 57 #define MAX_IMG_HEIGHT 0x3fff 58 59 #define CRTC_DUAL_MIXERS 2 60 61 #define MAX_XIN_COUNT 16 62 63 /** 64 * Supported UBWC feature versions 65 */ 66 enum { 67 DPU_HW_UBWC_VER_10 = 0x100, 68 DPU_HW_UBWC_VER_20 = 0x200, 69 DPU_HW_UBWC_VER_30 = 0x300, 70 DPU_HW_UBWC_VER_40 = 0x400, 71 }; 72 73 /** 74 * MDP TOP BLOCK features 75 * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be be done per pipe 76 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats 77 * @DPU_MDP_BWC, MDSS HW supports Bandwidth compression. 78 * @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth 79 * compression initial revision 80 * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 81 * @DPU_MDP_MAX Maximum value 82 83 */ 84 enum { 85 DPU_MDP_PANIC_PER_PIPE = 0x1, 86 DPU_MDP_10BIT_SUPPORT, 87 DPU_MDP_BWC, 88 DPU_MDP_UBWC_1_0, 89 DPU_MDP_UBWC_1_5, 90 DPU_MDP_MAX 91 }; 92 93 /** 94 * SSPP sub-blocks/features 95 * @DPU_SSPP_SRC Src and fetch part of the pipes, 96 * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support 97 * @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support 98 * @DPU_SSPP_SCALER_QSEED3LITE, QSEED3 Lite alogorithm support 99 * @DPU_SSPP_SCALER_QSEED4, QSEED4 algorithm support 100 * @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes 101 * @DPU_SSPP_CSC, Support of Color space converion 102 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion 103 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer 104 * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq 105 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control 106 * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect 107 * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support 108 * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support 109 * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper 110 * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec 111 * @DPU_SSPP_CDP Supports client driven prefetch 112 * @DPU_SSPP_MAX maximum value 113 */ 114 enum { 115 DPU_SSPP_SRC = 0x1, 116 DPU_SSPP_SCALER_QSEED2, 117 DPU_SSPP_SCALER_QSEED3, 118 DPU_SSPP_SCALER_QSEED3LITE, 119 DPU_SSPP_SCALER_QSEED4, 120 DPU_SSPP_SCALER_RGB, 121 DPU_SSPP_CSC, 122 DPU_SSPP_CSC_10BIT, 123 DPU_SSPP_CURSOR, 124 DPU_SSPP_QOS, 125 DPU_SSPP_QOS_8LVL, 126 DPU_SSPP_EXCL_RECT, 127 DPU_SSPP_SMART_DMA_V1, 128 DPU_SSPP_SMART_DMA_V2, 129 DPU_SSPP_TS_PREFILL, 130 DPU_SSPP_TS_PREFILL_REC1, 131 DPU_SSPP_CDP, 132 DPU_SSPP_MAX 133 }; 134 135 /* 136 * MIXER sub-blocks/features 137 * @DPU_MIXER_LAYER Layer mixer layer blend configuration, 138 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration 139 * @DPU_MIXER_GC Gamma correction block 140 * @DPU_DIM_LAYER Layer mixer supports dim layer 141 * @DPU_MIXER_MAX maximum value 142 */ 143 enum { 144 DPU_MIXER_LAYER = 0x1, 145 DPU_MIXER_SOURCESPLIT, 146 DPU_MIXER_GC, 147 DPU_DIM_LAYER, 148 DPU_MIXER_MAX 149 }; 150 151 /** 152 * DSPP sub-blocks 153 * @DPU_DSPP_PCC Panel color correction block 154 * @DPU_DSPP_GC Gamma correction block 155 */ 156 enum { 157 DPU_DSPP_PCC = 0x1, 158 DPU_DSPP_GC, 159 DPU_DSPP_MAX 160 }; 161 162 /** 163 * PINGPONG sub-blocks 164 * @DPU_PINGPONG_TE Tear check block 165 * @DPU_PINGPONG_TE2 Additional tear check block for split pipes 166 * @DPU_PINGPONG_SPLIT PP block supports split fifo 167 * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo 168 * @DPU_PINGPONG_DITHER, Dither blocks 169 * @DPU_PINGPONG_MAX 170 */ 171 enum { 172 DPU_PINGPONG_TE = 0x1, 173 DPU_PINGPONG_TE2, 174 DPU_PINGPONG_SPLIT, 175 DPU_PINGPONG_SLAVE, 176 DPU_PINGPONG_DITHER, 177 DPU_PINGPONG_MAX 178 }; 179 180 /** 181 * CTL sub-blocks 182 * @DPU_CTL_SPLIT_DISPLAY CTL supports video mode split display 183 * @DPU_CTL_MAX 184 */ 185 enum { 186 DPU_CTL_SPLIT_DISPLAY = 0x1, 187 DPU_CTL_ACTIVE_CFG, 188 DPU_CTL_MAX 189 }; 190 191 /** 192 * INTF sub-blocks 193 * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which 194 * pixel data arrives to this INTF 195 * @DPU_INTF_TE INTF block has TE configuration support 196 * @DPU_INTF_MAX 197 */ 198 enum { 199 DPU_INTF_INPUT_CTRL = 0x1, 200 DPU_INTF_TE, 201 DPU_INTF_MAX 202 }; 203 204 /** 205 * VBIF sub-blocks and features 206 * @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit 207 * @DPU_VBIF_QOS_REMAP VBIF supports QoS priority remap 208 * @DPU_VBIF_MAX maximum value 209 */ 210 enum { 211 DPU_VBIF_QOS_OTLIM = 0x1, 212 DPU_VBIF_QOS_REMAP, 213 DPU_VBIF_MAX 214 }; 215 216 /** 217 * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU 218 * @name: string name for debug purposes 219 * @id: enum identifying this block 220 * @base: register base offset to mdss 221 * @len: length of hardware block 222 * @features bit mask identifying sub-blocks/features 223 */ 224 #define DPU_HW_BLK_INFO \ 225 char name[DPU_HW_BLK_NAME_LEN]; \ 226 u32 id; \ 227 u32 base; \ 228 u32 len; \ 229 unsigned long features 230 231 /** 232 * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU 233 * @name: string name for debug purposes 234 * @id: enum identifying this sub-block 235 * @base: offset of this sub-block relative to the block 236 * offset 237 * @len register block length of this sub-block 238 */ 239 #define DPU_HW_SUBBLK_INFO \ 240 char name[DPU_HW_BLK_NAME_LEN]; \ 241 u32 id; \ 242 u32 base; \ 243 u32 len 244 245 /** 246 * struct dpu_src_blk: SSPP part of the source pipes 247 * @info: HW register and features supported by this sub-blk 248 */ 249 struct dpu_src_blk { 250 DPU_HW_SUBBLK_INFO; 251 }; 252 253 /** 254 * struct dpu_scaler_blk: Scaler information 255 * @info: HW register and features supported by this sub-blk 256 * @version: qseed block revision 257 */ 258 struct dpu_scaler_blk { 259 DPU_HW_SUBBLK_INFO; 260 u32 version; 261 }; 262 263 struct dpu_csc_blk { 264 DPU_HW_SUBBLK_INFO; 265 }; 266 267 /** 268 * struct dpu_pp_blk : Pixel processing sub-blk information 269 * @info: HW register and features supported by this sub-blk 270 * @version: HW Algorithm version 271 */ 272 struct dpu_pp_blk { 273 DPU_HW_SUBBLK_INFO; 274 u32 version; 275 }; 276 277 /** 278 * enum dpu_qos_lut_usage - define QoS LUT use cases 279 */ 280 enum dpu_qos_lut_usage { 281 DPU_QOS_LUT_USAGE_LINEAR, 282 DPU_QOS_LUT_USAGE_MACROTILE, 283 DPU_QOS_LUT_USAGE_NRT, 284 DPU_QOS_LUT_USAGE_MAX, 285 }; 286 287 /** 288 * struct dpu_qos_lut_entry - define QoS LUT table entry 289 * @fl: fill level, or zero on last entry to indicate default lut 290 * @lut: lut to use if equal to or less than fill level 291 */ 292 struct dpu_qos_lut_entry { 293 u32 fl; 294 u64 lut; 295 }; 296 297 /** 298 * struct dpu_qos_lut_tbl - define QoS LUT table 299 * @nentry: number of entry in this table 300 * @entries: Pointer to table entries 301 */ 302 struct dpu_qos_lut_tbl { 303 u32 nentry; 304 const struct dpu_qos_lut_entry *entries; 305 }; 306 307 /** 308 * struct dpu_caps - define DPU capabilities 309 * @max_mixer_width max layer mixer line width support. 310 * @max_mixer_blendstages max layer mixer blend stages or 311 * supported z order 312 * @qseed_type qseed2 or qseed3 support. 313 * @smart_dma_rev Supported version of SmartDMA feature. 314 * @ubwc_version UBWC feature version (0x0 for not supported) 315 * @has_src_split source split feature status 316 * @has_dim_layer dim layer feature status 317 * @has_idle_pc indicate if idle power collapse feature is supported 318 * @has_3d_merge indicate if 3D merge is supported 319 * @max_linewidth max linewidth for sspp 320 * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes 321 * @max_hdeci_exp max horizontal decimation supported (max is 2^value) 322 * @max_vdeci_exp max vertical decimation supported (max is 2^value) 323 */ 324 struct dpu_caps { 325 u32 max_mixer_width; 326 u32 max_mixer_blendstages; 327 u32 qseed_type; 328 u32 smart_dma_rev; 329 u32 ubwc_version; 330 bool has_src_split; 331 bool has_dim_layer; 332 bool has_idle_pc; 333 bool has_3d_merge; 334 /* SSPP limits */ 335 u32 max_linewidth; 336 u32 pixel_ram_size; 337 u32 max_hdeci_exp; 338 u32 max_vdeci_exp; 339 }; 340 341 /** 342 * struct dpu_sspp_sub_blks : SSPP sub-blocks 343 * common: Pointer to common configurations shared by sub blocks 344 * @creq_vblank: creq priority during vertical blanking 345 * @danger_vblank: danger priority during vertical blanking 346 * @maxdwnscale: max downscale ratio supported(without DECIMATION) 347 * @maxupscale: maxupscale ratio supported 348 * @smart_dma_priority: hw priority of rect1 of multirect pipe 349 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps 350 * @qseed_ver: qseed version 351 * @src_blk: 352 * @scaler_blk: 353 * @csc_blk: 354 * @hsic: 355 * @memcolor: 356 * @pcc_blk: 357 * @igc_blk: 358 * @format_list: Pointer to list of supported formats 359 * @num_formats: Number of supported formats 360 * @virt_format_list: Pointer to list of supported formats for virtual planes 361 * @virt_num_formats: Number of supported formats for virtual planes 362 */ 363 struct dpu_sspp_sub_blks { 364 u32 creq_vblank; 365 u32 danger_vblank; 366 u32 maxdwnscale; 367 u32 maxupscale; 368 u32 smart_dma_priority; 369 u32 max_per_pipe_bw; 370 u32 qseed_ver; 371 struct dpu_src_blk src_blk; 372 struct dpu_scaler_blk scaler_blk; 373 struct dpu_pp_blk csc_blk; 374 struct dpu_pp_blk hsic_blk; 375 struct dpu_pp_blk memcolor_blk; 376 struct dpu_pp_blk pcc_blk; 377 struct dpu_pp_blk igc_blk; 378 379 const u32 *format_list; 380 u32 num_formats; 381 const u32 *virt_format_list; 382 u32 virt_num_formats; 383 }; 384 385 /** 386 * struct dpu_lm_sub_blks: information of mixer block 387 * @maxwidth: Max pixel width supported by this mixer 388 * @maxblendstages: Max number of blend-stages supported 389 * @blendstage_base: Blend-stage register base offset 390 * @gc: gamma correction block 391 */ 392 struct dpu_lm_sub_blks { 393 u32 maxwidth; 394 u32 maxblendstages; 395 u32 blendstage_base[MAX_BLOCKS]; 396 struct dpu_pp_blk gc; 397 }; 398 399 /** 400 * struct dpu_dspp_sub_blks: Information of DSPP block 401 * @gc : gamma correction block 402 * @pcc: pixel color correction block 403 */ 404 struct dpu_dspp_sub_blks { 405 struct dpu_pp_blk gc; 406 struct dpu_pp_blk pcc; 407 }; 408 409 struct dpu_pingpong_sub_blks { 410 struct dpu_pp_blk te; 411 struct dpu_pp_blk te2; 412 struct dpu_pp_blk dither; 413 }; 414 415 /** 416 * dpu_clk_ctrl_type - Defines top level clock control signals 417 */ 418 enum dpu_clk_ctrl_type { 419 DPU_CLK_CTRL_NONE, 420 DPU_CLK_CTRL_VIG0, 421 DPU_CLK_CTRL_VIG1, 422 DPU_CLK_CTRL_VIG2, 423 DPU_CLK_CTRL_VIG3, 424 DPU_CLK_CTRL_VIG4, 425 DPU_CLK_CTRL_RGB0, 426 DPU_CLK_CTRL_RGB1, 427 DPU_CLK_CTRL_RGB2, 428 DPU_CLK_CTRL_RGB3, 429 DPU_CLK_CTRL_DMA0, 430 DPU_CLK_CTRL_DMA1, 431 DPU_CLK_CTRL_CURSOR0, 432 DPU_CLK_CTRL_CURSOR1, 433 DPU_CLK_CTRL_INLINE_ROT0_SSPP, 434 DPU_CLK_CTRL_REG_DMA, 435 DPU_CLK_CTRL_MAX, 436 }; 437 438 /* struct dpu_clk_ctrl_reg : Clock control register 439 * @reg_off: register offset 440 * @bit_off: bit offset 441 */ 442 struct dpu_clk_ctrl_reg { 443 u32 reg_off; 444 u32 bit_off; 445 }; 446 447 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info 448 * @id: index identifying this block 449 * @base: register base offset to mdss 450 * @features bit mask identifying sub-blocks/features 451 * @highest_bank_bit: UBWC parameter 452 * @ubwc_static: ubwc static configuration 453 * @ubwc_swizzle: ubwc default swizzle setting 454 * @clk_ctrls clock control register definition 455 */ 456 struct dpu_mdp_cfg { 457 DPU_HW_BLK_INFO; 458 u32 highest_bank_bit; 459 u32 ubwc_swizzle; 460 struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; 461 }; 462 463 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info 464 * @id: index identifying this block 465 * @base: register base offset to mdss 466 * @features bit mask identifying sub-blocks/features 467 */ 468 struct dpu_ctl_cfg { 469 DPU_HW_BLK_INFO; 470 }; 471 472 /** 473 * struct dpu_sspp_cfg - information of source pipes 474 * @id: index identifying this block 475 * @base register offset of this block 476 * @features bit mask identifying sub-blocks/features 477 * @sblk: SSPP sub-blocks information 478 * @xin_id: bus client identifier 479 * @clk_ctrl clock control identifier 480 * @type sspp type identifier 481 */ 482 struct dpu_sspp_cfg { 483 DPU_HW_BLK_INFO; 484 const struct dpu_sspp_sub_blks *sblk; 485 u32 xin_id; 486 enum dpu_clk_ctrl_type clk_ctrl; 487 u32 type; 488 }; 489 490 /** 491 * struct dpu_lm_cfg - information of layer mixer blocks 492 * @id: index identifying this block 493 * @base register offset of this block 494 * @features bit mask identifying sub-blocks/features 495 * @sblk: LM Sub-blocks information 496 * @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported 497 * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL 498 */ 499 struct dpu_lm_cfg { 500 DPU_HW_BLK_INFO; 501 const struct dpu_lm_sub_blks *sblk; 502 u32 pingpong; 503 u32 dspp; 504 unsigned long lm_pair_mask; 505 }; 506 507 /** 508 * struct dpu_dspp_cfg - information of DSPP blocks 509 * @id enum identifying this block 510 * @base register offset of this block 511 * @features bit mask identifying sub-blocks/features 512 * supported by this block 513 * @sblk sub-blocks information 514 */ 515 struct dpu_dspp_cfg { 516 DPU_HW_BLK_INFO; 517 const struct dpu_dspp_sub_blks *sblk; 518 }; 519 520 /** 521 * struct dpu_pingpong_cfg - information of PING-PONG blocks 522 * @id enum identifying this block 523 * @base register offset of this block 524 * @features bit mask identifying sub-blocks/features 525 * @sblk sub-blocks information 526 */ 527 struct dpu_pingpong_cfg { 528 DPU_HW_BLK_INFO; 529 u32 merge_3d; 530 const struct dpu_pingpong_sub_blks *sblk; 531 }; 532 533 /** 534 * struct dpu_merge_3d_cfg - information of DSPP blocks 535 * @id enum identifying this block 536 * @base register offset of this block 537 * @features bit mask identifying sub-blocks/features 538 * supported by this block 539 * @sblk sub-blocks information 540 */ 541 struct dpu_merge_3d_cfg { 542 DPU_HW_BLK_INFO; 543 const struct dpu_merge_3d_sub_blks *sblk; 544 }; 545 546 /** 547 * struct dpu_intf_cfg - information of timing engine blocks 548 * @id enum identifying this block 549 * @base register offset of this block 550 * @features bit mask identifying sub-blocks/features 551 * @type: Interface type(DSI, DP, HDMI) 552 * @controller_id: Controller Instance ID in case of multiple of intf type 553 * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch 554 */ 555 struct dpu_intf_cfg { 556 DPU_HW_BLK_INFO; 557 u32 type; /* interface type*/ 558 u32 controller_id; 559 u32 prog_fetch_lines_worst_case; 560 }; 561 562 /** 563 * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting 564 * @pps pixel per seconds 565 * @ot_limit OT limit to use up to specified pixel per second 566 */ 567 struct dpu_vbif_dynamic_ot_cfg { 568 u64 pps; 569 u32 ot_limit; 570 }; 571 572 /** 573 * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table 574 * @count length of cfg 575 * @cfg pointer to array of configuration settings with 576 * ascending requirements 577 */ 578 struct dpu_vbif_dynamic_ot_tbl { 579 u32 count; 580 const struct dpu_vbif_dynamic_ot_cfg *cfg; 581 }; 582 583 /** 584 * struct dpu_vbif_qos_tbl - QoS priority table 585 * @npriority_lvl num of priority level 586 * @priority_lvl pointer to array of priority level in ascending order 587 */ 588 struct dpu_vbif_qos_tbl { 589 u32 npriority_lvl; 590 const u32 *priority_lvl; 591 }; 592 593 /** 594 * struct dpu_vbif_cfg - information of VBIF blocks 595 * @id enum identifying this block 596 * @base register offset of this block 597 * @features bit mask identifying sub-blocks/features 598 * @ot_rd_limit default OT read limit 599 * @ot_wr_limit default OT write limit 600 * @xin_halt_timeout maximum time (in usec) for xin to halt 601 * @dynamic_ot_rd_tbl dynamic OT read configuration table 602 * @dynamic_ot_wr_tbl dynamic OT write configuration table 603 * @qos_rt_tbl real-time QoS priority table 604 * @qos_nrt_tbl non-real-time QoS priority table 605 * @memtype_count number of defined memtypes 606 * @memtype array of xin memtype definitions 607 */ 608 struct dpu_vbif_cfg { 609 DPU_HW_BLK_INFO; 610 u32 default_ot_rd_limit; 611 u32 default_ot_wr_limit; 612 u32 xin_halt_timeout; 613 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl; 614 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl; 615 struct dpu_vbif_qos_tbl qos_rt_tbl; 616 struct dpu_vbif_qos_tbl qos_nrt_tbl; 617 u32 memtype_count; 618 u32 memtype[MAX_XIN_COUNT]; 619 }; 620 /** 621 * struct dpu_reg_dma_cfg - information of lut dma blocks 622 * @id enum identifying this block 623 * @base register offset of this block 624 * @features bit mask identifying sub-blocks/features 625 * @version version of lutdma hw block 626 * @trigger_sel_off offset to trigger select registers of lutdma 627 */ 628 struct dpu_reg_dma_cfg { 629 DPU_HW_BLK_INFO; 630 u32 version; 631 u32 trigger_sel_off; 632 u32 xin_id; 633 enum dpu_clk_ctrl_type clk_ctrl; 634 }; 635 636 /** 637 * Define CDP use cases 638 * @DPU_PERF_CDP_UDAGE_RT: real-time use cases 639 * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD 640 */ 641 enum { 642 DPU_PERF_CDP_USAGE_RT, 643 DPU_PERF_CDP_USAGE_NRT, 644 DPU_PERF_CDP_USAGE_MAX 645 }; 646 647 /** 648 * struct dpu_perf_cdp_cfg - define CDP use case configuration 649 * @rd_enable: true if read pipe CDP is enabled 650 * @wr_enable: true if write pipe CDP is enabled 651 */ 652 struct dpu_perf_cdp_cfg { 653 bool rd_enable; 654 bool wr_enable; 655 }; 656 657 /** 658 * struct dpu_perf_cfg - performance control settings 659 * @max_bw_low low threshold of maximum bandwidth (kbps) 660 * @max_bw_high high threshold of maximum bandwidth (kbps) 661 * @min_core_ib minimum bandwidth for core (kbps) 662 * @min_core_ib minimum mnoc ib vote in kbps 663 * @min_llcc_ib minimum llcc ib vote in kbps 664 * @min_dram_ib minimum dram ib vote in kbps 665 * @core_ib_ff core instantaneous bandwidth fudge factor 666 * @core_clk_ff core clock fudge factor 667 * @comp_ratio_rt string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio> 668 * @comp_ratio_nrt string of 0 or more of <fourcc>/<ven>/<mod>/<comp ratio> 669 * @undersized_prefill_lines undersized prefill in lines 670 * @xtra_prefill_lines extra prefill latency in lines 671 * @dest_scale_prefill_lines destination scaler latency in lines 672 * @macrotile_perfill_lines macrotile latency in lines 673 * @yuv_nv12_prefill_lines yuv_nv12 latency in lines 674 * @linear_prefill_lines linear latency in lines 675 * @downscaling_prefill_lines downscaling latency in lines 676 * @amortizable_theshold minimum y position for traffic shaping prefill 677 * @min_prefill_lines minimum pipeline latency in lines 678 * @clk_inefficiency_factor DPU src clock inefficiency factor 679 * @bw_inefficiency_factor DPU axi bus bw inefficiency factor 680 * @safe_lut_tbl: LUT tables for safe signals 681 * @danger_lut_tbl: LUT tables for danger signals 682 * @qos_lut_tbl: LUT tables for QoS signals 683 * @cdp_cfg cdp use case configurations 684 */ 685 struct dpu_perf_cfg { 686 u32 max_bw_low; 687 u32 max_bw_high; 688 u32 min_core_ib; 689 u32 min_llcc_ib; 690 u32 min_dram_ib; 691 const char *core_ib_ff; 692 const char *core_clk_ff; 693 const char *comp_ratio_rt; 694 const char *comp_ratio_nrt; 695 u32 undersized_prefill_lines; 696 u32 xtra_prefill_lines; 697 u32 dest_scale_prefill_lines; 698 u32 macrotile_prefill_lines; 699 u32 yuv_nv12_prefill_lines; 700 u32 linear_prefill_lines; 701 u32 downscaling_prefill_lines; 702 u32 amortizable_threshold; 703 u32 min_prefill_lines; 704 u32 clk_inefficiency_factor; 705 u32 bw_inefficiency_factor; 706 u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 707 u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 708 struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 709 struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX]; 710 }; 711 712 /** 713 * struct dpu_mdss_cfg - information of MDSS HW 714 * This is the main catalog data structure representing 715 * this HW version. Contains number of instances, 716 * register offsets, capabilities of the all MDSS HW sub-blocks. 717 * 718 * @dma_formats Supported formats for dma pipe 719 * @cursor_formats Supported formats for cursor pipe 720 * @vig_formats Supported formats for vig pipe 721 * @mdss_irqs: Bitmap with the irqs supported by the target 722 */ 723 struct dpu_mdss_cfg { 724 u32 hwversion; 725 726 const struct dpu_caps *caps; 727 728 u32 mdp_count; 729 const struct dpu_mdp_cfg *mdp; 730 731 u32 ctl_count; 732 const struct dpu_ctl_cfg *ctl; 733 734 u32 sspp_count; 735 const struct dpu_sspp_cfg *sspp; 736 737 u32 mixer_count; 738 const struct dpu_lm_cfg *mixer; 739 740 u32 pingpong_count; 741 const struct dpu_pingpong_cfg *pingpong; 742 743 u32 merge_3d_count; 744 const struct dpu_merge_3d_cfg *merge_3d; 745 746 u32 intf_count; 747 const struct dpu_intf_cfg *intf; 748 749 u32 vbif_count; 750 const struct dpu_vbif_cfg *vbif; 751 752 u32 reg_dma_count; 753 struct dpu_reg_dma_cfg dma_cfg; 754 755 u32 ad_count; 756 757 u32 dspp_count; 758 const struct dpu_dspp_cfg *dspp; 759 760 /* Add additional block data structures here */ 761 762 struct dpu_perf_cfg perf; 763 const struct dpu_format_extended *dma_formats; 764 const struct dpu_format_extended *cursor_formats; 765 const struct dpu_format_extended *vig_formats; 766 767 unsigned long mdss_irqs; 768 }; 769 770 struct dpu_mdss_hw_cfg_handler { 771 u32 hw_rev; 772 void (*cfg_init)(struct dpu_mdss_cfg *dpu_cfg); 773 }; 774 775 /* 776 * Access Macros 777 */ 778 #define BLK_MDP(s) ((s)->mdp) 779 #define BLK_CTL(s) ((s)->ctl) 780 #define BLK_VIG(s) ((s)->vig) 781 #define BLK_RGB(s) ((s)->rgb) 782 #define BLK_DMA(s) ((s)->dma) 783 #define BLK_CURSOR(s) ((s)->cursor) 784 #define BLK_MIXER(s) ((s)->mixer) 785 #define BLK_PINGPONG(s) ((s)->pingpong) 786 #define BLK_INTF(s) ((s)->intf) 787 #define BLK_AD(s) ((s)->ad) 788 #define BLK_DSPP(s) ((s)->dspp) 789 #define BLK_MERGE3d(s) ((s)->merge_3d) 790 791 /** 792 * dpu_hw_catalog_init - dpu hardware catalog init API retrieves 793 * hardcoded target specific catalog information in config structure 794 * @hw_rev: caller needs provide the hardware revision. 795 * 796 * Return: dpu config structure 797 */ 798 struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev); 799 800 /** 801 * dpu_hw_catalog_deinit - dpu hardware catalog cleanup 802 * @dpu_cfg: pointer returned from init function 803 */ 804 void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg); 805 806 #endif /* _DPU_HW_CATALOG_H */ 807