1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_HW_CATALOG_H 8 #define _DPU_HW_CATALOG_H 9 10 #include <linux/kernel.h> 11 #include <linux/bug.h> 12 #include <linux/bitmap.h> 13 #include <linux/err.h> 14 15 /** 16 * Max hardware block count: For ex: max 12 SSPP pipes or 17 * 5 ctl paths. In all cases, it can have max 12 hardware blocks 18 * based on current design 19 */ 20 #define MAX_BLOCKS 12 21 22 #define DPU_HW_BLK_NAME_LEN 16 23 24 #define MAX_IMG_WIDTH 0x3fff 25 #define MAX_IMG_HEIGHT 0x3fff 26 27 #define CRTC_DUAL_MIXERS 2 28 29 #define MAX_XIN_COUNT 16 30 31 /** 32 * Supported UBWC feature versions 33 */ 34 enum { 35 DPU_HW_UBWC_VER_10 = 0x100, 36 DPU_HW_UBWC_VER_20 = 0x200, 37 DPU_HW_UBWC_VER_30 = 0x300, 38 DPU_HW_UBWC_VER_40 = 0x400, 39 }; 40 41 /** 42 * MDP TOP BLOCK features 43 * @DPU_MDP_PANIC_PER_PIPE Panic configuration needs to be done per pipe 44 * @DPU_MDP_10BIT_SUPPORT, Chipset supports 10 bit pixel formats 45 * @DPU_MDP_BWC, MDSS HW supports Bandwidth compression. 46 * @DPU_MDP_UBWC_1_0, This chipsets supports Universal Bandwidth 47 * compression initial revision 48 * @DPU_MDP_UBWC_1_5, Universal Bandwidth compression version 1.5 49 * @DPU_MDP_PERIPH_0_REMOVED Indicates that access to periph top0 block results 50 * in a failure 51 * @DPU_MDP_MAX Maximum value 52 53 */ 54 enum { 55 DPU_MDP_PANIC_PER_PIPE = 0x1, 56 DPU_MDP_10BIT_SUPPORT, 57 DPU_MDP_BWC, 58 DPU_MDP_UBWC_1_0, 59 DPU_MDP_UBWC_1_5, 60 DPU_MDP_AUDIO_SELECT, 61 DPU_MDP_PERIPH_0_REMOVED, 62 DPU_MDP_MAX 63 }; 64 65 /** 66 * SSPP sub-blocks/features 67 * @DPU_SSPP_SRC Src and fetch part of the pipes, 68 * @DPU_SSPP_SCALER_QSEED2, QSEED2 algorithm support 69 * @DPU_SSPP_SCALER_QSEED3, QSEED3 alogorithm support 70 * @DPU_SSPP_SCALER_QSEED3LITE, QSEED3 Lite alogorithm support 71 * @DPU_SSPP_SCALER_QSEED4, QSEED4 algorithm support 72 * @DPU_SSPP_SCALER_RGB, RGB Scaler, supported by RGB pipes 73 * @DPU_SSPP_CSC, Support of Color space converion 74 * @DPU_SSPP_CSC_10BIT, Support of 10-bit Color space conversion 75 * @DPU_SSPP_CURSOR, SSPP can be used as a cursor layer 76 * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq 77 * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control 78 * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect 79 * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support 80 * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support 81 * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper 82 * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec 83 * @DPU_SSPP_CDP Supports client driven prefetch 84 * @DPU_SSPP_INLINE_ROTATION Support inline rotation 85 * @DPU_SSPP_MAX maximum value 86 */ 87 enum { 88 DPU_SSPP_SRC = 0x1, 89 DPU_SSPP_SCALER_QSEED2, 90 DPU_SSPP_SCALER_QSEED3, 91 DPU_SSPP_SCALER_QSEED3LITE, 92 DPU_SSPP_SCALER_QSEED4, 93 DPU_SSPP_SCALER_RGB, 94 DPU_SSPP_CSC, 95 DPU_SSPP_CSC_10BIT, 96 DPU_SSPP_CURSOR, 97 DPU_SSPP_QOS, 98 DPU_SSPP_QOS_8LVL, 99 DPU_SSPP_EXCL_RECT, 100 DPU_SSPP_SMART_DMA_V1, 101 DPU_SSPP_SMART_DMA_V2, 102 DPU_SSPP_TS_PREFILL, 103 DPU_SSPP_TS_PREFILL_REC1, 104 DPU_SSPP_CDP, 105 DPU_SSPP_INLINE_ROTATION, 106 DPU_SSPP_MAX 107 }; 108 109 /* 110 * MIXER sub-blocks/features 111 * @DPU_MIXER_LAYER Layer mixer layer blend configuration, 112 * @DPU_MIXER_SOURCESPLIT Layer mixer supports source-split configuration 113 * @DPU_MIXER_GC Gamma correction block 114 * @DPU_DIM_LAYER Layer mixer supports dim layer 115 * @DPU_MIXER_COMBINED_ALPHA Layer mixer has combined alpha register 116 * @DPU_MIXER_MAX maximum value 117 */ 118 enum { 119 DPU_MIXER_LAYER = 0x1, 120 DPU_MIXER_SOURCESPLIT, 121 DPU_MIXER_GC, 122 DPU_DIM_LAYER, 123 DPU_MIXER_COMBINED_ALPHA, 124 DPU_MIXER_MAX 125 }; 126 127 /** 128 * DSPP sub-blocks 129 * @DPU_DSPP_PCC Panel color correction block 130 * @DPU_DSPP_GC Gamma correction block 131 * @DPU_DSPP_IGC Inverse gamma correction block 132 */ 133 enum { 134 DPU_DSPP_PCC = 0x1, 135 DPU_DSPP_GC, 136 DPU_DSPP_IGC, 137 DPU_DSPP_MAX 138 }; 139 140 /** 141 * PINGPONG sub-blocks 142 * @DPU_PINGPONG_TE Tear check block 143 * @DPU_PINGPONG_TE2 Additional tear check block for split pipes 144 * @DPU_PINGPONG_SPLIT PP block supports split fifo 145 * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo 146 * @DPU_PINGPONG_DITHER, Dither blocks 147 * @DPU_PINGPONG_MAX 148 */ 149 enum { 150 DPU_PINGPONG_TE = 0x1, 151 DPU_PINGPONG_TE2, 152 DPU_PINGPONG_SPLIT, 153 DPU_PINGPONG_SLAVE, 154 DPU_PINGPONG_DITHER, 155 DPU_PINGPONG_MAX 156 }; 157 158 /** 159 * CTL sub-blocks 160 * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display 161 * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs) 162 * @DPU_CTL_VM_CFG: CTL config to support multiple VMs 163 * @DPU_CTL_HAS_LAYER_EXT4: CTL has the CTL_LAYER_EXT4 register 164 * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush 165 * @DPU_CTL_MAX 166 */ 167 enum { 168 DPU_CTL_SPLIT_DISPLAY = 0x1, 169 DPU_CTL_ACTIVE_CFG, 170 DPU_CTL_FETCH_ACTIVE, 171 DPU_CTL_VM_CFG, 172 DPU_CTL_HAS_LAYER_EXT4, 173 DPU_CTL_DSPP_SUB_BLOCK_FLUSH, 174 DPU_CTL_MAX 175 }; 176 177 /** 178 * INTF sub-blocks 179 * @DPU_INTF_INPUT_CTRL Supports the setting of pp block from which 180 * pixel data arrives to this INTF 181 * @DPU_INTF_TE INTF block has TE configuration support 182 * @DPU_DATA_HCTL_EN Allows data to be transferred at different rate 183 * than video timing 184 * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register 185 * @DPU_INTF_MAX 186 */ 187 enum { 188 DPU_INTF_INPUT_CTRL = 0x1, 189 DPU_INTF_TE, 190 DPU_DATA_HCTL_EN, 191 DPU_INTF_STATUS_SUPPORTED, 192 DPU_INTF_MAX 193 }; 194 195 /** 196 * WB sub-blocks and features 197 * @DPU_WB_LINE_MODE Writeback module supports line/linear mode 198 * @DPU_WB_BLOCK_MODE Writeback module supports block mode read 199 * @DPU_WB_CHROMA_DOWN, Writeback chroma down block, 200 * @DPU_WB_DOWNSCALE, Writeback integer downscaler, 201 * @DPU_WB_DITHER, Dither block 202 * @DPU_WB_TRAFFIC_SHAPER, Writeback traffic shaper bloc 203 * @DPU_WB_UBWC, Writeback Universal bandwidth compression 204 * @DPU_WB_YUV_CONFIG Writeback supports output of YUV colorspace 205 * @DPU_WB_PIPE_ALPHA Writeback supports pipe alpha 206 * @DPU_WB_XY_ROI_OFFSET Writeback supports x/y-offset of out ROI in 207 * the destination image 208 * @DPU_WB_QOS, Writeback supports QoS control, danger/safe/creq 209 * @DPU_WB_QOS_8LVL, Writeback supports 8-level QoS control 210 * @DPU_WB_CDP Writeback supports client driven prefetch 211 * @DPU_WB_INPUT_CTRL Writeback supports from which pp block input pixel 212 * data arrives. 213 * @DPU_WB_CROP CWB supports cropping 214 * @DPU_WB_MAX maximum value 215 */ 216 enum { 217 DPU_WB_LINE_MODE = 0x1, 218 DPU_WB_BLOCK_MODE, 219 DPU_WB_UBWC, 220 DPU_WB_YUV_CONFIG, 221 DPU_WB_PIPE_ALPHA, 222 DPU_WB_XY_ROI_OFFSET, 223 DPU_WB_QOS, 224 DPU_WB_QOS_8LVL, 225 DPU_WB_CDP, 226 DPU_WB_INPUT_CTRL, 227 DPU_WB_CROP, 228 DPU_WB_MAX 229 }; 230 231 /** 232 * VBIF sub-blocks and features 233 * @DPU_VBIF_QOS_OTLIM VBIF supports OT Limit 234 * @DPU_VBIF_QOS_REMAP VBIF supports QoS priority remap 235 * @DPU_VBIF_MAX maximum value 236 */ 237 enum { 238 DPU_VBIF_QOS_OTLIM = 0x1, 239 DPU_VBIF_QOS_REMAP, 240 DPU_VBIF_MAX 241 }; 242 243 /** 244 * DSC features 245 * @DPU_DSC_OUTPUT_CTRL Configure which PINGPONG block gets 246 * the pixel output from this DSC. 247 */ 248 enum { 249 DPU_DSC_OUTPUT_CTRL = 0x1, 250 }; 251 252 /** 253 * MACRO DPU_HW_BLK_INFO - information of HW blocks inside DPU 254 * @name: string name for debug purposes 255 * @id: enum identifying this block 256 * @base: register base offset to mdss 257 * @len: length of hardware block 258 * @features bit mask identifying sub-blocks/features 259 */ 260 #define DPU_HW_BLK_INFO \ 261 char name[DPU_HW_BLK_NAME_LEN]; \ 262 u32 id; \ 263 u32 base; \ 264 u32 len; \ 265 unsigned long features 266 267 /** 268 * MACRO DPU_HW_SUBBLK_INFO - information of HW sub-block inside DPU 269 * @name: string name for debug purposes 270 * @id: enum identifying this sub-block 271 * @base: offset of this sub-block relative to the block 272 * offset 273 * @len register block length of this sub-block 274 */ 275 #define DPU_HW_SUBBLK_INFO \ 276 char name[DPU_HW_BLK_NAME_LEN]; \ 277 u32 id; \ 278 u32 base; \ 279 u32 len 280 281 /** 282 * struct dpu_src_blk: SSPP part of the source pipes 283 * @info: HW register and features supported by this sub-blk 284 */ 285 struct dpu_src_blk { 286 DPU_HW_SUBBLK_INFO; 287 }; 288 289 /** 290 * struct dpu_scaler_blk: Scaler information 291 * @info: HW register and features supported by this sub-blk 292 * @version: qseed block revision 293 */ 294 struct dpu_scaler_blk { 295 DPU_HW_SUBBLK_INFO; 296 u32 version; 297 }; 298 299 struct dpu_csc_blk { 300 DPU_HW_SUBBLK_INFO; 301 }; 302 303 /** 304 * struct dpu_pp_blk : Pixel processing sub-blk information 305 * @info: HW register and features supported by this sub-blk 306 * @version: HW Algorithm version 307 */ 308 struct dpu_pp_blk { 309 DPU_HW_SUBBLK_INFO; 310 u32 version; 311 }; 312 313 /** 314 * enum dpu_qos_lut_usage - define QoS LUT use cases 315 */ 316 enum dpu_qos_lut_usage { 317 DPU_QOS_LUT_USAGE_LINEAR, 318 DPU_QOS_LUT_USAGE_MACROTILE, 319 DPU_QOS_LUT_USAGE_NRT, 320 DPU_QOS_LUT_USAGE_MAX, 321 }; 322 323 /** 324 * struct dpu_qos_lut_entry - define QoS LUT table entry 325 * @fl: fill level, or zero on last entry to indicate default lut 326 * @lut: lut to use if equal to or less than fill level 327 */ 328 struct dpu_qos_lut_entry { 329 u32 fl; 330 u64 lut; 331 }; 332 333 /** 334 * struct dpu_qos_lut_tbl - define QoS LUT table 335 * @nentry: number of entry in this table 336 * @entries: Pointer to table entries 337 */ 338 struct dpu_qos_lut_tbl { 339 u32 nentry; 340 const struct dpu_qos_lut_entry *entries; 341 }; 342 343 /** 344 * struct dpu_rotation_cfg - define inline rotation config 345 * @rot_maxheight: max pre rotated height allowed for rotation 346 * @rot_num_formats: number of elements in @rot_format_list 347 * @rot_format_list: list of supported rotator formats 348 */ 349 struct dpu_rotation_cfg { 350 u32 rot_maxheight; 351 size_t rot_num_formats; 352 const u32 *rot_format_list; 353 }; 354 355 /** 356 * struct dpu_caps - define DPU capabilities 357 * @max_mixer_width max layer mixer line width support. 358 * @max_mixer_blendstages max layer mixer blend stages or 359 * supported z order 360 * @qseed_type qseed2 or qseed3 support. 361 * @has_src_split source split feature status 362 * @has_dim_layer dim layer feature status 363 * @has_idle_pc indicate if idle power collapse feature is supported 364 * @has_3d_merge indicate if 3D merge is supported 365 * @max_linewidth max linewidth for sspp 366 * @pixel_ram_size size of latency hiding and de-tiling buffer in bytes 367 * @max_hdeci_exp max horizontal decimation supported (max is 2^value) 368 * @max_vdeci_exp max vertical decimation supported (max is 2^value) 369 */ 370 struct dpu_caps { 371 u32 max_mixer_width; 372 u32 max_mixer_blendstages; 373 u32 qseed_type; 374 bool has_src_split; 375 bool has_dim_layer; 376 bool has_idle_pc; 377 bool has_3d_merge; 378 /* SSPP limits */ 379 u32 max_linewidth; 380 u32 pixel_ram_size; 381 u32 max_hdeci_exp; 382 u32 max_vdeci_exp; 383 }; 384 385 /** 386 * struct dpu_sspp_sub_blks : SSPP sub-blocks 387 * common: Pointer to common configurations shared by sub blocks 388 * @creq_vblank: creq priority during vertical blanking 389 * @danger_vblank: danger priority during vertical blanking 390 * @maxdwnscale: max downscale ratio supported(without DECIMATION) 391 * @maxupscale: maxupscale ratio supported 392 * @smart_dma_priority: hw priority of rect1 of multirect pipe 393 * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps 394 * @qseed_ver: qseed version 395 * @src_blk: 396 * @scaler_blk: 397 * @csc_blk: 398 * @hsic: 399 * @memcolor: 400 * @pcc_blk: 401 * @igc_blk: 402 * @format_list: Pointer to list of supported formats 403 * @num_formats: Number of supported formats 404 * @virt_format_list: Pointer to list of supported formats for virtual planes 405 * @virt_num_formats: Number of supported formats for virtual planes 406 * @dpu_rotation_cfg: inline rotation configuration 407 */ 408 struct dpu_sspp_sub_blks { 409 u32 creq_vblank; 410 u32 danger_vblank; 411 u32 maxdwnscale; 412 u32 maxupscale; 413 u32 smart_dma_priority; 414 u32 max_per_pipe_bw; 415 u32 qseed_ver; 416 struct dpu_src_blk src_blk; 417 struct dpu_scaler_blk scaler_blk; 418 struct dpu_pp_blk csc_blk; 419 struct dpu_pp_blk hsic_blk; 420 struct dpu_pp_blk memcolor_blk; 421 struct dpu_pp_blk pcc_blk; 422 struct dpu_pp_blk igc_blk; 423 424 const u32 *format_list; 425 u32 num_formats; 426 const u32 *virt_format_list; 427 u32 virt_num_formats; 428 const struct dpu_rotation_cfg *rotation_cfg; 429 }; 430 431 /** 432 * struct dpu_lm_sub_blks: information of mixer block 433 * @maxwidth: Max pixel width supported by this mixer 434 * @maxblendstages: Max number of blend-stages supported 435 * @blendstage_base: Blend-stage register base offset 436 * @gc: gamma correction block 437 */ 438 struct dpu_lm_sub_blks { 439 u32 maxwidth; 440 u32 maxblendstages; 441 u32 blendstage_base[MAX_BLOCKS]; 442 struct dpu_pp_blk gc; 443 }; 444 445 /** 446 * struct dpu_dspp_sub_blks: Information of DSPP block 447 * @gc : gamma correction block 448 * @pcc: pixel color correction block 449 */ 450 struct dpu_dspp_sub_blks { 451 struct dpu_pp_blk gc; 452 struct dpu_pp_blk pcc; 453 }; 454 455 struct dpu_pingpong_sub_blks { 456 struct dpu_pp_blk te; 457 struct dpu_pp_blk te2; 458 struct dpu_pp_blk dither; 459 }; 460 461 /** 462 * dpu_clk_ctrl_type - Defines top level clock control signals 463 */ 464 enum dpu_clk_ctrl_type { 465 DPU_CLK_CTRL_NONE, 466 DPU_CLK_CTRL_VIG0, 467 DPU_CLK_CTRL_VIG1, 468 DPU_CLK_CTRL_VIG2, 469 DPU_CLK_CTRL_VIG3, 470 DPU_CLK_CTRL_VIG4, 471 DPU_CLK_CTRL_RGB0, 472 DPU_CLK_CTRL_RGB1, 473 DPU_CLK_CTRL_RGB2, 474 DPU_CLK_CTRL_RGB3, 475 DPU_CLK_CTRL_DMA0, 476 DPU_CLK_CTRL_DMA1, 477 DPU_CLK_CTRL_DMA2, 478 DPU_CLK_CTRL_DMA3, 479 DPU_CLK_CTRL_DMA4, 480 DPU_CLK_CTRL_DMA5, 481 DPU_CLK_CTRL_CURSOR0, 482 DPU_CLK_CTRL_CURSOR1, 483 DPU_CLK_CTRL_INLINE_ROT0_SSPP, 484 DPU_CLK_CTRL_REG_DMA, 485 DPU_CLK_CTRL_WB2, 486 DPU_CLK_CTRL_MAX, 487 }; 488 489 /* struct dpu_clk_ctrl_reg : Clock control register 490 * @reg_off: register offset 491 * @bit_off: bit offset 492 */ 493 struct dpu_clk_ctrl_reg { 494 u32 reg_off; 495 u32 bit_off; 496 }; 497 498 /* struct dpu_mdp_cfg : MDP TOP-BLK instance info 499 * @id: index identifying this block 500 * @base: register base offset to mdss 501 * @features bit mask identifying sub-blocks/features 502 * @clk_ctrls clock control register definition 503 */ 504 struct dpu_mdp_cfg { 505 DPU_HW_BLK_INFO; 506 struct dpu_clk_ctrl_reg clk_ctrls[DPU_CLK_CTRL_MAX]; 507 }; 508 509 /** 510 * struct dpu_ubwc_cfg - UBWC and memory configuration 511 * 512 * @ubwc_version UBWC feature version (0x0 for not supported) 513 * @highest_bank_bit: UBWC parameter 514 * @ubwc_swizzle: ubwc default swizzle setting 515 */ 516 struct dpu_ubwc_cfg { 517 u32 ubwc_version; 518 u32 highest_bank_bit; 519 u32 ubwc_swizzle; 520 }; 521 522 /* struct dpu_ctl_cfg : MDP CTL instance info 523 * @id: index identifying this block 524 * @base: register base offset to mdss 525 * @features bit mask identifying sub-blocks/features 526 * @intr_start: interrupt index for CTL_START 527 */ 528 struct dpu_ctl_cfg { 529 DPU_HW_BLK_INFO; 530 s32 intr_start; 531 }; 532 533 /** 534 * struct dpu_sspp_cfg - information of source pipes 535 * @id: index identifying this block 536 * @base register offset of this block 537 * @features bit mask identifying sub-blocks/features 538 * @sblk: SSPP sub-blocks information 539 * @xin_id: bus client identifier 540 * @clk_ctrl clock control identifier 541 * @type sspp type identifier 542 */ 543 struct dpu_sspp_cfg { 544 DPU_HW_BLK_INFO; 545 const struct dpu_sspp_sub_blks *sblk; 546 u32 xin_id; 547 enum dpu_clk_ctrl_type clk_ctrl; 548 u32 type; 549 }; 550 551 /** 552 * struct dpu_lm_cfg - information of layer mixer blocks 553 * @id: index identifying this block 554 * @base register offset of this block 555 * @features bit mask identifying sub-blocks/features 556 * @sblk: LM Sub-blocks information 557 * @pingpong: ID of connected PingPong, PINGPONG_MAX if unsupported 558 * @lm_pair_mask: Bitmask of LMs that can be controlled by same CTL 559 */ 560 struct dpu_lm_cfg { 561 DPU_HW_BLK_INFO; 562 const struct dpu_lm_sub_blks *sblk; 563 u32 pingpong; 564 u32 dspp; 565 unsigned long lm_pair_mask; 566 }; 567 568 /** 569 * struct dpu_dspp_cfg - information of DSPP blocks 570 * @id enum identifying this block 571 * @base register offset of this block 572 * @features bit mask identifying sub-blocks/features 573 * supported by this block 574 * @sblk sub-blocks information 575 */ 576 struct dpu_dspp_cfg { 577 DPU_HW_BLK_INFO; 578 const struct dpu_dspp_sub_blks *sblk; 579 }; 580 581 /** 582 * struct dpu_pingpong_cfg - information of PING-PONG blocks 583 * @id enum identifying this block 584 * @base register offset of this block 585 * @features bit mask identifying sub-blocks/features 586 * @intr_done: index for PINGPONG done interrupt 587 * @intr_rdptr: index for PINGPONG readpointer done interrupt 588 * @sblk sub-blocks information 589 */ 590 struct dpu_pingpong_cfg { 591 DPU_HW_BLK_INFO; 592 u32 merge_3d; 593 s32 intr_done; 594 s32 intr_rdptr; 595 const struct dpu_pingpong_sub_blks *sblk; 596 }; 597 598 /** 599 * struct dpu_merge_3d_cfg - information of DSPP blocks 600 * @id enum identifying this block 601 * @base register offset of this block 602 * @features bit mask identifying sub-blocks/features 603 * supported by this block 604 * @sblk sub-blocks information 605 */ 606 struct dpu_merge_3d_cfg { 607 DPU_HW_BLK_INFO; 608 const struct dpu_merge_3d_sub_blks *sblk; 609 }; 610 611 /** 612 * struct dpu_dsc_cfg - information of DSC blocks 613 * @id enum identifying this block 614 * @base register offset of this block 615 * @features bit mask identifying sub-blocks/features 616 */ 617 struct dpu_dsc_cfg { 618 DPU_HW_BLK_INFO; 619 }; 620 621 /** 622 * struct dpu_intf_cfg - information of timing engine blocks 623 * @id enum identifying this block 624 * @base register offset of this block 625 * @features bit mask identifying sub-blocks/features 626 * @type: Interface type(DSI, DP, HDMI) 627 * @controller_id: Controller Instance ID in case of multiple of intf type 628 * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch 629 * @intr_underrun: index for INTF underrun interrupt 630 * @intr_vsync: index for INTF VSYNC interrupt 631 */ 632 struct dpu_intf_cfg { 633 DPU_HW_BLK_INFO; 634 u32 type; /* interface type*/ 635 u32 controller_id; 636 u32 prog_fetch_lines_worst_case; 637 s32 intr_underrun; 638 s32 intr_vsync; 639 }; 640 641 /** 642 * struct dpu_wb_cfg - information of writeback blocks 643 * @DPU_HW_BLK_INFO: refer to the description above for DPU_HW_BLK_INFO 644 * @vbif_idx: vbif client index 645 * @maxlinewidth: max line width supported by writeback block 646 * @xin_id: bus client identifier 647 * @intr_wb_done: interrupt index for WB_DONE 648 * @format_list: list of formats supported by this writeback block 649 * @num_formats: number of formats supported by this writeback block 650 * @clk_ctrl: clock control identifier 651 */ 652 struct dpu_wb_cfg { 653 DPU_HW_BLK_INFO; 654 u8 vbif_idx; 655 u32 maxlinewidth; 656 u32 xin_id; 657 s32 intr_wb_done; 658 const u32 *format_list; 659 u32 num_formats; 660 enum dpu_clk_ctrl_type clk_ctrl; 661 }; 662 663 /** 664 * struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting 665 * @pps pixel per seconds 666 * @ot_limit OT limit to use up to specified pixel per second 667 */ 668 struct dpu_vbif_dynamic_ot_cfg { 669 u64 pps; 670 u32 ot_limit; 671 }; 672 673 /** 674 * struct dpu_vbif_dynamic_ot_tbl - dynamic OT setting table 675 * @count length of cfg 676 * @cfg pointer to array of configuration settings with 677 * ascending requirements 678 */ 679 struct dpu_vbif_dynamic_ot_tbl { 680 u32 count; 681 const struct dpu_vbif_dynamic_ot_cfg *cfg; 682 }; 683 684 /** 685 * struct dpu_vbif_qos_tbl - QoS priority table 686 * @npriority_lvl num of priority level 687 * @priority_lvl pointer to array of priority level in ascending order 688 */ 689 struct dpu_vbif_qos_tbl { 690 u32 npriority_lvl; 691 const u32 *priority_lvl; 692 }; 693 694 /** 695 * struct dpu_vbif_cfg - information of VBIF blocks 696 * @id enum identifying this block 697 * @base register offset of this block 698 * @features bit mask identifying sub-blocks/features 699 * @ot_rd_limit default OT read limit 700 * @ot_wr_limit default OT write limit 701 * @xin_halt_timeout maximum time (in usec) for xin to halt 702 * @qos_rp_remap_size size of VBIF_XINL_QOS_RP_REMAP register space 703 * @dynamic_ot_rd_tbl dynamic OT read configuration table 704 * @dynamic_ot_wr_tbl dynamic OT write configuration table 705 * @qos_rt_tbl real-time QoS priority table 706 * @qos_nrt_tbl non-real-time QoS priority table 707 * @memtype_count number of defined memtypes 708 * @memtype array of xin memtype definitions 709 */ 710 struct dpu_vbif_cfg { 711 DPU_HW_BLK_INFO; 712 u32 default_ot_rd_limit; 713 u32 default_ot_wr_limit; 714 u32 xin_halt_timeout; 715 u32 qos_rp_remap_size; 716 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_rd_tbl; 717 struct dpu_vbif_dynamic_ot_tbl dynamic_ot_wr_tbl; 718 struct dpu_vbif_qos_tbl qos_rt_tbl; 719 struct dpu_vbif_qos_tbl qos_nrt_tbl; 720 u32 memtype_count; 721 u32 memtype[MAX_XIN_COUNT]; 722 }; 723 /** 724 * struct dpu_reg_dma_cfg - information of lut dma blocks 725 * @id enum identifying this block 726 * @base register offset of this block 727 * @features bit mask identifying sub-blocks/features 728 * @version version of lutdma hw block 729 * @trigger_sel_off offset to trigger select registers of lutdma 730 */ 731 struct dpu_reg_dma_cfg { 732 DPU_HW_BLK_INFO; 733 u32 version; 734 u32 trigger_sel_off; 735 u32 xin_id; 736 enum dpu_clk_ctrl_type clk_ctrl; 737 }; 738 739 /** 740 * Define CDP use cases 741 * @DPU_PERF_CDP_UDAGE_RT: real-time use cases 742 * @DPU_PERF_CDP_USAGE_NRT: non real-time use cases such as WFD 743 */ 744 enum { 745 DPU_PERF_CDP_USAGE_RT, 746 DPU_PERF_CDP_USAGE_NRT, 747 DPU_PERF_CDP_USAGE_MAX 748 }; 749 750 /** 751 * struct dpu_perf_cdp_cfg - define CDP use case configuration 752 * @rd_enable: true if read pipe CDP is enabled 753 * @wr_enable: true if write pipe CDP is enabled 754 */ 755 struct dpu_perf_cdp_cfg { 756 bool rd_enable; 757 bool wr_enable; 758 }; 759 760 /** 761 * struct dpu_perf_cfg - performance control settings 762 * @max_bw_low low threshold of maximum bandwidth (kbps) 763 * @max_bw_high high threshold of maximum bandwidth (kbps) 764 * @min_core_ib minimum bandwidth for core (kbps) 765 * @min_core_ib minimum mnoc ib vote in kbps 766 * @min_llcc_ib minimum llcc ib vote in kbps 767 * @min_dram_ib minimum dram ib vote in kbps 768 * @undersized_prefill_lines undersized prefill in lines 769 * @xtra_prefill_lines extra prefill latency in lines 770 * @dest_scale_prefill_lines destination scaler latency in lines 771 * @macrotile_perfill_lines macrotile latency in lines 772 * @yuv_nv12_prefill_lines yuv_nv12 latency in lines 773 * @linear_prefill_lines linear latency in lines 774 * @downscaling_prefill_lines downscaling latency in lines 775 * @amortizable_theshold minimum y position for traffic shaping prefill 776 * @min_prefill_lines minimum pipeline latency in lines 777 * @clk_inefficiency_factor DPU src clock inefficiency factor 778 * @bw_inefficiency_factor DPU axi bus bw inefficiency factor 779 * @safe_lut_tbl: LUT tables for safe signals 780 * @danger_lut_tbl: LUT tables for danger signals 781 * @qos_lut_tbl: LUT tables for QoS signals 782 * @cdp_cfg cdp use case configurations 783 */ 784 struct dpu_perf_cfg { 785 u32 max_bw_low; 786 u32 max_bw_high; 787 u32 min_core_ib; 788 u32 min_llcc_ib; 789 u32 min_dram_ib; 790 u32 undersized_prefill_lines; 791 u32 xtra_prefill_lines; 792 u32 dest_scale_prefill_lines; 793 u32 macrotile_prefill_lines; 794 u32 yuv_nv12_prefill_lines; 795 u32 linear_prefill_lines; 796 u32 downscaling_prefill_lines; 797 u32 amortizable_threshold; 798 u32 min_prefill_lines; 799 u32 clk_inefficiency_factor; 800 u32 bw_inefficiency_factor; 801 u32 safe_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 802 u32 danger_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 803 struct dpu_qos_lut_tbl qos_lut_tbl[DPU_QOS_LUT_USAGE_MAX]; 804 struct dpu_perf_cdp_cfg cdp_cfg[DPU_PERF_CDP_USAGE_MAX]; 805 }; 806 807 /** 808 * struct dpu_mdss_cfg - information of MDSS HW 809 * This is the main catalog data structure representing 810 * this HW version. Contains number of instances, 811 * register offsets, capabilities of the all MDSS HW sub-blocks. 812 * 813 * @dma_formats Supported formats for dma pipe 814 * @cursor_formats Supported formats for cursor pipe 815 * @vig_formats Supported formats for vig pipe 816 * @mdss_irqs: Bitmap with the irqs supported by the target 817 */ 818 struct dpu_mdss_cfg { 819 const struct dpu_caps *caps; 820 821 const struct dpu_ubwc_cfg *ubwc; 822 823 u32 mdp_count; 824 const struct dpu_mdp_cfg *mdp; 825 826 u32 ctl_count; 827 const struct dpu_ctl_cfg *ctl; 828 829 u32 sspp_count; 830 const struct dpu_sspp_cfg *sspp; 831 832 u32 mixer_count; 833 const struct dpu_lm_cfg *mixer; 834 835 u32 pingpong_count; 836 const struct dpu_pingpong_cfg *pingpong; 837 838 u32 merge_3d_count; 839 const struct dpu_merge_3d_cfg *merge_3d; 840 841 u32 dsc_count; 842 const struct dpu_dsc_cfg *dsc; 843 844 u32 intf_count; 845 const struct dpu_intf_cfg *intf; 846 847 u32 vbif_count; 848 const struct dpu_vbif_cfg *vbif; 849 850 u32 wb_count; 851 const struct dpu_wb_cfg *wb; 852 853 u32 reg_dma_count; 854 const struct dpu_reg_dma_cfg *dma_cfg; 855 856 u32 ad_count; 857 858 u32 dspp_count; 859 const struct dpu_dspp_cfg *dspp; 860 861 /* Add additional block data structures here */ 862 863 const struct dpu_perf_cfg *perf; 864 const struct dpu_format_extended *dma_formats; 865 const struct dpu_format_extended *cursor_formats; 866 const struct dpu_format_extended *vig_formats; 867 868 unsigned long mdss_irqs; 869 }; 870 871 extern const struct dpu_mdss_cfg dpu_msm8998_cfg; 872 extern const struct dpu_mdss_cfg dpu_sdm845_cfg; 873 extern const struct dpu_mdss_cfg dpu_sm8150_cfg; 874 extern const struct dpu_mdss_cfg dpu_sc8180x_cfg; 875 extern const struct dpu_mdss_cfg dpu_sm8250_cfg; 876 extern const struct dpu_mdss_cfg dpu_sc7180_cfg; 877 extern const struct dpu_mdss_cfg dpu_sm6115_cfg; 878 extern const struct dpu_mdss_cfg dpu_qcm2290_cfg; 879 extern const struct dpu_mdss_cfg dpu_sm8350_cfg; 880 extern const struct dpu_mdss_cfg dpu_sc7280_cfg; 881 extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg; 882 extern const struct dpu_mdss_cfg dpu_sm8450_cfg; 883 extern const struct dpu_mdss_cfg dpu_sm8550_cfg; 884 885 #endif /* _DPU_HW_CATALOG_H */ 886