1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
3  * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
4  */
5 
6 #define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
7 #include <linux/slab.h>
8 #include <linux/of_address.h>
9 #include <linux/platform_device.h>
10 #include "dpu_hw_mdss.h"
11 #include "dpu_hw_interrupts.h"
12 #include "dpu_hw_catalog.h"
13 #include "dpu_kms.h"
14 
15 #define VIG_MASK \
16 	(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
17 	BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\
18 	BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT))
19 
20 #define VIG_MSM8998_MASK \
21 	(VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3))
22 
23 #define VIG_SDM845_MASK \
24 	(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3))
25 
26 #define VIG_SC7180_MASK \
27 	(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))
28 
29 #define VIG_SM8250_MASK \
30 	(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
31 
32 #define VIG_QCM2290_MASK (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL))
33 
34 #define DMA_MSM8998_MASK \
35 	(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\
36 	BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
37 	BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
38 
39 #define VIG_SC7280_MASK \
40 	(VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION))
41 
42 #define DMA_SDM845_MASK \
43 	(BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\
44 	BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\
45 	BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT))
46 
47 #define DMA_CURSOR_SDM845_MASK \
48 	(DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR))
49 
50 #define DMA_CURSOR_MSM8998_MASK \
51 	(DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR))
52 
53 #define MIXER_MSM8998_MASK \
54 	(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER))
55 
56 #define MIXER_SDM845_MASK \
57 	(BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
58 
59 #define MIXER_QCM2290_MASK \
60 	(BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA))
61 
62 #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER)
63 
64 #define PINGPONG_SDM845_SPLIT_MASK \
65 	(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
66 
67 #define CTL_SC7280_MASK \
68 	(BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG))
69 
70 #define CTL_SM8550_MASK \
71 	(CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4))
72 
73 #define MERGE_3D_SM8150_MASK (0)
74 
75 #define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC) | BIT(DPU_DSPP_GC)
76 
77 #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC)
78 
79 #define INTF_SDM845_MASK (0)
80 
81 #define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE)
82 
83 #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN)
84 
85 #define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
86 			 BIT(MDP_SSPP_TOP0_INTR2) | \
87 			 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
88 			 BIT(MDP_INTF0_INTR) | \
89 			 BIT(MDP_INTF1_INTR) | \
90 			 BIT(MDP_INTF2_INTR) | \
91 			 BIT(MDP_INTF3_INTR) | \
92 			 BIT(MDP_AD4_0_INTR) | \
93 			 BIT(MDP_AD4_1_INTR))
94 
95 #define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
96 			 BIT(MDP_SSPP_TOP0_INTR2) | \
97 			 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
98 			 BIT(MDP_INTF0_INTR) | \
99 			 BIT(MDP_INTF1_INTR))
100 
101 #define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
102 			 BIT(MDP_SSPP_TOP0_INTR2) | \
103 			 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
104 			 BIT(MDP_INTF0_7xxx_INTR) | \
105 			 BIT(MDP_INTF1_7xxx_INTR) | \
106 			 BIT(MDP_INTF5_7xxx_INTR))
107 
108 #define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
109 			 BIT(MDP_SSPP_TOP0_INTR2) | \
110 			 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
111 			 BIT(MDP_INTF0_INTR) | \
112 			 BIT(MDP_INTF1_INTR) | \
113 			 BIT(MDP_INTF2_INTR) | \
114 			 BIT(MDP_INTF3_INTR) | \
115 			 BIT(MDP_INTF4_INTR))
116 
117 #define IRQ_SM8350_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
118 			 BIT(MDP_SSPP_TOP0_INTR2) | \
119 			 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
120 			 BIT(MDP_INTF0_7xxx_INTR) | \
121 			 BIT(MDP_INTF1_7xxx_INTR) | \
122 			 BIT(MDP_INTF2_7xxx_INTR) | \
123 			 BIT(MDP_INTF3_7xxx_INTR))
124 
125 #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
126 			  BIT(MDP_SSPP_TOP0_INTR2) | \
127 			  BIT(MDP_SSPP_TOP0_HIST_INTR) | \
128 			  BIT(MDP_INTF0_INTR) | \
129 			  BIT(MDP_INTF1_INTR) | \
130 			  BIT(MDP_INTF2_INTR) | \
131 			  BIT(MDP_INTF3_INTR) | \
132 			  BIT(MDP_INTF4_INTR) | \
133 			  BIT(MDP_INTF5_INTR) | \
134 			  BIT(MDP_AD4_0_INTR) | \
135 			  BIT(MDP_AD4_1_INTR))
136 
137 #define IRQ_SC8280XP_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
138 			   BIT(MDP_SSPP_TOP0_INTR2) | \
139 			   BIT(MDP_SSPP_TOP0_HIST_INTR) | \
140 			   BIT(MDP_INTF0_7xxx_INTR) | \
141 			   BIT(MDP_INTF1_7xxx_INTR) | \
142 			   BIT(MDP_INTF2_7xxx_INTR) | \
143 			   BIT(MDP_INTF3_7xxx_INTR) | \
144 			   BIT(MDP_INTF4_7xxx_INTR) | \
145 			   BIT(MDP_INTF5_7xxx_INTR) | \
146 			   BIT(MDP_INTF6_7xxx_INTR) | \
147 			   BIT(MDP_INTF7_7xxx_INTR) | \
148 			   BIT(MDP_INTF8_7xxx_INTR))
149 
150 #define IRQ_SM8450_MASK (BIT(MDP_SSPP_TOP0_INTR) | \
151 			 BIT(MDP_SSPP_TOP0_INTR2) | \
152 			 BIT(MDP_SSPP_TOP0_HIST_INTR) | \
153 			 BIT(MDP_INTF0_7xxx_INTR) | \
154 			 BIT(MDP_INTF1_7xxx_INTR) | \
155 			 BIT(MDP_INTF2_7xxx_INTR) | \
156 			 BIT(MDP_INTF3_7xxx_INTR))
157 
158 #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \
159 			 BIT(DPU_WB_UBWC) | \
160 			 BIT(DPU_WB_YUV_CONFIG) | \
161 			 BIT(DPU_WB_PIPE_ALPHA) | \
162 			 BIT(DPU_WB_XY_ROI_OFFSET) | \
163 			 BIT(DPU_WB_QOS) | \
164 			 BIT(DPU_WB_QOS_8LVL) | \
165 			 BIT(DPU_WB_CDP) | \
166 			 BIT(DPU_WB_INPUT_CTRL))
167 
168 #define DEFAULT_PIXEL_RAM_SIZE		(50 * 1024)
169 #define DEFAULT_DPU_LINE_WIDTH		2048
170 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH	2560
171 
172 #define MAX_HORZ_DECIMATION	4
173 #define MAX_VERT_DECIMATION	4
174 
175 #define MAX_UPSCALE_RATIO	20
176 #define MAX_DOWNSCALE_RATIO	4
177 #define SSPP_UNITY_SCALE	1
178 
179 #define STRCAT(X, Y) (X Y)
180 
181 static const uint32_t plane_formats[] = {
182 	DRM_FORMAT_ARGB8888,
183 	DRM_FORMAT_ABGR8888,
184 	DRM_FORMAT_RGBA8888,
185 	DRM_FORMAT_BGRA8888,
186 	DRM_FORMAT_XRGB8888,
187 	DRM_FORMAT_RGBX8888,
188 	DRM_FORMAT_BGRX8888,
189 	DRM_FORMAT_XBGR8888,
190 	DRM_FORMAT_XRGB2101010,
191 	DRM_FORMAT_RGB888,
192 	DRM_FORMAT_BGR888,
193 	DRM_FORMAT_RGB565,
194 	DRM_FORMAT_BGR565,
195 	DRM_FORMAT_ARGB1555,
196 	DRM_FORMAT_ABGR1555,
197 	DRM_FORMAT_RGBA5551,
198 	DRM_FORMAT_BGRA5551,
199 	DRM_FORMAT_XRGB1555,
200 	DRM_FORMAT_XBGR1555,
201 	DRM_FORMAT_RGBX5551,
202 	DRM_FORMAT_BGRX5551,
203 	DRM_FORMAT_ARGB4444,
204 	DRM_FORMAT_ABGR4444,
205 	DRM_FORMAT_RGBA4444,
206 	DRM_FORMAT_BGRA4444,
207 	DRM_FORMAT_XRGB4444,
208 	DRM_FORMAT_XBGR4444,
209 	DRM_FORMAT_RGBX4444,
210 	DRM_FORMAT_BGRX4444,
211 };
212 
213 static const uint32_t plane_formats_yuv[] = {
214 	DRM_FORMAT_ARGB8888,
215 	DRM_FORMAT_ABGR8888,
216 	DRM_FORMAT_RGBA8888,
217 	DRM_FORMAT_BGRX8888,
218 	DRM_FORMAT_BGRA8888,
219 	DRM_FORMAT_XRGB2101010,
220 	DRM_FORMAT_XRGB8888,
221 	DRM_FORMAT_XBGR8888,
222 	DRM_FORMAT_RGBX8888,
223 	DRM_FORMAT_RGB888,
224 	DRM_FORMAT_BGR888,
225 	DRM_FORMAT_RGB565,
226 	DRM_FORMAT_BGR565,
227 	DRM_FORMAT_ARGB1555,
228 	DRM_FORMAT_ABGR1555,
229 	DRM_FORMAT_RGBA5551,
230 	DRM_FORMAT_BGRA5551,
231 	DRM_FORMAT_XRGB1555,
232 	DRM_FORMAT_XBGR1555,
233 	DRM_FORMAT_RGBX5551,
234 	DRM_FORMAT_BGRX5551,
235 	DRM_FORMAT_ARGB4444,
236 	DRM_FORMAT_ABGR4444,
237 	DRM_FORMAT_RGBA4444,
238 	DRM_FORMAT_BGRA4444,
239 	DRM_FORMAT_XRGB4444,
240 	DRM_FORMAT_XBGR4444,
241 	DRM_FORMAT_RGBX4444,
242 	DRM_FORMAT_BGRX4444,
243 
244 	DRM_FORMAT_P010,
245 	DRM_FORMAT_NV12,
246 	DRM_FORMAT_NV21,
247 	DRM_FORMAT_NV16,
248 	DRM_FORMAT_NV61,
249 	DRM_FORMAT_VYUY,
250 	DRM_FORMAT_UYVY,
251 	DRM_FORMAT_YUYV,
252 	DRM_FORMAT_YVYU,
253 	DRM_FORMAT_YUV420,
254 	DRM_FORMAT_YVU420,
255 };
256 
257 static const u32 rotation_v2_formats[] = {
258 	DRM_FORMAT_NV12,
259 	/* TODO add formats after validation */
260 };
261 
262 static const uint32_t wb2_formats[] = {
263 	DRM_FORMAT_RGB565,
264 	DRM_FORMAT_BGR565,
265 	DRM_FORMAT_RGB888,
266 	DRM_FORMAT_ARGB8888,
267 	DRM_FORMAT_RGBA8888,
268 	DRM_FORMAT_ABGR8888,
269 	DRM_FORMAT_XRGB8888,
270 	DRM_FORMAT_RGBX8888,
271 	DRM_FORMAT_XBGR8888,
272 	DRM_FORMAT_ARGB1555,
273 	DRM_FORMAT_RGBA5551,
274 	DRM_FORMAT_XRGB1555,
275 	DRM_FORMAT_RGBX5551,
276 	DRM_FORMAT_ARGB4444,
277 	DRM_FORMAT_RGBA4444,
278 	DRM_FORMAT_RGBX4444,
279 	DRM_FORMAT_XRGB4444,
280 	DRM_FORMAT_BGR565,
281 	DRM_FORMAT_BGR888,
282 	DRM_FORMAT_ABGR8888,
283 	DRM_FORMAT_BGRA8888,
284 	DRM_FORMAT_BGRX8888,
285 	DRM_FORMAT_XBGR8888,
286 	DRM_FORMAT_ABGR1555,
287 	DRM_FORMAT_BGRA5551,
288 	DRM_FORMAT_XBGR1555,
289 	DRM_FORMAT_BGRX5551,
290 	DRM_FORMAT_ABGR4444,
291 	DRM_FORMAT_BGRA4444,
292 	DRM_FORMAT_BGRX4444,
293 	DRM_FORMAT_XBGR4444,
294 };
295 
296 /*************************************************************
297  * DPU sub blocks config
298  *************************************************************/
299 /* DPU top level caps */
300 static const struct dpu_caps msm8998_dpu_caps = {
301 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
302 	.max_mixer_blendstages = 0x7,
303 	.qseed_type = DPU_SSPP_SCALER_QSEED3,
304 	.smart_dma_rev = DPU_SSPP_SMART_DMA_V1,
305 	.ubwc_version = DPU_HW_UBWC_VER_10,
306 	.has_src_split = true,
307 	.has_dim_layer = true,
308 	.has_idle_pc = true,
309 	.has_3d_merge = true,
310 	.max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
311 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
312 	.max_hdeci_exp = MAX_HORZ_DECIMATION,
313 	.max_vdeci_exp = MAX_VERT_DECIMATION,
314 };
315 
316 static const struct dpu_caps qcm2290_dpu_caps = {
317 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
318 	.max_mixer_blendstages = 0x4,
319 	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
320 	.ubwc_version = DPU_HW_UBWC_VER_20,
321 	.has_dim_layer = true,
322 	.has_idle_pc = true,
323 	.max_linewidth = 2160,
324 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
325 };
326 
327 static const struct dpu_caps sdm845_dpu_caps = {
328 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
329 	.max_mixer_blendstages = 0xb,
330 	.qseed_type = DPU_SSPP_SCALER_QSEED3,
331 	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
332 	.ubwc_version = DPU_HW_UBWC_VER_20,
333 	.has_src_split = true,
334 	.has_dim_layer = true,
335 	.has_idle_pc = true,
336 	.has_3d_merge = true,
337 	.max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
338 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
339 	.max_hdeci_exp = MAX_HORZ_DECIMATION,
340 	.max_vdeci_exp = MAX_VERT_DECIMATION,
341 };
342 
343 static const struct dpu_caps sc7180_dpu_caps = {
344 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
345 	.max_mixer_blendstages = 0x9,
346 	.qseed_type = DPU_SSPP_SCALER_QSEED4,
347 	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
348 	.ubwc_version = DPU_HW_UBWC_VER_20,
349 	.has_dim_layer = true,
350 	.has_idle_pc = true,
351 	.max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
352 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
353 };
354 
355 static const struct dpu_caps sm6115_dpu_caps = {
356 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
357 	.max_mixer_blendstages = 0x4,
358 	.qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
359 	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
360 	.ubwc_version = DPU_HW_UBWC_VER_10,
361 	.has_dim_layer = true,
362 	.has_idle_pc = true,
363 	.max_linewidth = 2160,
364 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
365 };
366 
367 static const struct dpu_caps sm8150_dpu_caps = {
368 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
369 	.max_mixer_blendstages = 0xb,
370 	.qseed_type = DPU_SSPP_SCALER_QSEED3,
371 	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
372 	.ubwc_version = DPU_HW_UBWC_VER_30,
373 	.has_src_split = true,
374 	.has_dim_layer = true,
375 	.has_idle_pc = true,
376 	.has_3d_merge = true,
377 	.max_linewidth = 4096,
378 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
379 	.max_hdeci_exp = MAX_HORZ_DECIMATION,
380 	.max_vdeci_exp = MAX_VERT_DECIMATION,
381 };
382 
383 static const struct dpu_caps sc8180x_dpu_caps = {
384 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
385 	.max_mixer_blendstages = 0xb,
386 	.qseed_type = DPU_SSPP_SCALER_QSEED3,
387 	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
388 	.ubwc_version = DPU_HW_UBWC_VER_30,
389 	.has_src_split = true,
390 	.has_dim_layer = true,
391 	.has_idle_pc = true,
392 	.has_3d_merge = true,
393 	.max_linewidth = 4096,
394 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
395 	.max_hdeci_exp = MAX_HORZ_DECIMATION,
396 	.max_vdeci_exp = MAX_VERT_DECIMATION,
397 };
398 
399 static const struct dpu_caps sc8280xp_dpu_caps = {
400 	.max_mixer_width = 2560,
401 	.max_mixer_blendstages = 11,
402 	.qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
403 	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
404 	.ubwc_version = DPU_HW_UBWC_VER_40,
405 	.has_src_split = true,
406 	.has_dim_layer = true,
407 	.has_idle_pc = true,
408 	.has_3d_merge = true,
409 	.max_linewidth = 5120,
410 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
411 };
412 
413 static const struct dpu_caps sm8250_dpu_caps = {
414 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
415 	.max_mixer_blendstages = 0xb,
416 	.qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
417 	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
418 	.ubwc_version = DPU_HW_UBWC_VER_40,
419 	.has_src_split = true,
420 	.has_dim_layer = true,
421 	.has_idle_pc = true,
422 	.has_3d_merge = true,
423 	.max_linewidth = 4096,
424 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
425 };
426 
427 static const struct dpu_caps sm8350_dpu_caps = {
428 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
429 	.max_mixer_blendstages = 0xb,
430 	.qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
431 	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
432 	.ubwc_version = DPU_HW_UBWC_VER_40,
433 	.has_src_split = true,
434 	.has_dim_layer = true,
435 	.has_idle_pc = true,
436 	.has_3d_merge = true,
437 	.max_linewidth = 4096,
438 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
439 };
440 
441 static const struct dpu_caps sm8450_dpu_caps = {
442 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
443 	.max_mixer_blendstages = 0xb,
444 	.qseed_type = DPU_SSPP_SCALER_QSEED4,
445 	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
446 	.ubwc_version = DPU_HW_UBWC_VER_40,
447 	.has_src_split = true,
448 	.has_dim_layer = true,
449 	.has_idle_pc = true,
450 	.has_3d_merge = true,
451 	.max_linewidth = 5120,
452 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
453 };
454 
455 static const struct dpu_caps sm8550_dpu_caps = {
456 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
457 	.max_mixer_blendstages = 0xb,
458 	.qseed_type = DPU_SSPP_SCALER_QSEED3LITE,
459 	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */
460 	.ubwc_version = DPU_HW_UBWC_VER_40,
461 	.has_src_split = true,
462 	.has_dim_layer = true,
463 	.has_idle_pc = true,
464 	.has_3d_merge = true,
465 	.max_linewidth = 5120,
466 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
467 };
468 
469 static const struct dpu_caps sc7280_dpu_caps = {
470 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
471 	.max_mixer_blendstages = 0x7,
472 	.qseed_type = DPU_SSPP_SCALER_QSEED4,
473 	.smart_dma_rev = DPU_SSPP_SMART_DMA_V2,
474 	.ubwc_version = DPU_HW_UBWC_VER_30,
475 	.has_dim_layer = true,
476 	.has_idle_pc = true,
477 	.max_linewidth = 2400,
478 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
479 };
480 
481 static const struct dpu_mdp_cfg msm8998_mdp[] = {
482 	{
483 	.name = "top_0", .id = MDP_TOP,
484 	.base = 0x0, .len = 0x458,
485 	.features = 0,
486 	.highest_bank_bit = 0x2,
487 	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
488 			.reg_off = 0x2AC, .bit_off = 0},
489 	.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
490 			.reg_off = 0x2B4, .bit_off = 0},
491 	.clk_ctrls[DPU_CLK_CTRL_VIG2] = {
492 			.reg_off = 0x2BC, .bit_off = 0},
493 	.clk_ctrls[DPU_CLK_CTRL_VIG3] = {
494 			.reg_off = 0x2C4, .bit_off = 0},
495 	.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
496 			.reg_off = 0x2AC, .bit_off = 8},
497 	.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
498 			.reg_off = 0x2B4, .bit_off = 8},
499 	.clk_ctrls[DPU_CLK_CTRL_DMA2] = {
500 			.reg_off = 0x2C4, .bit_off = 8},
501 	.clk_ctrls[DPU_CLK_CTRL_DMA3] = {
502 			.reg_off = 0x2C4, .bit_off = 12},
503 	.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
504 			.reg_off = 0x3A8, .bit_off = 15},
505 	.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
506 			.reg_off = 0x3B0, .bit_off = 15},
507 	},
508 };
509 
510 static const struct dpu_mdp_cfg sdm845_mdp[] = {
511 	{
512 	.name = "top_0", .id = MDP_TOP,
513 	.base = 0x0, .len = 0x45C,
514 	.features = BIT(DPU_MDP_AUDIO_SELECT),
515 	.highest_bank_bit = 0x2,
516 	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
517 			.reg_off = 0x2AC, .bit_off = 0},
518 	.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
519 			.reg_off = 0x2B4, .bit_off = 0},
520 	.clk_ctrls[DPU_CLK_CTRL_VIG2] = {
521 			.reg_off = 0x2BC, .bit_off = 0},
522 	.clk_ctrls[DPU_CLK_CTRL_VIG3] = {
523 			.reg_off = 0x2C4, .bit_off = 0},
524 	.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
525 			.reg_off = 0x2AC, .bit_off = 8},
526 	.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
527 			.reg_off = 0x2B4, .bit_off = 8},
528 	.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
529 			.reg_off = 0x2BC, .bit_off = 8},
530 	.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
531 			.reg_off = 0x2C4, .bit_off = 8},
532 	},
533 };
534 
535 static const struct dpu_mdp_cfg sc7180_mdp[] = {
536 	{
537 	.name = "top_0", .id = MDP_TOP,
538 	.base = 0x0, .len = 0x494,
539 	.features = 0,
540 	.highest_bank_bit = 0x3,
541 	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
542 		.reg_off = 0x2AC, .bit_off = 0},
543 	.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
544 		.reg_off = 0x2AC, .bit_off = 8},
545 	.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
546 		.reg_off = 0x2B4, .bit_off = 8},
547 	.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
548 		.reg_off = 0x2C4, .bit_off = 8},
549 	.clk_ctrls[DPU_CLK_CTRL_WB2] = {
550 		.reg_off = 0x3B8, .bit_off = 24},
551 	},
552 };
553 
554 static const struct dpu_mdp_cfg sc8180x_mdp[] = {
555 	{
556 	.name = "top_0", .id = MDP_TOP,
557 	.base = 0x0, .len = 0x45C,
558 	.features = BIT(DPU_MDP_AUDIO_SELECT),
559 	.highest_bank_bit = 0x3,
560 	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
561 			.reg_off = 0x2AC, .bit_off = 0},
562 	.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
563 			.reg_off = 0x2B4, .bit_off = 0},
564 	.clk_ctrls[DPU_CLK_CTRL_VIG2] = {
565 			.reg_off = 0x2BC, .bit_off = 0},
566 	.clk_ctrls[DPU_CLK_CTRL_VIG3] = {
567 			.reg_off = 0x2C4, .bit_off = 0},
568 	.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
569 			.reg_off = 0x2AC, .bit_off = 8},
570 	.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
571 			.reg_off = 0x2B4, .bit_off = 8},
572 	.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
573 			.reg_off = 0x2BC, .bit_off = 8},
574 	.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
575 			.reg_off = 0x2C4, .bit_off = 8},
576 	},
577 };
578 
579 static const struct dpu_mdp_cfg sm6115_mdp[] = {
580 	{
581 	.name = "top_0", .id = MDP_TOP,
582 	.base = 0x0, .len = 0x494,
583 	.features = 0,
584 	.highest_bank_bit = 0x1,
585 	.ubwc_swizzle = 0x7,
586 	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
587 		.reg_off = 0x2ac, .bit_off = 0},
588 	.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
589 		.reg_off = 0x2ac, .bit_off = 8},
590 	},
591 };
592 
593 static const struct dpu_mdp_cfg sm8250_mdp[] = {
594 	{
595 	.name = "top_0", .id = MDP_TOP,
596 	.base = 0x0, .len = 0x494,
597 	.features = 0,
598 	.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
599 	.ubwc_swizzle = 0x6,
600 	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
601 			.reg_off = 0x2AC, .bit_off = 0},
602 	.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
603 			.reg_off = 0x2B4, .bit_off = 0},
604 	.clk_ctrls[DPU_CLK_CTRL_VIG2] = {
605 			.reg_off = 0x2BC, .bit_off = 0},
606 	.clk_ctrls[DPU_CLK_CTRL_VIG3] = {
607 			.reg_off = 0x2C4, .bit_off = 0},
608 	.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
609 			.reg_off = 0x2AC, .bit_off = 8},
610 	.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
611 			.reg_off = 0x2B4, .bit_off = 8},
612 	.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
613 			.reg_off = 0x2BC, .bit_off = 8},
614 	.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
615 			.reg_off = 0x2C4, .bit_off = 8},
616 	.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
617 			.reg_off = 0x2BC, .bit_off = 20},
618 	.clk_ctrls[DPU_CLK_CTRL_WB2] = {
619 			.reg_off = 0x3B8, .bit_off = 24},
620 	},
621 };
622 
623 static const struct dpu_mdp_cfg sm8350_mdp[] = {
624 	{
625 	.name = "top_0", .id = MDP_TOP,
626 	.base = 0x0, .len = 0x494,
627 	.features = 0,
628 	.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
629 	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
630 			.reg_off = 0x2ac, .bit_off = 0},
631 	.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
632 			.reg_off = 0x2b4, .bit_off = 0},
633 	.clk_ctrls[DPU_CLK_CTRL_VIG2] = {
634 			.reg_off = 0x2bc, .bit_off = 0},
635 	.clk_ctrls[DPU_CLK_CTRL_VIG3] = {
636 			.reg_off = 0x2c4, .bit_off = 0},
637 	.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
638 			.reg_off = 0x2ac, .bit_off = 8},
639 	.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
640 			.reg_off = 0x2b4, .bit_off = 8},
641 	.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
642 			.reg_off = 0x2bc, .bit_off = 8},
643 	.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
644 			.reg_off = 0x2c4, .bit_off = 8},
645 	.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
646 			.reg_off = 0x2bc, .bit_off = 20},
647 	},
648 };
649 
650 static const struct dpu_mdp_cfg sm8450_mdp[] = {
651 	{
652 	.name = "top_0", .id = MDP_TOP,
653 	.base = 0x0, .len = 0x494,
654 	.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
655 	.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
656 	.ubwc_swizzle = 0x6,
657 	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
658 			.reg_off = 0x2AC, .bit_off = 0},
659 	.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
660 			.reg_off = 0x2B4, .bit_off = 0},
661 	.clk_ctrls[DPU_CLK_CTRL_VIG2] = {
662 			.reg_off = 0x2BC, .bit_off = 0},
663 	.clk_ctrls[DPU_CLK_CTRL_VIG3] = {
664 			.reg_off = 0x2C4, .bit_off = 0},
665 	.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
666 			.reg_off = 0x2AC, .bit_off = 8},
667 	.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
668 			.reg_off = 0x2B4, .bit_off = 8},
669 	.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
670 			.reg_off = 0x2BC, .bit_off = 8},
671 	.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
672 			.reg_off = 0x2C4, .bit_off = 8},
673 	.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
674 			.reg_off = 0x2BC, .bit_off = 20},
675 	},
676 };
677 
678 static const struct dpu_mdp_cfg sc7280_mdp[] = {
679 	{
680 	.name = "top_0", .id = MDP_TOP,
681 	.base = 0x0, .len = 0x2014,
682 	.highest_bank_bit = 0x1,
683 	.ubwc_swizzle = 0x6,
684 	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
685 		.reg_off = 0x2AC, .bit_off = 0},
686 	.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
687 		.reg_off = 0x2AC, .bit_off = 8},
688 	.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
689 		.reg_off = 0x2B4, .bit_off = 8},
690 	.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
691 		.reg_off = 0x2C4, .bit_off = 8},
692 	},
693 };
694 
695 static const struct dpu_mdp_cfg sc8280xp_mdp[] = {
696 	{
697 	.name = "top_0", .id = MDP_TOP,
698 	.base = 0x0, .len = 0x494,
699 	.features = 0,
700 	.highest_bank_bit = 2,
701 	.ubwc_swizzle = 6,
702 	.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0},
703 	.clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0},
704 	.clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0},
705 	.clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0},
706 	.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8},
707 	.clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8},
708 	.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x2bc, .bit_off = 8},
709 	.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { .reg_off = 0x2c4, .bit_off = 8},
710 	.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20},
711 	},
712 };
713 
714 static const struct dpu_mdp_cfg sm8550_mdp[] = {
715 	{
716 	.name = "top_0", .id = MDP_TOP,
717 	.base = 0, .len = 0x494,
718 	.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
719 	.highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */
720 	.ubwc_swizzle = 0x6,
721 	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
722 			.reg_off = 0x4330, .bit_off = 0},
723 	.clk_ctrls[DPU_CLK_CTRL_VIG1] = {
724 			.reg_off = 0x6330, .bit_off = 0},
725 	.clk_ctrls[DPU_CLK_CTRL_VIG2] = {
726 			.reg_off = 0x8330, .bit_off = 0},
727 	.clk_ctrls[DPU_CLK_CTRL_VIG3] = {
728 			.reg_off = 0xa330, .bit_off = 0},
729 	.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
730 			.reg_off = 0x24330, .bit_off = 0},
731 	.clk_ctrls[DPU_CLK_CTRL_DMA1] = {
732 			.reg_off = 0x26330, .bit_off = 0},
733 	.clk_ctrls[DPU_CLK_CTRL_DMA2] = {
734 			.reg_off = 0x28330, .bit_off = 0},
735 	.clk_ctrls[DPU_CLK_CTRL_DMA3] = {
736 			.reg_off = 0x2a330, .bit_off = 0},
737 	.clk_ctrls[DPU_CLK_CTRL_CURSOR0] = {
738 			.reg_off = 0x2c330, .bit_off = 0},
739 	.clk_ctrls[DPU_CLK_CTRL_CURSOR1] = {
740 			.reg_off = 0x2e330, .bit_off = 0},
741 	.clk_ctrls[DPU_CLK_CTRL_REG_DMA] = {
742 			.reg_off = 0x2bc, .bit_off = 20},
743 	},
744 };
745 
746 static const struct dpu_mdp_cfg qcm2290_mdp[] = {
747 	{
748 	.name = "top_0", .id = MDP_TOP,
749 	.base = 0x0, .len = 0x494,
750 	.features = 0,
751 	.highest_bank_bit = 0x2,
752 	.clk_ctrls[DPU_CLK_CTRL_VIG0] = {
753 		.reg_off = 0x2AC, .bit_off = 0},
754 	.clk_ctrls[DPU_CLK_CTRL_DMA0] = {
755 		.reg_off = 0x2AC, .bit_off = 8},
756 	},
757 };
758 
759 /*************************************************************
760  * CTL sub blocks config
761  *************************************************************/
762 static const struct dpu_ctl_cfg msm8998_ctl[] = {
763 	{
764 	.name = "ctl_0", .id = CTL_0,
765 	.base = 0x1000, .len = 0x94,
766 	.features = BIT(DPU_CTL_SPLIT_DISPLAY),
767 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
768 	},
769 	{
770 	.name = "ctl_1", .id = CTL_1,
771 	.base = 0x1200, .len = 0x94,
772 	.features = 0,
773 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
774 	},
775 	{
776 	.name = "ctl_2", .id = CTL_2,
777 	.base = 0x1400, .len = 0x94,
778 	.features = BIT(DPU_CTL_SPLIT_DISPLAY),
779 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
780 	},
781 	{
782 	.name = "ctl_3", .id = CTL_3,
783 	.base = 0x1600, .len = 0x94,
784 	.features = 0,
785 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
786 	},
787 	{
788 	.name = "ctl_4", .id = CTL_4,
789 	.base = 0x1800, .len = 0x94,
790 	.features = 0,
791 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
792 	},
793 };
794 
795 static const struct dpu_ctl_cfg sdm845_ctl[] = {
796 	{
797 	.name = "ctl_0", .id = CTL_0,
798 	.base = 0x1000, .len = 0xE4,
799 	.features = BIT(DPU_CTL_SPLIT_DISPLAY),
800 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
801 	},
802 	{
803 	.name = "ctl_1", .id = CTL_1,
804 	.base = 0x1200, .len = 0xE4,
805 	.features = BIT(DPU_CTL_SPLIT_DISPLAY),
806 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
807 	},
808 	{
809 	.name = "ctl_2", .id = CTL_2,
810 	.base = 0x1400, .len = 0xE4,
811 	.features = 0,
812 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
813 	},
814 	{
815 	.name = "ctl_3", .id = CTL_3,
816 	.base = 0x1600, .len = 0xE4,
817 	.features = 0,
818 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
819 	},
820 	{
821 	.name = "ctl_4", .id = CTL_4,
822 	.base = 0x1800, .len = 0xE4,
823 	.features = 0,
824 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
825 	},
826 };
827 
828 static const struct dpu_ctl_cfg sc7180_ctl[] = {
829 	{
830 	.name = "ctl_0", .id = CTL_0,
831 	.base = 0x1000, .len = 0xE4,
832 	.features = BIT(DPU_CTL_ACTIVE_CFG),
833 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
834 	},
835 	{
836 	.name = "ctl_1", .id = CTL_1,
837 	.base = 0x1200, .len = 0xE4,
838 	.features = BIT(DPU_CTL_ACTIVE_CFG),
839 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
840 	},
841 	{
842 	.name = "ctl_2", .id = CTL_2,
843 	.base = 0x1400, .len = 0xE4,
844 	.features = BIT(DPU_CTL_ACTIVE_CFG),
845 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
846 	},
847 };
848 
849 static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
850 	{
851 	.name = "ctl_0", .id = CTL_0,
852 	.base = 0x15000, .len = 0x204,
853 	.features = CTL_SC7280_MASK,
854 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
855 	},
856 	{
857 	.name = "ctl_1", .id = CTL_1,
858 	.base = 0x16000, .len = 0x204,
859 	.features = CTL_SC7280_MASK,
860 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
861 	},
862 	{
863 	.name = "ctl_2", .id = CTL_2,
864 	.base = 0x17000, .len = 0x204,
865 	.features = CTL_SC7280_MASK,
866 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
867 	},
868 	{
869 	.name = "ctl_3", .id = CTL_3,
870 	.base = 0x18000, .len = 0x204,
871 	.features = CTL_SC7280_MASK,
872 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
873 	},
874 	{
875 	.name = "ctl_4", .id = CTL_4,
876 	.base = 0x19000, .len = 0x204,
877 	.features = CTL_SC7280_MASK,
878 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
879 	},
880 	{
881 	.name = "ctl_5", .id = CTL_5,
882 	.base = 0x1a000, .len = 0x204,
883 	.features = CTL_SC7280_MASK,
884 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
885 	},
886 };
887 
888 static const struct dpu_ctl_cfg sm8150_ctl[] = {
889 	{
890 	.name = "ctl_0", .id = CTL_0,
891 	.base = 0x1000, .len = 0x1e0,
892 	.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
893 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
894 	},
895 	{
896 	.name = "ctl_1", .id = CTL_1,
897 	.base = 0x1200, .len = 0x1e0,
898 	.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
899 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
900 	},
901 	{
902 	.name = "ctl_2", .id = CTL_2,
903 	.base = 0x1400, .len = 0x1e0,
904 	.features = BIT(DPU_CTL_ACTIVE_CFG),
905 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
906 	},
907 	{
908 	.name = "ctl_3", .id = CTL_3,
909 	.base = 0x1600, .len = 0x1e0,
910 	.features = BIT(DPU_CTL_ACTIVE_CFG),
911 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
912 	},
913 	{
914 	.name = "ctl_4", .id = CTL_4,
915 	.base = 0x1800, .len = 0x1e0,
916 	.features = BIT(DPU_CTL_ACTIVE_CFG),
917 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
918 	},
919 	{
920 	.name = "ctl_5", .id = CTL_5,
921 	.base = 0x1a00, .len = 0x1e0,
922 	.features = BIT(DPU_CTL_ACTIVE_CFG),
923 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
924 	},
925 };
926 
927 static const struct dpu_ctl_cfg sm8350_ctl[] = {
928 	{
929 	.name = "ctl_0", .id = CTL_0,
930 	.base = 0x15000, .len = 0x1e8,
931 	.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
932 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
933 	},
934 	{
935 	.name = "ctl_1", .id = CTL_1,
936 	.base = 0x16000, .len = 0x1e8,
937 	.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
938 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
939 	},
940 	{
941 	.name = "ctl_2", .id = CTL_2,
942 	.base = 0x17000, .len = 0x1e8,
943 	.features = CTL_SC7280_MASK,
944 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
945 	},
946 	{
947 	.name = "ctl_3", .id = CTL_3,
948 	.base = 0x18000, .len = 0x1e8,
949 	.features = CTL_SC7280_MASK,
950 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
951 	},
952 	{
953 	.name = "ctl_4", .id = CTL_4,
954 	.base = 0x19000, .len = 0x1e8,
955 	.features = CTL_SC7280_MASK,
956 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
957 	},
958 	{
959 	.name = "ctl_5", .id = CTL_5,
960 	.base = 0x1a000, .len = 0x1e8,
961 	.features = CTL_SC7280_MASK,
962 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
963 	},
964 };
965 
966 static const struct dpu_ctl_cfg sm8450_ctl[] = {
967 	{
968 	.name = "ctl_0", .id = CTL_0,
969 	.base = 0x15000, .len = 0x204,
970 	.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE),
971 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
972 	},
973 	{
974 	.name = "ctl_1", .id = CTL_1,
975 	.base = 0x16000, .len = 0x204,
976 	.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
977 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
978 	},
979 	{
980 	.name = "ctl_2", .id = CTL_2,
981 	.base = 0x17000, .len = 0x204,
982 	.features = CTL_SC7280_MASK,
983 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
984 	},
985 	{
986 	.name = "ctl_3", .id = CTL_3,
987 	.base = 0x18000, .len = 0x204,
988 	.features = CTL_SC7280_MASK,
989 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
990 	},
991 	{
992 	.name = "ctl_4", .id = CTL_4,
993 	.base = 0x19000, .len = 0x204,
994 	.features = CTL_SC7280_MASK,
995 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
996 	},
997 	{
998 	.name = "ctl_5", .id = CTL_5,
999 	.base = 0x1a000, .len = 0x204,
1000 	.features = CTL_SC7280_MASK,
1001 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
1002 	},
1003 };
1004 
1005 static const struct dpu_ctl_cfg sm8550_ctl[] = {
1006 	{
1007 	.name = "ctl_0", .id = CTL_0,
1008 	.base = 0x15000, .len = 0x290,
1009 	.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
1010 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
1011 	},
1012 	{
1013 	.name = "ctl_1", .id = CTL_1,
1014 	.base = 0x16000, .len = 0x290,
1015 	.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
1016 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
1017 	},
1018 	{
1019 	.name = "ctl_2", .id = CTL_2,
1020 	.base = 0x17000, .len = 0x290,
1021 	.features = CTL_SM8550_MASK,
1022 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
1023 	},
1024 	{
1025 	.name = "ctl_3", .id = CTL_3,
1026 	.base = 0x18000, .len = 0x290,
1027 	.features = CTL_SM8550_MASK,
1028 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
1029 	},
1030 	{
1031 	.name = "ctl_4", .id = CTL_4,
1032 	.base = 0x19000, .len = 0x290,
1033 	.features = CTL_SM8550_MASK,
1034 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
1035 	},
1036 	{
1037 	.name = "ctl_5", .id = CTL_5,
1038 	.base = 0x1a000, .len = 0x290,
1039 	.features = CTL_SM8550_MASK,
1040 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
1041 	},
1042 };
1043 
1044 static const struct dpu_ctl_cfg sc7280_ctl[] = {
1045 	{
1046 	.name = "ctl_0", .id = CTL_0,
1047 	.base = 0x15000, .len = 0x1E8,
1048 	.features = CTL_SC7280_MASK,
1049 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
1050 	},
1051 	{
1052 	.name = "ctl_1", .id = CTL_1,
1053 	.base = 0x16000, .len = 0x1E8,
1054 	.features = CTL_SC7280_MASK,
1055 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
1056 	},
1057 	{
1058 	.name = "ctl_2", .id = CTL_2,
1059 	.base = 0x17000, .len = 0x1E8,
1060 	.features = CTL_SC7280_MASK,
1061 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
1062 	},
1063 	{
1064 	.name = "ctl_3", .id = CTL_3,
1065 	.base = 0x18000, .len = 0x1E8,
1066 	.features = CTL_SC7280_MASK,
1067 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
1068 	},
1069 };
1070 
1071 static const struct dpu_ctl_cfg qcm2290_ctl[] = {
1072 	{
1073 	.name = "ctl_0", .id = CTL_0,
1074 	.base = 0x1000, .len = 0x1dc,
1075 	.features = BIT(DPU_CTL_ACTIVE_CFG),
1076 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
1077 	},
1078 };
1079 
1080 /*************************************************************
1081  * SSPP sub blocks config
1082  *************************************************************/
1083 
1084 /* SSPP common configuration */
1085 #define _VIG_SBLK(num, sdma_pri, qseed_ver) \
1086 	{ \
1087 	.maxdwnscale = MAX_DOWNSCALE_RATIO, \
1088 	.maxupscale = MAX_UPSCALE_RATIO, \
1089 	.smart_dma_priority = sdma_pri, \
1090 	.src_blk = {.name = STRCAT("sspp_src_", num), \
1091 		.id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
1092 	.scaler_blk = {.name = STRCAT("sspp_scaler", num), \
1093 		.id = qseed_ver, \
1094 		.base = 0xa00, .len = 0xa0,}, \
1095 	.csc_blk = {.name = STRCAT("sspp_csc", num), \
1096 		.id = DPU_SSPP_CSC_10BIT, \
1097 		.base = 0x1a00, .len = 0x100,}, \
1098 	.format_list = plane_formats_yuv, \
1099 	.num_formats = ARRAY_SIZE(plane_formats_yuv), \
1100 	.virt_format_list = plane_formats, \
1101 	.virt_num_formats = ARRAY_SIZE(plane_formats), \
1102 	.rotation_cfg = NULL, \
1103 	}
1104 
1105 #define _VIG_SBLK_ROT(num, sdma_pri, qseed_ver, rot_cfg) \
1106 	{ \
1107 	.maxdwnscale = MAX_DOWNSCALE_RATIO, \
1108 	.maxupscale = MAX_UPSCALE_RATIO, \
1109 	.smart_dma_priority = sdma_pri, \
1110 	.src_blk = {.name = STRCAT("sspp_src_", num), \
1111 		.id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
1112 	.scaler_blk = {.name = STRCAT("sspp_scaler", num), \
1113 		.id = qseed_ver, \
1114 		.base = 0xa00, .len = 0xa0,}, \
1115 	.csc_blk = {.name = STRCAT("sspp_csc", num), \
1116 		.id = DPU_SSPP_CSC_10BIT, \
1117 		.base = 0x1a00, .len = 0x100,}, \
1118 	.format_list = plane_formats_yuv, \
1119 	.num_formats = ARRAY_SIZE(plane_formats_yuv), \
1120 	.virt_format_list = plane_formats, \
1121 	.virt_num_formats = ARRAY_SIZE(plane_formats), \
1122 	.rotation_cfg = rot_cfg, \
1123 	}
1124 
1125 #define _DMA_SBLK(num, sdma_pri) \
1126 	{ \
1127 	.maxdwnscale = SSPP_UNITY_SCALE, \
1128 	.maxupscale = SSPP_UNITY_SCALE, \
1129 	.smart_dma_priority = sdma_pri, \
1130 	.src_blk = {.name = STRCAT("sspp_src_", num), \
1131 		.id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
1132 	.format_list = plane_formats, \
1133 	.num_formats = ARRAY_SIZE(plane_formats), \
1134 	.virt_format_list = plane_formats, \
1135 	.virt_num_formats = ARRAY_SIZE(plane_formats), \
1136 	}
1137 
1138 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 =
1139 				_VIG_SBLK("0", 0, DPU_SSPP_SCALER_QSEED3);
1140 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 =
1141 				_VIG_SBLK("1", 0, DPU_SSPP_SCALER_QSEED3);
1142 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 =
1143 				_VIG_SBLK("2", 0, DPU_SSPP_SCALER_QSEED3);
1144 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 =
1145 				_VIG_SBLK("3", 0, DPU_SSPP_SCALER_QSEED3);
1146 
1147 static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = {
1148 	.rot_maxheight = 1088,
1149 	.rot_num_formats = ARRAY_SIZE(rotation_v2_formats),
1150 	.rot_format_list = rotation_v2_formats,
1151 };
1152 
1153 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 =
1154 				_VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3);
1155 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 =
1156 				_VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3);
1157 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 =
1158 				_VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3);
1159 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 =
1160 				_VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3);
1161 
1162 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1);
1163 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2);
1164 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3);
1165 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4);
1166 
1167 #define SSPP_BLK(_name, _id, _base, _features, \
1168 		_sblk, _xinid, _type, _clkctrl) \
1169 	{ \
1170 	.name = _name, .id = _id, \
1171 	.base = _base, .len = 0x1c8, \
1172 	.features = _features, \
1173 	.sblk = &_sblk, \
1174 	.xin_id = _xinid, \
1175 	.type = _type, \
1176 	.clk_ctrl = _clkctrl \
1177 	}
1178 
1179 static const struct dpu_sspp_cfg msm8998_sspp[] = {
1180 	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_MSM8998_MASK,
1181 		msm8998_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
1182 	SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_MSM8998_MASK,
1183 		msm8998_vig_sblk_1, 4,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
1184 	SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_MSM8998_MASK,
1185 		msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
1186 	SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_MSM8998_MASK,
1187 		msm8998_vig_sblk_3, 12,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
1188 	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_MSM8998_MASK,
1189 		sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
1190 	SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_MSM8998_MASK,
1191 		sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
1192 	SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_CURSOR_MSM8998_MASK,
1193 		sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
1194 	SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000,  DMA_CURSOR_MSM8998_MASK,
1195 		sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
1196 };
1197 
1198 static const struct dpu_sspp_cfg sdm845_sspp[] = {
1199 	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK,
1200 		sdm845_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
1201 	SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK,
1202 		sdm845_vig_sblk_1, 4,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
1203 	SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK,
1204 		sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
1205 	SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK,
1206 		sdm845_vig_sblk_3, 12,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
1207 	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
1208 		sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
1209 	SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_SDM845_MASK,
1210 		sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
1211 	SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_CURSOR_SDM845_MASK,
1212 		sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
1213 	SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000,  DMA_CURSOR_SDM845_MASK,
1214 		sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
1215 };
1216 
1217 static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 =
1218 				_VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4);
1219 
1220 static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
1221 			_VIG_SBLK_ROT("0", 4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2);
1222 
1223 static const struct dpu_sspp_cfg sc7180_sspp[] = {
1224 	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
1225 		sc7180_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
1226 	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
1227 		sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
1228 	SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_CURSOR_SDM845_MASK,
1229 		sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
1230 	SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_CURSOR_SDM845_MASK,
1231 		sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
1232 };
1233 
1234 static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
1235 				_VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED3LITE);
1236 
1237 static const struct dpu_sspp_cfg sm6115_sspp[] = {
1238 	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,
1239 		sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
1240 	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
1241 		sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
1242 };
1243 
1244 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
1245 				_VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);
1246 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
1247 				_VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE);
1248 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 =
1249 				_VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE);
1250 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 =
1251 				_VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE);
1252 
1253 static const struct dpu_sspp_cfg sm8250_sspp[] = {
1254 	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,
1255 		sm8250_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
1256 	SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK,
1257 		sm8250_vig_sblk_1, 4,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
1258 	SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK,
1259 		sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
1260 	SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK,
1261 		sm8250_vig_sblk_3, 12,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
1262 	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
1263 		sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
1264 	SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_SDM845_MASK,
1265 		sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
1266 	SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_CURSOR_SDM845_MASK,
1267 		sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
1268 	SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000,  DMA_CURSOR_SDM845_MASK,
1269 		sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
1270 };
1271 
1272 static const struct dpu_sspp_sub_blks sm8450_vig_sblk_0 =
1273 				_VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);
1274 static const struct dpu_sspp_sub_blks sm8450_vig_sblk_1 =
1275 				_VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE);
1276 static const struct dpu_sspp_sub_blks sm8450_vig_sblk_2 =
1277 				_VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE);
1278 static const struct dpu_sspp_sub_blks sm8450_vig_sblk_3 =
1279 				_VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE);
1280 
1281 static const struct dpu_sspp_cfg sm8450_sspp[] = {
1282 	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
1283 		sm8450_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
1284 	SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK,
1285 		sm8450_vig_sblk_1, 4,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
1286 	SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK,
1287 		sm8450_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
1288 	SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK,
1289 		sm8450_vig_sblk_3, 12,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
1290 	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
1291 		sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
1292 	SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_SDM845_MASK,
1293 		sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
1294 	SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_CURSOR_SDM845_MASK,
1295 		sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
1296 	SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000,  DMA_CURSOR_SDM845_MASK,
1297 		sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
1298 };
1299 
1300 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 =
1301 				_VIG_SBLK("0", 7, DPU_SSPP_SCALER_QSEED3LITE);
1302 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 =
1303 				_VIG_SBLK("1", 8, DPU_SSPP_SCALER_QSEED3LITE);
1304 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 =
1305 				_VIG_SBLK("2", 9, DPU_SSPP_SCALER_QSEED3LITE);
1306 static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 =
1307 				_VIG_SBLK("3", 10, DPU_SSPP_SCALER_QSEED3LITE);
1308 static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK("12", 5);
1309 static const struct dpu_sspp_sub_blks sd8550_dma_sblk_5 = _DMA_SBLK("13", 6);
1310 
1311 static const struct dpu_sspp_cfg sm8550_sspp[] = {
1312 	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK,
1313 		sm8550_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
1314 	SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SC7180_MASK,
1315 		sm8550_vig_sblk_1, 4,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
1316 	SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SC7180_MASK,
1317 		sm8550_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
1318 	SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SC7180_MASK,
1319 		sm8550_vig_sblk_3, 12,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
1320 	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
1321 		sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
1322 	SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_SDM845_MASK,
1323 		sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
1324 	SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_SDM845_MASK,
1325 		sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
1326 	SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000,  DMA_SDM845_MASK,
1327 		sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
1328 	SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000,  DMA_CURSOR_SDM845_MASK,
1329 		sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
1330 	SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000,  DMA_CURSOR_SDM845_MASK,
1331 		sd8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
1332 };
1333 
1334 static const struct dpu_sspp_cfg sc7280_sspp[] = {
1335 	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK,
1336 		sc7280_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
1337 	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
1338 		sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
1339 	SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000,  DMA_CURSOR_SDM845_MASK,
1340 		sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
1341 	SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000,  DMA_CURSOR_SDM845_MASK,
1342 		sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
1343 };
1344 
1345 static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_0 =
1346 				_VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE);
1347 static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_1 =
1348 				_VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE);
1349 static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_2 =
1350 				_VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE);
1351 static const struct dpu_sspp_sub_blks sc8280xp_vig_sblk_3 =
1352 				_VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE);
1353 
1354 static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
1355 	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK,
1356 		 sc8280xp_vig_sblk_0, 0,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
1357 	SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK,
1358 		 sc8280xp_vig_sblk_1, 4,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1),
1359 	SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK,
1360 		 sc8280xp_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2),
1361 	SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK,
1362 		 sc8280xp_vig_sblk_3, 12,  SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3),
1363 	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK,
1364 		 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
1365 	SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK,
1366 		 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
1367 	SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK,
1368 		 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0),
1369 	SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK,
1370 		 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1),
1371 };
1372 
1373 #define _VIG_SBLK_NOSCALE(num, sdma_pri) \
1374 	{ \
1375 	.maxdwnscale = SSPP_UNITY_SCALE, \
1376 	.maxupscale = SSPP_UNITY_SCALE, \
1377 	.smart_dma_priority = sdma_pri, \
1378 	.src_blk = {.name = STRCAT("sspp_src_", num), \
1379 		.id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \
1380 	.format_list = plane_formats_yuv, \
1381 	.num_formats = ARRAY_SIZE(plane_formats_yuv), \
1382 	.virt_format_list = plane_formats, \
1383 	.virt_num_formats = ARRAY_SIZE(plane_formats), \
1384 	}
1385 
1386 static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE("0", 2);
1387 static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1);
1388 
1389 static const struct dpu_sspp_cfg qcm2290_sspp[] = {
1390 	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK,
1391 		 qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
1392 	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000,  DMA_SDM845_MASK,
1393 		 qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
1394 };
1395 
1396 /*************************************************************
1397  * MIXER sub blocks config
1398  *************************************************************/
1399 
1400 #define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \
1401 	{ \
1402 	.name = _name, .id = _id, \
1403 	.base = _base, .len = 0x320, \
1404 	.features = _fmask, \
1405 	.sblk = _sblk, \
1406 	.pingpong = _pp, \
1407 	.lm_pair_mask = (1 << _lmpair), \
1408 	.dspp = _dspp \
1409 	}
1410 
1411 /* MSM8998 */
1412 
1413 static const struct dpu_lm_sub_blks msm8998_lm_sblk = {
1414 	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
1415 	.maxblendstages = 7, /* excluding base layer */
1416 	.blendstage_base = { /* offsets relative to mixer base */
1417 		0x20, 0x50, 0x80, 0xb0, 0x230,
1418 		0x260, 0x290
1419 	},
1420 };
1421 
1422 static const struct dpu_lm_cfg msm8998_lm[] = {
1423 	LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK,
1424 		&msm8998_lm_sblk, PINGPONG_0, LM_2, DSPP_0),
1425 	LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK,
1426 		&msm8998_lm_sblk, PINGPONG_1, LM_5, DSPP_1),
1427 	LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK,
1428 		&msm8998_lm_sblk, PINGPONG_2, LM_0, 0),
1429 	LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK,
1430 		&msm8998_lm_sblk, PINGPONG_MAX, 0, 0),
1431 	LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK,
1432 		&msm8998_lm_sblk, PINGPONG_MAX, 0, 0),
1433 	LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK,
1434 		&msm8998_lm_sblk, PINGPONG_3, LM_1, 0),
1435 };
1436 
1437 /* SDM845 */
1438 
1439 static const struct dpu_lm_sub_blks sdm845_lm_sblk = {
1440 	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
1441 	.maxblendstages = 11, /* excluding base layer */
1442 	.blendstage_base = { /* offsets relative to mixer base */
1443 		0x20, 0x38, 0x50, 0x68, 0x80, 0x98,
1444 		0xb0, 0xc8, 0xe0, 0xf8, 0x110
1445 	},
1446 };
1447 
1448 static const struct dpu_lm_cfg sdm845_lm[] = {
1449 	LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
1450 		&sdm845_lm_sblk, PINGPONG_0, LM_1, 0),
1451 	LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
1452 		&sdm845_lm_sblk, PINGPONG_1, LM_0, 0),
1453 	LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
1454 		&sdm845_lm_sblk, PINGPONG_2, LM_5, 0),
1455 	LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK,
1456 		&sdm845_lm_sblk, PINGPONG_MAX, 0, 0),
1457 	LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK,
1458 		&sdm845_lm_sblk, PINGPONG_MAX, 0, 0),
1459 	LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
1460 		&sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
1461 };
1462 
1463 /* SC7180 */
1464 
1465 static const struct dpu_lm_sub_blks sc7180_lm_sblk = {
1466 	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
1467 	.maxblendstages = 7, /* excluding base layer */
1468 	.blendstage_base = { /* offsets relative to mixer base */
1469 		0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0
1470 	},
1471 };
1472 
1473 static const struct dpu_lm_cfg sc7180_lm[] = {
1474 	LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
1475 		&sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
1476 	LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
1477 		&sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
1478 };
1479 
1480 /* SC8280XP */
1481 
1482 static const struct dpu_lm_cfg sc8280xp_lm[] = {
1483 	LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
1484 	LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
1485 	LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_2, LM_3, DSPP_2),
1486 	LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_3, LM_2, DSPP_3),
1487 	LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
1488 	LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
1489 };
1490 
1491 /* SM8150 */
1492 
1493 static const struct dpu_lm_cfg sm8150_lm[] = {
1494 	LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
1495 		&sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
1496 	LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
1497 		&sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
1498 	LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
1499 		&sdm845_lm_sblk, PINGPONG_2, LM_3, 0),
1500 	LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
1501 		&sdm845_lm_sblk, PINGPONG_3, LM_2, 0),
1502 	LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
1503 		&sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
1504 	LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
1505 		&sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
1506 };
1507 
1508 static const struct dpu_lm_cfg sc7280_lm[] = {
1509 	LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
1510 		&sc7180_lm_sblk, PINGPONG_0, 0, DSPP_0),
1511 	LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
1512 		&sc7180_lm_sblk, PINGPONG_2, LM_3, 0),
1513 	LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
1514 		&sc7180_lm_sblk, PINGPONG_3, LM_2, 0),
1515 };
1516 
1517 /* QCM2290 */
1518 
1519 static const struct dpu_lm_sub_blks qcm2290_lm_sblk = {
1520 	.maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
1521 	.maxblendstages = 4, /* excluding base layer */
1522 	.blendstage_base = { /* offsets relative to mixer base */
1523 		0x20, 0x38, 0x50, 0x68
1524 	},
1525 };
1526 
1527 static const struct dpu_lm_cfg qcm2290_lm[] = {
1528 	LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
1529 		&qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
1530 };
1531 
1532 /*************************************************************
1533  * DSPP sub blocks config
1534  *************************************************************/
1535 static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = {
1536 	.pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,
1537 		.len = 0x90, .version = 0x10007},
1538 	.gc = { .id = DPU_DSPP_GC, .base = 0x17c0,
1539 		.len = 0x90, .version = 0x10007},
1540 };
1541 
1542 static const struct dpu_dspp_sub_blks sc7180_dspp_sblk = {
1543 	.pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,
1544 		.len = 0x90, .version = 0x10000},
1545 };
1546 
1547 static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = {
1548 	.pcc = {.id = DPU_DSPP_PCC, .base = 0x1700,
1549 		.len = 0x90, .version = 0x40000},
1550 };
1551 
1552 #define DSPP_BLK(_name, _id, _base, _mask, _sblk) \
1553 		{\
1554 		.name = _name, .id = _id, \
1555 		.base = _base, .len = 0x1800, \
1556 		.features = _mask, \
1557 		.sblk = _sblk \
1558 		}
1559 
1560 static const struct dpu_dspp_cfg msm8998_dspp[] = {
1561 	DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_MSM8998_MASK,
1562 		 &msm8998_dspp_sblk),
1563 	DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_MSM8998_MASK,
1564 		 &msm8998_dspp_sblk),
1565 };
1566 
1567 static const struct dpu_dspp_cfg sc7180_dspp[] = {
1568 	DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
1569 		 &sc7180_dspp_sblk),
1570 };
1571 
1572 static const struct dpu_dspp_cfg sm8150_dspp[] = {
1573 	DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
1574 		 &sm8150_dspp_sblk),
1575 	DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
1576 		 &sm8150_dspp_sblk),
1577 	DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
1578 		 &sm8150_dspp_sblk),
1579 	DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
1580 		 &sm8150_dspp_sblk),
1581 };
1582 
1583 static const struct dpu_dspp_cfg qcm2290_dspp[] = {
1584 	DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
1585 		 &sm8150_dspp_sblk),
1586 };
1587 
1588 /*************************************************************
1589  * PINGPONG sub blocks config
1590  *************************************************************/
1591 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = {
1592 	.te2 = {.id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0,
1593 		.version = 0x1},
1594 	.dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0,
1595 		.len = 0x20, .version = 0x10000},
1596 };
1597 
1598 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = {
1599 	.dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0,
1600 		.len = 0x20, .version = 0x10000},
1601 };
1602 
1603 static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
1604 	.dither = {.id = DPU_PINGPONG_DITHER, .base = 0xe0,
1605 	.len = 0x20, .version = 0x20000},
1606 };
1607 
1608 #define PP_BLK_DIPHER(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
1609 	{\
1610 	.name = _name, .id = _id, \
1611 	.base = _base, .len = 0, \
1612 	.features = BIT(DPU_PINGPONG_DITHER), \
1613 	.merge_3d = _merge_3d, \
1614 	.sblk = &_sblk, \
1615 	.intr_done = _done, \
1616 	.intr_rdptr = _rdptr, \
1617 	}
1618 #define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
1619 	{\
1620 	.name = _name, .id = _id, \
1621 	.base = _base, .len = 0xd4, \
1622 	.features = PINGPONG_SDM845_SPLIT_MASK, \
1623 	.merge_3d = _merge_3d, \
1624 	.sblk = &_sblk, \
1625 	.intr_done = _done, \
1626 	.intr_rdptr = _rdptr, \
1627 	}
1628 #define PP_BLK(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \
1629 	{\
1630 	.name = _name, .id = _id, \
1631 	.base = _base, .len = 0xd4, \
1632 	.features = PINGPONG_SDM845_MASK, \
1633 	.merge_3d = _merge_3d, \
1634 	.sblk = &_sblk, \
1635 	.intr_done = _done, \
1636 	.intr_rdptr = _rdptr, \
1637 	}
1638 
1639 static const struct dpu_pingpong_cfg sdm845_pp[] = {
1640 	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te,
1641 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
1642 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
1643 	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te,
1644 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
1645 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
1646 	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk,
1647 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
1648 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
1649 	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk,
1650 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
1651 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
1652 };
1653 
1654 static struct dpu_pingpong_cfg sc7180_pp[] = {
1655 	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, -1, -1),
1656 	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1),
1657 };
1658 
1659 static struct dpu_pingpong_cfg sc8280xp_pp[] = {
1660 	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te,
1661 		  DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1),
1662 	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te,
1663 		  DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), -1),
1664 	PP_BLK_TE("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk_te,
1665 		  DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), -1),
1666 	PP_BLK_TE("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk_te,
1667 		  DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), -1),
1668 	PP_BLK_TE("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk_te,
1669 		  DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), -1),
1670 	PP_BLK_TE("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk_te,
1671 		  DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), -1),
1672 };
1673 
1674 static const struct dpu_pingpong_cfg sm8150_pp[] = {
1675 	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te,
1676 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
1677 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
1678 	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te,
1679 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
1680 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
1681 	PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk,
1682 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
1683 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
1684 	PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk,
1685 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
1686 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
1687 	PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk,
1688 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
1689 			-1),
1690 	PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk,
1691 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
1692 			-1),
1693 };
1694 
1695 static const struct dpu_pingpong_cfg sm8350_pp[] = {
1696 	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te,
1697 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
1698 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
1699 	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te,
1700 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
1701 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
1702 	PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk,
1703 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
1704 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
1705 	PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk,
1706 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
1707 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
1708 	PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk,
1709 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
1710 			-1),
1711 	PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk,
1712 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
1713 			-1),
1714 };
1715 
1716 static const struct dpu_pingpong_cfg sc7280_pp[] = {
1717 	PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1),
1718 	PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1),
1719 	PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
1720 	PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
1721 };
1722 
1723 static struct dpu_pingpong_cfg qcm2290_pp[] = {
1724 	PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk,
1725 		DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
1726 		DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
1727 };
1728 
1729 /* FIXME: interrupts */
1730 static const struct dpu_pingpong_cfg sm8450_pp[] = {
1731 	PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te,
1732 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
1733 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)),
1734 	PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te,
1735 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
1736 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)),
1737 	PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk,
1738 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
1739 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)),
1740 	PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk,
1741 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
1742 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)),
1743 	PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk,
1744 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
1745 			-1),
1746 	PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk,
1747 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
1748 			-1),
1749 	PP_BLK("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sdm845_pp_sblk,
1750 			-1,
1751 			-1),
1752 	PP_BLK("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sdm845_pp_sblk,
1753 			-1,
1754 			-1),
1755 };
1756 
1757 static const struct dpu_pingpong_cfg sm8550_pp[] = {
1758 	PP_BLK_DIPHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk,
1759 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
1760 			-1),
1761 	PP_BLK_DIPHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk,
1762 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
1763 			-1),
1764 	PP_BLK_DIPHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk,
1765 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
1766 			-1),
1767 	PP_BLK_DIPHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk,
1768 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
1769 			-1),
1770 	PP_BLK_DIPHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk,
1771 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
1772 			-1),
1773 	PP_BLK_DIPHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk,
1774 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
1775 			-1),
1776 	PP_BLK_DIPHER("pingpong_6", PINGPONG_6, 0x66000, MERGE_3D_3, sc7280_pp_sblk,
1777 			-1,
1778 			-1),
1779 	PP_BLK_DIPHER("pingpong_7", PINGPONG_7, 0x66400, MERGE_3D_3, sc7280_pp_sblk,
1780 			-1,
1781 			-1),
1782 };
1783 
1784 /*************************************************************
1785  * MERGE_3D sub blocks config
1786  *************************************************************/
1787 #define MERGE_3D_BLK(_name, _id, _base) \
1788 	{\
1789 	.name = _name, .id = _id, \
1790 	.base = _base, .len = 0x100, \
1791 	.features = MERGE_3D_SM8150_MASK, \
1792 	.sblk = NULL \
1793 	}
1794 
1795 static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
1796 	MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000),
1797 	MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100),
1798 	MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200),
1799 };
1800 
1801 static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = {
1802 	MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
1803 	MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
1804 	MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
1805 };
1806 
1807 static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = {
1808 	MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
1809 	MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
1810 	MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
1811 	MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00),
1812 };
1813 
1814 static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = {
1815 	MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000),
1816 	MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000),
1817 	MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000),
1818 	MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x66700),
1819 };
1820 
1821 /*************************************************************
1822  * DSC sub blocks config
1823  *************************************************************/
1824 #define DSC_BLK(_name, _id, _base, _features) \
1825 	{\
1826 	.name = _name, .id = _id, \
1827 	.base = _base, .len = 0x140, \
1828 	.features = _features, \
1829 	}
1830 
1831 static struct dpu_dsc_cfg sdm845_dsc[] = {
1832 	DSC_BLK("dsc_0", DSC_0, 0x80000, 0),
1833 	DSC_BLK("dsc_1", DSC_1, 0x80400, 0),
1834 	DSC_BLK("dsc_2", DSC_2, 0x80800, 0),
1835 	DSC_BLK("dsc_3", DSC_3, 0x80c00, 0),
1836 };
1837 
1838 static struct dpu_dsc_cfg sm8150_dsc[] = {
1839 	DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
1840 	DSC_BLK("dsc_1", DSC_1, 0x80400, BIT(DPU_DSC_OUTPUT_CTRL)),
1841 	DSC_BLK("dsc_2", DSC_2, 0x80800, BIT(DPU_DSC_OUTPUT_CTRL)),
1842 	DSC_BLK("dsc_3", DSC_3, 0x80c00, BIT(DPU_DSC_OUTPUT_CTRL)),
1843 };
1844 
1845 /*************************************************************
1846  * INTF sub blocks config
1847  *************************************************************/
1848 #define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \
1849 	{\
1850 	.name = _name, .id = _id, \
1851 	.base = _base, .len = 0x280, \
1852 	.features = _features, \
1853 	.type = _type, \
1854 	.controller_id = _ctrl_id, \
1855 	.prog_fetch_lines_worst_case = _progfetch, \
1856 	.intr_underrun = DPU_IRQ_IDX(_reg, _underrun_bit), \
1857 	.intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \
1858 	}
1859 
1860 static const struct dpu_intf_cfg msm8998_intf[] = {
1861 	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1862 	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1863 	INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
1864 	INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
1865 };
1866 
1867 static const struct dpu_intf_cfg sdm845_intf[] = {
1868 	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1869 	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1870 	INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
1871 	INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
1872 };
1873 
1874 static const struct dpu_intf_cfg sc7180_intf[] = {
1875 	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1876 	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1877 };
1878 
1879 static const struct dpu_intf_cfg sm8150_intf[] = {
1880 	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1881 	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1882 	INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
1883 	INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
1884 };
1885 
1886 static const struct dpu_intf_cfg sc7280_intf[] = {
1887 	INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1888 	INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1889 	INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
1890 };
1891 
1892 static const struct dpu_intf_cfg sm8350_intf[] = {
1893 	INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1894 	INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1895 	INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
1896 	INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
1897 };
1898 
1899 static const struct dpu_intf_cfg sc8180x_intf[] = {
1900 	INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1901 	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1902 	INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
1903 	/* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */
1904 	INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
1905 	INTF_BLK("intf_4", INTF_4, 0x6C000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
1906 	INTF_BLK("intf_5", INTF_5, 0x6C800, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
1907 };
1908 
1909 /* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
1910 static const struct dpu_intf_cfg sc8280xp_intf[] = {
1911 	INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1912 	INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1913 	INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
1914 	INTF_BLK("intf_3", INTF_3, 0x37000, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
1915 	INTF_BLK("intf_4", INTF_4, 0x38000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 20, 21),
1916 	INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_3, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23),
1917 	INTF_BLK("intf_6", INTF_6, 0x3a000, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 16, 17),
1918 	INTF_BLK("intf_7", INTF_7, 0x3b000, INTF_NONE, MSM_DP_CONTROLLER_2, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 18, 19),
1919 	INTF_BLK("intf_8", INTF_8, 0x3c000, INTF_NONE, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 12, 13),
1920 };
1921 
1922 static const struct dpu_intf_cfg qcm2290_intf[] = {
1923 	INTF_BLK("intf_0", INTF_0, 0x00000, INTF_NONE, 0, 0, 0, 0, 0, 0),
1924 	INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1925 };
1926 
1927 static const struct dpu_intf_cfg sm8450_intf[] = {
1928 	INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1929 	INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1930 	INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
1931 	INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
1932 };
1933 
1934 static const struct dpu_intf_cfg sm8550_intf[] = {
1935 	INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25),
1936 	/* TODO TE sub-blocks for intf1 & intf2 */
1937 	INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27),
1938 	INTF_BLK("intf_2", INTF_2, 0x36000, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29),
1939 	INTF_BLK("intf_3", INTF_3, 0x37000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31),
1940 };
1941 
1942 /*************************************************************
1943  * Writeback blocks config
1944  *************************************************************/
1945 #define WB_BLK(_name, _id, _base, _features, _clk_ctrl, \
1946 		__xin_id, vbif_id, _reg, _max_linewidth, _wb_done_bit) \
1947 	{ \
1948 	.name = _name, .id = _id, \
1949 	.base = _base, .len = 0x2c8, \
1950 	.features = _features, \
1951 	.format_list = wb2_formats, \
1952 	.num_formats = ARRAY_SIZE(wb2_formats), \
1953 	.clk_ctrl = _clk_ctrl, \
1954 	.xin_id = __xin_id, \
1955 	.vbif_idx = vbif_id, \
1956 	.maxlinewidth = _max_linewidth, \
1957 	.intr_wb_done = DPU_IRQ_IDX(_reg, _wb_done_bit) \
1958 	}
1959 
1960 static const struct dpu_wb_cfg sm8250_wb[] = {
1961 	WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6,
1962 			VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4),
1963 };
1964 
1965 /*************************************************************
1966  * VBIF sub blocks config
1967  *************************************************************/
1968 /* VBIF QOS remap */
1969 static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2};
1970 static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1};
1971 static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6};
1972 static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3};
1973 
1974 static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = {
1975 	{
1976 		.pps = 1088 * 1920 * 30,
1977 		.ot_limit = 2,
1978 	},
1979 	{
1980 		.pps = 1088 * 1920 * 60,
1981 		.ot_limit = 6,
1982 	},
1983 	{
1984 		.pps = 3840 * 2160 * 30,
1985 		.ot_limit = 16,
1986 	},
1987 };
1988 
1989 static const struct dpu_vbif_cfg msm8998_vbif[] = {
1990 	{
1991 	.name = "vbif_rt", .id = VBIF_RT,
1992 	.base = 0, .len = 0x1040,
1993 	.default_ot_rd_limit = 32,
1994 	.default_ot_wr_limit = 32,
1995 	.features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM),
1996 	.xin_halt_timeout = 0x4000,
1997 	.qos_rp_remap_size = 0x20,
1998 	.dynamic_ot_rd_tbl = {
1999 		.count = ARRAY_SIZE(msm8998_ot_rdwr_cfg),
2000 		.cfg = msm8998_ot_rdwr_cfg,
2001 		},
2002 	.dynamic_ot_wr_tbl = {
2003 		.count = ARRAY_SIZE(msm8998_ot_rdwr_cfg),
2004 		.cfg = msm8998_ot_rdwr_cfg,
2005 		},
2006 	.qos_rt_tbl = {
2007 		.npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl),
2008 		.priority_lvl = msm8998_rt_pri_lvl,
2009 		},
2010 	.qos_nrt_tbl = {
2011 		.npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl),
2012 		.priority_lvl = msm8998_nrt_pri_lvl,
2013 		},
2014 	.memtype_count = 14,
2015 	.memtype = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2},
2016 	},
2017 };
2018 
2019 static const struct dpu_vbif_cfg sdm845_vbif[] = {
2020 	{
2021 	.name = "vbif_rt", .id = VBIF_RT,
2022 	.base = 0, .len = 0x1040,
2023 	.features = BIT(DPU_VBIF_QOS_REMAP),
2024 	.xin_halt_timeout = 0x4000,
2025 	.qos_rp_remap_size = 0x40,
2026 	.qos_rt_tbl = {
2027 		.npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl),
2028 		.priority_lvl = sdm845_rt_pri_lvl,
2029 		},
2030 	.qos_nrt_tbl = {
2031 		.npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl),
2032 		.priority_lvl = sdm845_nrt_pri_lvl,
2033 		},
2034 	.memtype_count = 14,
2035 	.memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3},
2036 	},
2037 };
2038 
2039 static const struct dpu_reg_dma_cfg sc8280xp_regdma = {
2040 	.base = 0x0,
2041 	.version = 0x00020000,
2042 	.trigger_sel_off = 0x119c,
2043 	.xin_id = 7,
2044 	.clk_ctrl = DPU_CLK_CTRL_REG_DMA,
2045 };
2046 
2047 static const struct dpu_reg_dma_cfg sdm845_regdma = {
2048 	.base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c
2049 };
2050 
2051 static const struct dpu_reg_dma_cfg sm8150_regdma = {
2052 	.base = 0x0, .version = 0x00010001, .trigger_sel_off = 0x119c
2053 };
2054 
2055 static const struct dpu_reg_dma_cfg sm8250_regdma = {
2056 	.base = 0x0,
2057 	.version = 0x00010002,
2058 	.trigger_sel_off = 0x119c,
2059 	.xin_id = 7,
2060 	.clk_ctrl = DPU_CLK_CTRL_REG_DMA,
2061 };
2062 
2063 static const struct dpu_reg_dma_cfg sm8350_regdma = {
2064 	.base = 0x400,
2065 	.version = 0x00020000,
2066 	.trigger_sel_off = 0x119c,
2067 	.xin_id = 7,
2068 	.clk_ctrl = DPU_CLK_CTRL_REG_DMA,
2069 };
2070 
2071 static const struct dpu_reg_dma_cfg sm8450_regdma = {
2072 	.base = 0x0,
2073 	.version = 0x00020000,
2074 	.trigger_sel_off = 0x119c,
2075 	.xin_id = 7,
2076 	.clk_ctrl = DPU_CLK_CTRL_REG_DMA,
2077 };
2078 
2079 /*************************************************************
2080  * PERF data config
2081  *************************************************************/
2082 
2083 /* SSPP QOS LUTs */
2084 static const struct dpu_qos_lut_entry msm8998_qos_linear[] = {
2085 	{.fl = 4,  .lut = 0x1b},
2086 	{.fl = 5,  .lut = 0x5b},
2087 	{.fl = 6,  .lut = 0x15b},
2088 	{.fl = 7,  .lut = 0x55b},
2089 	{.fl = 8,  .lut = 0x155b},
2090 	{.fl = 9,  .lut = 0x555b},
2091 	{.fl = 10, .lut = 0x1555b},
2092 	{.fl = 11, .lut = 0x5555b},
2093 	{.fl = 12, .lut = 0x15555b},
2094 	{.fl = 13, .lut = 0x55555b},
2095 	{.fl = 14, .lut = 0},
2096 	{.fl = 1,  .lut = 0x1b},
2097 	{.fl = 0,  .lut = 0}
2098 };
2099 
2100 static const struct dpu_qos_lut_entry sdm845_qos_linear[] = {
2101 	{.fl = 4, .lut = 0x357},
2102 	{.fl = 5, .lut = 0x3357},
2103 	{.fl = 6, .lut = 0x23357},
2104 	{.fl = 7, .lut = 0x223357},
2105 	{.fl = 8, .lut = 0x2223357},
2106 	{.fl = 9, .lut = 0x22223357},
2107 	{.fl = 10, .lut = 0x222223357},
2108 	{.fl = 11, .lut = 0x2222223357},
2109 	{.fl = 12, .lut = 0x22222223357},
2110 	{.fl = 13, .lut = 0x222222223357},
2111 	{.fl = 14, .lut = 0x1222222223357},
2112 	{.fl = 0, .lut = 0x11222222223357}
2113 };
2114 
2115 static const struct dpu_qos_lut_entry msm8998_qos_macrotile[] = {
2116 	{.fl = 10, .lut = 0x1aaff},
2117 	{.fl = 11, .lut = 0x5aaff},
2118 	{.fl = 12, .lut = 0x15aaff},
2119 	{.fl = 13, .lut = 0x55aaff},
2120 	{.fl = 1,  .lut = 0x1aaff},
2121 	{.fl = 0,  .lut = 0},
2122 };
2123 
2124 static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
2125 	{.fl = 0, .lut = 0x0011222222335777},
2126 };
2127 
2128 static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
2129 	{.fl = 0, .lut = 0x0011222222223357 },
2130 };
2131 
2132 static const struct dpu_qos_lut_entry sc8180x_qos_linear[] = {
2133 	{.fl = 4, .lut = 0x0000000000000357 },
2134 };
2135 
2136 static const struct dpu_qos_lut_entry qcm2290_qos_linear[] = {
2137 	{.fl = 0, .lut = 0x0011222222335777},
2138 };
2139 
2140 static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = {
2141 	{.fl = 10, .lut = 0x344556677},
2142 	{.fl = 11, .lut = 0x3344556677},
2143 	{.fl = 12, .lut = 0x23344556677},
2144 	{.fl = 13, .lut = 0x223344556677},
2145 	{.fl = 14, .lut = 0x1223344556677},
2146 	{.fl = 0, .lut = 0x112233344556677},
2147 };
2148 
2149 static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = {
2150 	{.fl = 0, .lut = 0x0011223344556677},
2151 };
2152 
2153 static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = {
2154 	{.fl = 10, .lut = 0x0000000344556677},
2155 };
2156 
2157 static const struct dpu_qos_lut_entry msm8998_qos_nrt[] = {
2158 	{.fl = 0, .lut = 0x0},
2159 };
2160 
2161 static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = {
2162 	{.fl = 0, .lut = 0x0},
2163 };
2164 
2165 static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
2166 	{.fl = 0, .lut = 0x0},
2167 };
2168 
2169 static const struct dpu_perf_cfg msm8998_perf_data = {
2170 	.max_bw_low = 6700000,
2171 	.max_bw_high = 6700000,
2172 	.min_core_ib = 2400000,
2173 	.min_llcc_ib = 800000,
2174 	.min_dram_ib = 800000,
2175 	.undersized_prefill_lines = 2,
2176 	.xtra_prefill_lines = 2,
2177 	.dest_scale_prefill_lines = 3,
2178 	.macrotile_prefill_lines = 4,
2179 	.yuv_nv12_prefill_lines = 8,
2180 	.linear_prefill_lines = 1,
2181 	.downscaling_prefill_lines = 1,
2182 	.amortizable_threshold = 25,
2183 	.min_prefill_lines = 25,
2184 	.danger_lut_tbl = {0xf, 0xffff, 0x0},
2185 	.safe_lut_tbl = {0xfffc, 0xff00, 0xffff},
2186 	.qos_lut_tbl = {
2187 		{.nentry = ARRAY_SIZE(msm8998_qos_linear),
2188 		.entries = msm8998_qos_linear
2189 		},
2190 		{.nentry = ARRAY_SIZE(msm8998_qos_macrotile),
2191 		.entries = msm8998_qos_macrotile
2192 		},
2193 		{.nentry = ARRAY_SIZE(msm8998_qos_nrt),
2194 		.entries = msm8998_qos_nrt
2195 		},
2196 	},
2197 	.cdp_cfg = {
2198 		{.rd_enable = 1, .wr_enable = 1},
2199 		{.rd_enable = 1, .wr_enable = 0}
2200 	},
2201 	.clk_inefficiency_factor = 200,
2202 	.bw_inefficiency_factor = 120,
2203 };
2204 
2205 static const struct dpu_perf_cfg sdm845_perf_data = {
2206 	.max_bw_low = 6800000,
2207 	.max_bw_high = 6800000,
2208 	.min_core_ib = 2400000,
2209 	.min_llcc_ib = 800000,
2210 	.min_dram_ib = 800000,
2211 	.undersized_prefill_lines = 2,
2212 	.xtra_prefill_lines = 2,
2213 	.dest_scale_prefill_lines = 3,
2214 	.macrotile_prefill_lines = 4,
2215 	.yuv_nv12_prefill_lines = 8,
2216 	.linear_prefill_lines = 1,
2217 	.downscaling_prefill_lines = 1,
2218 	.amortizable_threshold = 25,
2219 	.min_prefill_lines = 24,
2220 	.danger_lut_tbl = {0xf, 0xffff, 0x0},
2221 	.safe_lut_tbl = {0xfff0, 0xf000, 0xffff},
2222 	.qos_lut_tbl = {
2223 		{.nentry = ARRAY_SIZE(sdm845_qos_linear),
2224 		.entries = sdm845_qos_linear
2225 		},
2226 		{.nentry = ARRAY_SIZE(sdm845_qos_macrotile),
2227 		.entries = sdm845_qos_macrotile
2228 		},
2229 		{.nentry = ARRAY_SIZE(sdm845_qos_nrt),
2230 		.entries = sdm845_qos_nrt
2231 		},
2232 	},
2233 	.cdp_cfg = {
2234 		{.rd_enable = 1, .wr_enable = 1},
2235 		{.rd_enable = 1, .wr_enable = 0}
2236 	},
2237 	.clk_inefficiency_factor = 105,
2238 	.bw_inefficiency_factor = 120,
2239 };
2240 
2241 static const struct dpu_perf_cfg sc7180_perf_data = {
2242 	.max_bw_low = 6800000,
2243 	.max_bw_high = 6800000,
2244 	.min_core_ib = 2400000,
2245 	.min_llcc_ib = 800000,
2246 	.min_dram_ib = 1600000,
2247 	.min_prefill_lines = 24,
2248 	.danger_lut_tbl = {0xff, 0xffff, 0x0},
2249 	.safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
2250 	.qos_lut_tbl = {
2251 		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
2252 		.entries = sc7180_qos_linear
2253 		},
2254 		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
2255 		.entries = sc7180_qos_macrotile
2256 		},
2257 		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
2258 		.entries = sc7180_qos_nrt
2259 		},
2260 	},
2261 	.cdp_cfg = {
2262 		{.rd_enable = 1, .wr_enable = 1},
2263 		{.rd_enable = 1, .wr_enable = 0}
2264 	},
2265 	.clk_inefficiency_factor = 105,
2266 	.bw_inefficiency_factor = 120,
2267 };
2268 
2269 static const struct dpu_perf_cfg sm6115_perf_data = {
2270 	.max_bw_low = 3100000,
2271 	.max_bw_high = 4000000,
2272 	.min_core_ib = 2400000,
2273 	.min_llcc_ib = 800000,
2274 	.min_dram_ib = 800000,
2275 	.min_prefill_lines = 24,
2276 	.danger_lut_tbl = {0xff, 0xffff, 0x0},
2277 	.safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
2278 	.qos_lut_tbl = {
2279 		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
2280 		.entries = sc7180_qos_linear
2281 		},
2282 		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
2283 		.entries = sc7180_qos_macrotile
2284 		},
2285 		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
2286 		.entries = sc7180_qos_nrt
2287 		},
2288 		/* TODO: macrotile-qseed is different from macrotile */
2289 	},
2290 	.cdp_cfg = {
2291 		{.rd_enable = 1, .wr_enable = 1},
2292 		{.rd_enable = 1, .wr_enable = 0}
2293 	},
2294 	.clk_inefficiency_factor = 105,
2295 	.bw_inefficiency_factor = 120,
2296 };
2297 
2298 static const struct dpu_perf_cfg sm8150_perf_data = {
2299 	.max_bw_low = 12800000,
2300 	.max_bw_high = 12800000,
2301 	.min_core_ib = 2400000,
2302 	.min_llcc_ib = 800000,
2303 	.min_dram_ib = 800000,
2304 	.min_prefill_lines = 24,
2305 	.danger_lut_tbl = {0xf, 0xffff, 0x0},
2306 	.safe_lut_tbl = {0xfff8, 0xf000, 0xffff},
2307 	.qos_lut_tbl = {
2308 		{.nentry = ARRAY_SIZE(sm8150_qos_linear),
2309 		.entries = sm8150_qos_linear
2310 		},
2311 		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
2312 		.entries = sc7180_qos_macrotile
2313 		},
2314 		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
2315 		.entries = sc7180_qos_nrt
2316 		},
2317 		/* TODO: macrotile-qseed is different from macrotile */
2318 	},
2319 	.cdp_cfg = {
2320 		{.rd_enable = 1, .wr_enable = 1},
2321 		{.rd_enable = 1, .wr_enable = 0}
2322 	},
2323 	.clk_inefficiency_factor = 105,
2324 	.bw_inefficiency_factor = 120,
2325 };
2326 
2327 static const struct dpu_perf_cfg sc8180x_perf_data = {
2328 	.max_bw_low = 9600000,
2329 	.max_bw_high = 9600000,
2330 	.min_core_ib = 2400000,
2331 	.min_llcc_ib = 800000,
2332 	.min_dram_ib = 800000,
2333 	.danger_lut_tbl = {0xf, 0xffff, 0x0},
2334 	.qos_lut_tbl = {
2335 		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
2336 		.entries = sc7180_qos_linear
2337 		},
2338 		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
2339 		.entries = sc7180_qos_macrotile
2340 		},
2341 		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
2342 		.entries = sc7180_qos_nrt
2343 		},
2344 		/* TODO: macrotile-qseed is different from macrotile */
2345 	},
2346 	.cdp_cfg = {
2347 		{.rd_enable = 1, .wr_enable = 1},
2348 		{.rd_enable = 1, .wr_enable = 0}
2349 	},
2350 	.clk_inefficiency_factor = 105,
2351 	.bw_inefficiency_factor = 120,
2352 };
2353 
2354 static const struct dpu_perf_cfg sc8280xp_perf_data = {
2355 	.max_bw_low = 13600000,
2356 	.max_bw_high = 18200000,
2357 	.min_core_ib = 2500000,
2358 	.min_llcc_ib = 0,
2359 	.min_dram_ib = 800000,
2360 	.danger_lut_tbl = {0xf, 0xffff, 0x0},
2361 	.qos_lut_tbl = {
2362 		{.nentry = ARRAY_SIZE(sc8180x_qos_linear),
2363 		.entries = sc8180x_qos_linear
2364 		},
2365 		{.nentry = ARRAY_SIZE(sc8180x_qos_macrotile),
2366 		.entries = sc8180x_qos_macrotile
2367 		},
2368 		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
2369 		.entries = sc7180_qos_nrt
2370 		},
2371 		/* TODO: macrotile-qseed is different from macrotile */
2372 	},
2373 	.cdp_cfg = {
2374 		{.rd_enable = 1, .wr_enable = 1},
2375 		{.rd_enable = 1, .wr_enable = 0}
2376 	},
2377 	.clk_inefficiency_factor = 105,
2378 	.bw_inefficiency_factor = 120,
2379 };
2380 
2381 static const struct dpu_perf_cfg sm8250_perf_data = {
2382 	.max_bw_low = 13700000,
2383 	.max_bw_high = 16600000,
2384 	.min_core_ib = 4800000,
2385 	.min_llcc_ib = 0,
2386 	.min_dram_ib = 800000,
2387 	.min_prefill_lines = 35,
2388 	.danger_lut_tbl = {0xf, 0xffff, 0x0},
2389 	.safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
2390 	.qos_lut_tbl = {
2391 		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
2392 		.entries = sc7180_qos_linear
2393 		},
2394 		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
2395 		.entries = sc7180_qos_macrotile
2396 		},
2397 		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
2398 		.entries = sc7180_qos_nrt
2399 		},
2400 		/* TODO: macrotile-qseed is different from macrotile */
2401 	},
2402 	.cdp_cfg = {
2403 		{.rd_enable = 1, .wr_enable = 1},
2404 		{.rd_enable = 1, .wr_enable = 0}
2405 	},
2406 	.clk_inefficiency_factor = 105,
2407 	.bw_inefficiency_factor = 120,
2408 };
2409 
2410 static const struct dpu_perf_cfg sm8450_perf_data = {
2411 	.max_bw_low = 13600000,
2412 	.max_bw_high = 18200000,
2413 	.min_core_ib = 2500000,
2414 	.min_llcc_ib = 0,
2415 	.min_dram_ib = 800000,
2416 	.min_prefill_lines = 35,
2417 	/* FIXME: lut tables */
2418 	.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
2419 	.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
2420 	.qos_lut_tbl = {
2421 		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
2422 		.entries = sc7180_qos_linear
2423 		},
2424 		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
2425 		.entries = sc7180_qos_macrotile
2426 		},
2427 		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
2428 		.entries = sc7180_qos_nrt
2429 		},
2430 		/* TODO: macrotile-qseed is different from macrotile */
2431 	},
2432 	.cdp_cfg = {
2433 		{.rd_enable = 1, .wr_enable = 1},
2434 		{.rd_enable = 1, .wr_enable = 0}
2435 	},
2436 	.clk_inefficiency_factor = 105,
2437 	.bw_inefficiency_factor = 120,
2438 };
2439 
2440 static const struct dpu_perf_cfg sc7280_perf_data = {
2441 	.max_bw_low = 4700000,
2442 	.max_bw_high = 8800000,
2443 	.min_core_ib = 2500000,
2444 	.min_llcc_ib = 0,
2445 	.min_dram_ib = 1600000,
2446 	.min_prefill_lines = 24,
2447 	.danger_lut_tbl = {0xffff, 0xffff, 0x0},
2448 	.safe_lut_tbl = {0xff00, 0xff00, 0xffff},
2449 	.qos_lut_tbl = {
2450 		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
2451 		.entries = sc7180_qos_macrotile
2452 		},
2453 		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
2454 		.entries = sc7180_qos_macrotile
2455 		},
2456 		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
2457 		.entries = sc7180_qos_nrt
2458 		},
2459 	},
2460 	.cdp_cfg = {
2461 		{.rd_enable = 1, .wr_enable = 1},
2462 		{.rd_enable = 1, .wr_enable = 0}
2463 	},
2464 	.clk_inefficiency_factor = 105,
2465 	.bw_inefficiency_factor = 120,
2466 };
2467 
2468 static const struct dpu_perf_cfg sm8350_perf_data = {
2469 	.max_bw_low = 11800000,
2470 	.max_bw_high = 15500000,
2471 	.min_core_ib = 2500000,
2472 	.min_llcc_ib = 0,
2473 	.min_dram_ib = 800000,
2474 	.min_prefill_lines = 40,
2475 	/* FIXME: lut tables */
2476 	.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
2477 	.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
2478 	.qos_lut_tbl = {
2479 		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
2480 		.entries = sc7180_qos_linear
2481 		},
2482 		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
2483 		.entries = sc7180_qos_macrotile
2484 		},
2485 		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
2486 		.entries = sc7180_qos_nrt
2487 		},
2488 		/* TODO: macrotile-qseed is different from macrotile */
2489 	},
2490 	.cdp_cfg = {
2491 		{.rd_enable = 1, .wr_enable = 1},
2492 		{.rd_enable = 1, .wr_enable = 0}
2493 	},
2494 	.clk_inefficiency_factor = 105,
2495 	.bw_inefficiency_factor = 120,
2496 };
2497 
2498 static const struct dpu_perf_cfg qcm2290_perf_data = {
2499 	.max_bw_low = 2700000,
2500 	.max_bw_high = 2700000,
2501 	.min_core_ib = 1300000,
2502 	.min_llcc_ib = 0,
2503 	.min_dram_ib = 1600000,
2504 	.min_prefill_lines = 24,
2505 	.danger_lut_tbl = {0xff, 0x0, 0x0},
2506 	.safe_lut_tbl = {0xfff0, 0x0, 0x0},
2507 	.qos_lut_tbl = {
2508 		{.nentry = ARRAY_SIZE(qcm2290_qos_linear),
2509 		.entries = qcm2290_qos_linear
2510 		},
2511 	},
2512 	.cdp_cfg = {
2513 		{.rd_enable = 1, .wr_enable = 1},
2514 		{.rd_enable = 1, .wr_enable = 0}
2515 	},
2516 	.clk_inefficiency_factor = 105,
2517 	.bw_inefficiency_factor = 120,
2518 };
2519 /*************************************************************
2520  * Hardware catalog
2521  *************************************************************/
2522 
2523 static const struct dpu_mdss_cfg msm8998_dpu_cfg = {
2524 	.caps = &msm8998_dpu_caps,
2525 	.mdp_count = ARRAY_SIZE(msm8998_mdp),
2526 	.mdp = msm8998_mdp,
2527 	.ctl_count = ARRAY_SIZE(msm8998_ctl),
2528 	.ctl = msm8998_ctl,
2529 	.sspp_count = ARRAY_SIZE(msm8998_sspp),
2530 	.sspp = msm8998_sspp,
2531 	.mixer_count = ARRAY_SIZE(msm8998_lm),
2532 	.mixer = msm8998_lm,
2533 	.dspp_count = ARRAY_SIZE(msm8998_dspp),
2534 	.dspp = msm8998_dspp,
2535 	.pingpong_count = ARRAY_SIZE(sdm845_pp),
2536 	.pingpong = sdm845_pp,
2537 	.intf_count = ARRAY_SIZE(msm8998_intf),
2538 	.intf = msm8998_intf,
2539 	.vbif_count = ARRAY_SIZE(msm8998_vbif),
2540 	.vbif = msm8998_vbif,
2541 	.reg_dma_count = 0,
2542 	.perf = &msm8998_perf_data,
2543 	.mdss_irqs = IRQ_SM8250_MASK,
2544 };
2545 
2546 static const struct dpu_mdss_cfg sdm845_dpu_cfg = {
2547 	.caps = &sdm845_dpu_caps,
2548 	.mdp_count = ARRAY_SIZE(sdm845_mdp),
2549 	.mdp = sdm845_mdp,
2550 	.ctl_count = ARRAY_SIZE(sdm845_ctl),
2551 	.ctl = sdm845_ctl,
2552 	.sspp_count = ARRAY_SIZE(sdm845_sspp),
2553 	.sspp = sdm845_sspp,
2554 	.mixer_count = ARRAY_SIZE(sdm845_lm),
2555 	.mixer = sdm845_lm,
2556 	.pingpong_count = ARRAY_SIZE(sdm845_pp),
2557 	.pingpong = sdm845_pp,
2558 	.dsc_count = ARRAY_SIZE(sdm845_dsc),
2559 	.dsc = sdm845_dsc,
2560 	.intf_count = ARRAY_SIZE(sdm845_intf),
2561 	.intf = sdm845_intf,
2562 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
2563 	.vbif = sdm845_vbif,
2564 	.reg_dma_count = 1,
2565 	.dma_cfg = &sdm845_regdma,
2566 	.perf = &sdm845_perf_data,
2567 	.mdss_irqs = IRQ_SDM845_MASK,
2568 };
2569 
2570 static const struct dpu_mdss_cfg sc7180_dpu_cfg = {
2571 	.caps = &sc7180_dpu_caps,
2572 	.mdp_count = ARRAY_SIZE(sc7180_mdp),
2573 	.mdp = sc7180_mdp,
2574 	.ctl_count = ARRAY_SIZE(sc7180_ctl),
2575 	.ctl = sc7180_ctl,
2576 	.sspp_count = ARRAY_SIZE(sc7180_sspp),
2577 	.sspp = sc7180_sspp,
2578 	.mixer_count = ARRAY_SIZE(sc7180_lm),
2579 	.mixer = sc7180_lm,
2580 	.dspp_count = ARRAY_SIZE(sc7180_dspp),
2581 	.dspp = sc7180_dspp,
2582 	.pingpong_count = ARRAY_SIZE(sc7180_pp),
2583 	.pingpong = sc7180_pp,
2584 	.intf_count = ARRAY_SIZE(sc7180_intf),
2585 	.intf = sc7180_intf,
2586 	.wb_count = ARRAY_SIZE(sm8250_wb),
2587 	.wb = sm8250_wb,
2588 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
2589 	.vbif = sdm845_vbif,
2590 	.reg_dma_count = 1,
2591 	.dma_cfg = &sdm845_regdma,
2592 	.perf = &sc7180_perf_data,
2593 	.mdss_irqs = IRQ_SC7180_MASK,
2594 };
2595 
2596 static const struct dpu_mdss_cfg sm6115_dpu_cfg = {
2597 	.caps = &sm6115_dpu_caps,
2598 	.mdp_count = ARRAY_SIZE(sm6115_mdp),
2599 	.mdp = sm6115_mdp,
2600 	.ctl_count = ARRAY_SIZE(qcm2290_ctl),
2601 	.ctl = qcm2290_ctl,
2602 	.sspp_count = ARRAY_SIZE(sm6115_sspp),
2603 	.sspp = sm6115_sspp,
2604 	.mixer_count = ARRAY_SIZE(qcm2290_lm),
2605 	.mixer = qcm2290_lm,
2606 	.dspp_count = ARRAY_SIZE(qcm2290_dspp),
2607 	.dspp = qcm2290_dspp,
2608 	.pingpong_count = ARRAY_SIZE(qcm2290_pp),
2609 	.pingpong = qcm2290_pp,
2610 	.intf_count = ARRAY_SIZE(qcm2290_intf),
2611 	.intf = qcm2290_intf,
2612 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
2613 	.vbif = sdm845_vbif,
2614 	.perf = &sm6115_perf_data,
2615 	.mdss_irqs = IRQ_SC7180_MASK,
2616 };
2617 
2618 static const struct dpu_mdss_cfg sm8150_dpu_cfg = {
2619 	.caps = &sm8150_dpu_caps,
2620 	.mdp_count = ARRAY_SIZE(sdm845_mdp),
2621 	.mdp = sdm845_mdp,
2622 	.ctl_count = ARRAY_SIZE(sm8150_ctl),
2623 	.ctl = sm8150_ctl,
2624 	.sspp_count = ARRAY_SIZE(sdm845_sspp),
2625 	.sspp = sdm845_sspp,
2626 	.mixer_count = ARRAY_SIZE(sm8150_lm),
2627 	.mixer = sm8150_lm,
2628 	.dspp_count = ARRAY_SIZE(sm8150_dspp),
2629 	.dspp = sm8150_dspp,
2630 	.dsc_count = ARRAY_SIZE(sm8150_dsc),
2631 	.dsc = sm8150_dsc,
2632 	.pingpong_count = ARRAY_SIZE(sm8150_pp),
2633 	.pingpong = sm8150_pp,
2634 	.merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
2635 	.merge_3d = sm8150_merge_3d,
2636 	.intf_count = ARRAY_SIZE(sm8150_intf),
2637 	.intf = sm8150_intf,
2638 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
2639 	.vbif = sdm845_vbif,
2640 	.reg_dma_count = 1,
2641 	.dma_cfg = &sm8150_regdma,
2642 	.perf = &sm8150_perf_data,
2643 	.mdss_irqs = IRQ_SDM845_MASK,
2644 };
2645 
2646 static const struct dpu_mdss_cfg sc8180x_dpu_cfg = {
2647 	.caps = &sc8180x_dpu_caps,
2648 	.mdp_count = ARRAY_SIZE(sc8180x_mdp),
2649 	.mdp = sc8180x_mdp,
2650 	.ctl_count = ARRAY_SIZE(sm8150_ctl),
2651 	.ctl = sm8150_ctl,
2652 	.sspp_count = ARRAY_SIZE(sdm845_sspp),
2653 	.sspp = sdm845_sspp,
2654 	.mixer_count = ARRAY_SIZE(sm8150_lm),
2655 	.mixer = sm8150_lm,
2656 	.pingpong_count = ARRAY_SIZE(sm8150_pp),
2657 	.pingpong = sm8150_pp,
2658 	.merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
2659 	.merge_3d = sm8150_merge_3d,
2660 	.intf_count = ARRAY_SIZE(sc8180x_intf),
2661 	.intf = sc8180x_intf,
2662 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
2663 	.vbif = sdm845_vbif,
2664 	.reg_dma_count = 1,
2665 	.dma_cfg = &sm8150_regdma,
2666 	.perf = &sc8180x_perf_data,
2667 	.mdss_irqs = IRQ_SC8180X_MASK,
2668 };
2669 
2670 static const struct dpu_mdss_cfg sc8280xp_dpu_cfg = {
2671 	.caps = &sc8280xp_dpu_caps,
2672 	.mdp_count = ARRAY_SIZE(sc8280xp_mdp),
2673 	.mdp = sc8280xp_mdp,
2674 	.ctl_count = ARRAY_SIZE(sc8280xp_ctl),
2675 	.ctl = sc8280xp_ctl,
2676 	.sspp_count = ARRAY_SIZE(sc8280xp_sspp),
2677 	.sspp = sc8280xp_sspp,
2678 	.mixer_count = ARRAY_SIZE(sc8280xp_lm),
2679 	.mixer = sc8280xp_lm,
2680 	.dspp_count = ARRAY_SIZE(sm8150_dspp),
2681 	.dspp = sm8150_dspp,
2682 	.pingpong_count = ARRAY_SIZE(sc8280xp_pp),
2683 	.pingpong = sc8280xp_pp,
2684 	.merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),
2685 	.merge_3d = sm8350_merge_3d,
2686 	.intf_count = ARRAY_SIZE(sc8280xp_intf),
2687 	.intf = sc8280xp_intf,
2688 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
2689 	.vbif = sdm845_vbif,
2690 	.reg_dma_count = 1,
2691 	.dma_cfg = &sc8280xp_regdma,
2692 	.perf = &sc8280xp_perf_data,
2693 	.mdss_irqs = IRQ_SC8280XP_MASK,
2694 };
2695 
2696 static const struct dpu_mdss_cfg sm8250_dpu_cfg = {
2697 	.caps = &sm8250_dpu_caps,
2698 	.mdp_count = ARRAY_SIZE(sm8250_mdp),
2699 	.mdp = sm8250_mdp,
2700 	.ctl_count = ARRAY_SIZE(sm8150_ctl),
2701 	.ctl = sm8150_ctl,
2702 	.sspp_count = ARRAY_SIZE(sm8250_sspp),
2703 	.sspp = sm8250_sspp,
2704 	.mixer_count = ARRAY_SIZE(sm8150_lm),
2705 	.mixer = sm8150_lm,
2706 	.dspp_count = ARRAY_SIZE(sm8150_dspp),
2707 	.dspp = sm8150_dspp,
2708 	.dsc_count = ARRAY_SIZE(sm8150_dsc),
2709 	.dsc = sm8150_dsc,
2710 	.pingpong_count = ARRAY_SIZE(sm8150_pp),
2711 	.pingpong = sm8150_pp,
2712 	.merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
2713 	.merge_3d = sm8150_merge_3d,
2714 	.intf_count = ARRAY_SIZE(sm8150_intf),
2715 	.intf = sm8150_intf,
2716 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
2717 	.vbif = sdm845_vbif,
2718 	.wb_count = ARRAY_SIZE(sm8250_wb),
2719 	.wb = sm8250_wb,
2720 	.reg_dma_count = 1,
2721 	.dma_cfg = &sm8250_regdma,
2722 	.perf = &sm8250_perf_data,
2723 	.mdss_irqs = IRQ_SM8250_MASK,
2724 };
2725 
2726 static const struct dpu_mdss_cfg sm8350_dpu_cfg = {
2727 	.caps = &sm8350_dpu_caps,
2728 	.mdp_count = ARRAY_SIZE(sm8350_mdp),
2729 	.mdp = sm8350_mdp,
2730 	.ctl_count = ARRAY_SIZE(sm8350_ctl),
2731 	.ctl = sm8350_ctl,
2732 	.sspp_count = ARRAY_SIZE(sm8250_sspp),
2733 	.sspp = sm8250_sspp,
2734 	.mixer_count = ARRAY_SIZE(sm8150_lm),
2735 	.mixer = sm8150_lm,
2736 	.dspp_count = ARRAY_SIZE(sm8150_dspp),
2737 	.dspp = sm8150_dspp,
2738 	.pingpong_count = ARRAY_SIZE(sm8350_pp),
2739 	.pingpong = sm8350_pp,
2740 	.merge_3d_count = ARRAY_SIZE(sm8350_merge_3d),
2741 	.merge_3d = sm8350_merge_3d,
2742 	.intf_count = ARRAY_SIZE(sm8350_intf),
2743 	.intf = sm8350_intf,
2744 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
2745 	.vbif = sdm845_vbif,
2746 	.reg_dma_count = 1,
2747 	.dma_cfg = &sm8350_regdma,
2748 	.perf = &sm8350_perf_data,
2749 	.mdss_irqs = IRQ_SM8350_MASK,
2750 };
2751 
2752 static const struct dpu_mdss_cfg sm8450_dpu_cfg = {
2753 	.caps = &sm8450_dpu_caps,
2754 	.mdp_count = ARRAY_SIZE(sm8450_mdp),
2755 	.mdp = sm8450_mdp,
2756 	.ctl_count = ARRAY_SIZE(sm8450_ctl),
2757 	.ctl = sm8450_ctl,
2758 	.sspp_count = ARRAY_SIZE(sm8450_sspp),
2759 	.sspp = sm8450_sspp,
2760 	.mixer_count = ARRAY_SIZE(sm8150_lm),
2761 	.mixer = sm8150_lm,
2762 	.dspp_count = ARRAY_SIZE(sm8150_dspp),
2763 	.dspp = sm8150_dspp,
2764 	.pingpong_count = ARRAY_SIZE(sm8450_pp),
2765 	.pingpong = sm8450_pp,
2766 	.merge_3d_count = ARRAY_SIZE(sm8450_merge_3d),
2767 	.merge_3d = sm8450_merge_3d,
2768 	.intf_count = ARRAY_SIZE(sm8450_intf),
2769 	.intf = sm8450_intf,
2770 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
2771 	.vbif = sdm845_vbif,
2772 	.reg_dma_count = 1,
2773 	.dma_cfg = &sm8450_regdma,
2774 	.perf = &sm8450_perf_data,
2775 	.mdss_irqs = IRQ_SM8450_MASK,
2776 };
2777 
2778 static const struct dpu_mdss_cfg sm8550_dpu_cfg = {
2779 	.caps = &sm8550_dpu_caps,
2780 	.mdp_count = ARRAY_SIZE(sm8550_mdp),
2781 	.mdp = sm8550_mdp,
2782 	.ctl_count = ARRAY_SIZE(sm8550_ctl),
2783 	.ctl = sm8550_ctl,
2784 	.sspp_count = ARRAY_SIZE(sm8550_sspp),
2785 	.sspp = sm8550_sspp,
2786 	.mixer_count = ARRAY_SIZE(sm8150_lm),
2787 	.mixer = sm8150_lm,
2788 	.dspp_count = ARRAY_SIZE(sm8150_dspp),
2789 	.dspp = sm8150_dspp,
2790 	.pingpong_count = ARRAY_SIZE(sm8550_pp),
2791 	.pingpong = sm8550_pp,
2792 	.merge_3d_count = ARRAY_SIZE(sm8550_merge_3d),
2793 	.merge_3d = sm8550_merge_3d,
2794 	.intf_count = ARRAY_SIZE(sm8550_intf),
2795 	.intf = sm8550_intf,
2796 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
2797 	.vbif = sdm845_vbif,
2798 	.reg_dma_count = 1,
2799 	.dma_cfg = &sm8450_regdma,
2800 	.perf = &sm8450_perf_data,
2801 	.mdss_irqs = IRQ_SM8450_MASK,
2802 };
2803 
2804 static const struct dpu_mdss_cfg sc7280_dpu_cfg = {
2805 	.caps = &sc7280_dpu_caps,
2806 	.mdp_count = ARRAY_SIZE(sc7280_mdp),
2807 	.mdp = sc7280_mdp,
2808 	.ctl_count = ARRAY_SIZE(sc7280_ctl),
2809 	.ctl = sc7280_ctl,
2810 	.sspp_count = ARRAY_SIZE(sc7280_sspp),
2811 	.sspp = sc7280_sspp,
2812 	.dspp_count = ARRAY_SIZE(sc7180_dspp),
2813 	.dspp = sc7180_dspp,
2814 	.mixer_count = ARRAY_SIZE(sc7280_lm),
2815 	.mixer = sc7280_lm,
2816 	.pingpong_count = ARRAY_SIZE(sc7280_pp),
2817 	.pingpong = sc7280_pp,
2818 	.intf_count = ARRAY_SIZE(sc7280_intf),
2819 	.intf = sc7280_intf,
2820 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
2821 	.vbif = sdm845_vbif,
2822 	.perf = &sc7280_perf_data,
2823 	.mdss_irqs = IRQ_SC7280_MASK,
2824 };
2825 
2826 static const struct dpu_mdss_cfg qcm2290_dpu_cfg = {
2827 	.caps = &qcm2290_dpu_caps,
2828 	.mdp_count = ARRAY_SIZE(qcm2290_mdp),
2829 	.mdp = qcm2290_mdp,
2830 	.ctl_count = ARRAY_SIZE(qcm2290_ctl),
2831 	.ctl = qcm2290_ctl,
2832 	.sspp_count = ARRAY_SIZE(qcm2290_sspp),
2833 	.sspp = qcm2290_sspp,
2834 	.mixer_count = ARRAY_SIZE(qcm2290_lm),
2835 	.mixer = qcm2290_lm,
2836 	.dspp_count = ARRAY_SIZE(qcm2290_dspp),
2837 	.dspp = qcm2290_dspp,
2838 	.pingpong_count = ARRAY_SIZE(qcm2290_pp),
2839 	.pingpong = qcm2290_pp,
2840 	.intf_count = ARRAY_SIZE(qcm2290_intf),
2841 	.intf = qcm2290_intf,
2842 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
2843 	.vbif = sdm845_vbif,
2844 	.reg_dma_count = 1,
2845 	.dma_cfg = &sdm845_regdma,
2846 	.perf = &qcm2290_perf_data,
2847 	.mdss_irqs = IRQ_SC7180_MASK,
2848 };
2849 
2850 static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = {
2851 	{ .hw_rev = DPU_HW_VER_300, .dpu_cfg = &msm8998_dpu_cfg},
2852 	{ .hw_rev = DPU_HW_VER_301, .dpu_cfg = &msm8998_dpu_cfg},
2853 	{ .hw_rev = DPU_HW_VER_400, .dpu_cfg = &sdm845_dpu_cfg},
2854 	{ .hw_rev = DPU_HW_VER_401, .dpu_cfg = &sdm845_dpu_cfg},
2855 	{ .hw_rev = DPU_HW_VER_500, .dpu_cfg = &sm8150_dpu_cfg},
2856 	{ .hw_rev = DPU_HW_VER_501, .dpu_cfg = &sm8150_dpu_cfg},
2857 	{ .hw_rev = DPU_HW_VER_510, .dpu_cfg = &sc8180x_dpu_cfg},
2858 	{ .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg},
2859 	{ .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg},
2860 	{ .hw_rev = DPU_HW_VER_630, .dpu_cfg = &sm6115_dpu_cfg},
2861 	{ .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg},
2862 	{ .hw_rev = DPU_HW_VER_700, .dpu_cfg = &sm8350_dpu_cfg},
2863 	{ .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg},
2864 	{ .hw_rev = DPU_HW_VER_800, .dpu_cfg = &sc8280xp_dpu_cfg},
2865 	{ .hw_rev = DPU_HW_VER_810, .dpu_cfg = &sm8450_dpu_cfg},
2866 	{ .hw_rev = DPU_HW_VER_900, .dpu_cfg = &sm8550_dpu_cfg},
2867 };
2868 
2869 const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev)
2870 {
2871 	int i;
2872 
2873 	for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) {
2874 		if (cfg_handler[i].hw_rev == hw_rev)
2875 			return cfg_handler[i].dpu_cfg;
2876 	}
2877 
2878 	DPU_ERROR("unsupported chipset id:%X\n", hw_rev);
2879 
2880 	return ERR_PTR(-ENODEV);
2881 }
2882 
2883