1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 7 #include <linux/slab.h> 8 #include <linux/of_address.h> 9 #include <linux/platform_device.h> 10 #include "dpu_hw_mdss.h" 11 #include "dpu_hw_interrupts.h" 12 #include "dpu_hw_catalog.h" 13 #include "dpu_kms.h" 14 15 #define VIG_MASK \ 16 (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\ 17 BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) |\ 18 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) 19 20 #define VIG_MSM8998_MASK \ 21 (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3)) 22 23 #define VIG_SDM845_MASK \ 24 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3)) 25 26 #define VIG_SC7180_MASK \ 27 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4)) 28 29 #define VIG_SM8250_MASK \ 30 (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE)) 31 32 #define VIG_QCM2290_MASK (VIG_MASK | BIT(DPU_SSPP_QOS_8LVL)) 33 34 #define DMA_MSM8998_MASK \ 35 (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\ 36 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 37 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 38 39 #define VIG_SC7280_MASK \ 40 (VIG_SC7180_MASK | BIT(DPU_SSPP_INLINE_ROTATION)) 41 42 #define DMA_SDM845_MASK \ 43 (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ 44 BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 45 BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 46 47 #define DMA_CURSOR_SDM845_MASK \ 48 (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR)) 49 50 #define DMA_CURSOR_MSM8998_MASK \ 51 (DMA_MSM8998_MASK | BIT(DPU_SSPP_CURSOR)) 52 53 #define MIXER_MSM8998_MASK \ 54 (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER)) 55 56 #define MIXER_SDM845_MASK \ 57 (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) 58 59 #define MIXER_SC7180_MASK \ 60 (BIT(DPU_DIM_LAYER) | BIT(DPU_MIXER_COMBINED_ALPHA)) 61 62 #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER) 63 64 #define PINGPONG_SDM845_SPLIT_MASK \ 65 (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) 66 67 #define CTL_SC7280_MASK \ 68 (BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_FETCH_ACTIVE) | BIT(DPU_CTL_VM_CFG)) 69 70 #define MERGE_3D_SM8150_MASK (0) 71 72 #define DSPP_MSM8998_MASK BIT(DPU_DSPP_PCC) | BIT(DPU_DSPP_GC) 73 74 #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) 75 76 #define INTF_SDM845_MASK (0) 77 78 #define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) 79 80 #define INTF_SC7280_MASK INTF_SC7180_MASK | BIT(DPU_DATA_HCTL_EN) 81 82 #define IRQ_SDM845_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ 83 BIT(MDP_SSPP_TOP0_INTR2) | \ 84 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 85 BIT(MDP_INTF0_INTR) | \ 86 BIT(MDP_INTF1_INTR) | \ 87 BIT(MDP_INTF2_INTR) | \ 88 BIT(MDP_INTF3_INTR) | \ 89 BIT(MDP_INTF4_INTR) | \ 90 BIT(MDP_AD4_0_INTR) | \ 91 BIT(MDP_AD4_1_INTR)) 92 93 #define IRQ_SC7180_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ 94 BIT(MDP_SSPP_TOP0_INTR2) | \ 95 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 96 BIT(MDP_INTF0_INTR) | \ 97 BIT(MDP_INTF1_INTR)) 98 99 #define IRQ_SC7280_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ 100 BIT(MDP_SSPP_TOP0_INTR2) | \ 101 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 102 BIT(MDP_INTF0_7xxx_INTR) | \ 103 BIT(MDP_INTF1_7xxx_INTR) | \ 104 BIT(MDP_INTF5_7xxx_INTR)) 105 106 #define IRQ_SM8250_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ 107 BIT(MDP_SSPP_TOP0_INTR2) | \ 108 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 109 BIT(MDP_INTF0_INTR) | \ 110 BIT(MDP_INTF1_INTR) | \ 111 BIT(MDP_INTF2_INTR) | \ 112 BIT(MDP_INTF3_INTR) | \ 113 BIT(MDP_INTF4_INTR)) 114 115 #define IRQ_SC8180X_MASK (BIT(MDP_SSPP_TOP0_INTR) | \ 116 BIT(MDP_SSPP_TOP0_INTR2) | \ 117 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 118 BIT(MDP_INTF0_INTR) | \ 119 BIT(MDP_INTF1_INTR) | \ 120 BIT(MDP_INTF2_INTR) | \ 121 BIT(MDP_INTF3_INTR) | \ 122 BIT(MDP_INTF4_INTR) | \ 123 BIT(MDP_INTF5_INTR) | \ 124 BIT(MDP_AD4_0_INTR) | \ 125 BIT(MDP_AD4_1_INTR)) 126 127 #define WB_SM8250_MASK (BIT(DPU_WB_LINE_MODE) | \ 128 BIT(DPU_WB_UBWC) | \ 129 BIT(DPU_WB_YUV_CONFIG) | \ 130 BIT(DPU_WB_PIPE_ALPHA) | \ 131 BIT(DPU_WB_XY_ROI_OFFSET) | \ 132 BIT(DPU_WB_QOS) | \ 133 BIT(DPU_WB_QOS_8LVL) | \ 134 BIT(DPU_WB_CDP) | \ 135 BIT(DPU_WB_INPUT_CTRL)) 136 137 #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024) 138 #define DEFAULT_DPU_LINE_WIDTH 2048 139 #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560 140 141 #define MAX_HORZ_DECIMATION 4 142 #define MAX_VERT_DECIMATION 4 143 144 #define MAX_UPSCALE_RATIO 20 145 #define MAX_DOWNSCALE_RATIO 4 146 #define SSPP_UNITY_SCALE 1 147 148 #define STRCAT(X, Y) (X Y) 149 150 static const uint32_t plane_formats[] = { 151 DRM_FORMAT_ARGB8888, 152 DRM_FORMAT_ABGR8888, 153 DRM_FORMAT_RGBA8888, 154 DRM_FORMAT_BGRA8888, 155 DRM_FORMAT_XRGB8888, 156 DRM_FORMAT_RGBX8888, 157 DRM_FORMAT_BGRX8888, 158 DRM_FORMAT_XBGR8888, 159 DRM_FORMAT_XRGB2101010, 160 DRM_FORMAT_RGB888, 161 DRM_FORMAT_BGR888, 162 DRM_FORMAT_RGB565, 163 DRM_FORMAT_BGR565, 164 DRM_FORMAT_ARGB1555, 165 DRM_FORMAT_ABGR1555, 166 DRM_FORMAT_RGBA5551, 167 DRM_FORMAT_BGRA5551, 168 DRM_FORMAT_XRGB1555, 169 DRM_FORMAT_XBGR1555, 170 DRM_FORMAT_RGBX5551, 171 DRM_FORMAT_BGRX5551, 172 DRM_FORMAT_ARGB4444, 173 DRM_FORMAT_ABGR4444, 174 DRM_FORMAT_RGBA4444, 175 DRM_FORMAT_BGRA4444, 176 DRM_FORMAT_XRGB4444, 177 DRM_FORMAT_XBGR4444, 178 DRM_FORMAT_RGBX4444, 179 DRM_FORMAT_BGRX4444, 180 }; 181 182 static const uint32_t plane_formats_yuv[] = { 183 DRM_FORMAT_ARGB8888, 184 DRM_FORMAT_ABGR8888, 185 DRM_FORMAT_RGBA8888, 186 DRM_FORMAT_BGRX8888, 187 DRM_FORMAT_BGRA8888, 188 DRM_FORMAT_XRGB2101010, 189 DRM_FORMAT_XRGB8888, 190 DRM_FORMAT_XBGR8888, 191 DRM_FORMAT_RGBX8888, 192 DRM_FORMAT_RGB888, 193 DRM_FORMAT_BGR888, 194 DRM_FORMAT_RGB565, 195 DRM_FORMAT_BGR565, 196 DRM_FORMAT_ARGB1555, 197 DRM_FORMAT_ABGR1555, 198 DRM_FORMAT_RGBA5551, 199 DRM_FORMAT_BGRA5551, 200 DRM_FORMAT_XRGB1555, 201 DRM_FORMAT_XBGR1555, 202 DRM_FORMAT_RGBX5551, 203 DRM_FORMAT_BGRX5551, 204 DRM_FORMAT_ARGB4444, 205 DRM_FORMAT_ABGR4444, 206 DRM_FORMAT_RGBA4444, 207 DRM_FORMAT_BGRA4444, 208 DRM_FORMAT_XRGB4444, 209 DRM_FORMAT_XBGR4444, 210 DRM_FORMAT_RGBX4444, 211 DRM_FORMAT_BGRX4444, 212 213 DRM_FORMAT_P010, 214 DRM_FORMAT_NV12, 215 DRM_FORMAT_NV21, 216 DRM_FORMAT_NV16, 217 DRM_FORMAT_NV61, 218 DRM_FORMAT_VYUY, 219 DRM_FORMAT_UYVY, 220 DRM_FORMAT_YUYV, 221 DRM_FORMAT_YVYU, 222 DRM_FORMAT_YUV420, 223 DRM_FORMAT_YVU420, 224 }; 225 226 static const u32 rotation_v2_formats[] = { 227 DRM_FORMAT_NV12, 228 /* TODO add formats after validation */ 229 }; 230 231 static const uint32_t wb2_formats[] = { 232 DRM_FORMAT_RGB565, 233 DRM_FORMAT_BGR565, 234 DRM_FORMAT_RGB888, 235 DRM_FORMAT_ARGB8888, 236 DRM_FORMAT_RGBA8888, 237 DRM_FORMAT_ABGR8888, 238 DRM_FORMAT_XRGB8888, 239 DRM_FORMAT_RGBX8888, 240 DRM_FORMAT_XBGR8888, 241 DRM_FORMAT_ARGB1555, 242 DRM_FORMAT_RGBA5551, 243 DRM_FORMAT_XRGB1555, 244 DRM_FORMAT_RGBX5551, 245 DRM_FORMAT_ARGB4444, 246 DRM_FORMAT_RGBA4444, 247 DRM_FORMAT_RGBX4444, 248 DRM_FORMAT_XRGB4444, 249 DRM_FORMAT_BGR565, 250 DRM_FORMAT_BGR888, 251 DRM_FORMAT_ABGR8888, 252 DRM_FORMAT_BGRA8888, 253 DRM_FORMAT_BGRX8888, 254 DRM_FORMAT_XBGR8888, 255 DRM_FORMAT_ABGR1555, 256 DRM_FORMAT_BGRA5551, 257 DRM_FORMAT_XBGR1555, 258 DRM_FORMAT_BGRX5551, 259 DRM_FORMAT_ABGR4444, 260 DRM_FORMAT_BGRA4444, 261 DRM_FORMAT_BGRX4444, 262 DRM_FORMAT_XBGR4444, 263 }; 264 265 /************************************************************* 266 * DPU sub blocks config 267 *************************************************************/ 268 /* DPU top level caps */ 269 static const struct dpu_caps msm8998_dpu_caps = { 270 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 271 .max_mixer_blendstages = 0x7, 272 .qseed_type = DPU_SSPP_SCALER_QSEED3, 273 .smart_dma_rev = DPU_SSPP_SMART_DMA_V1, 274 .ubwc_version = DPU_HW_UBWC_VER_10, 275 .has_src_split = true, 276 .has_dim_layer = true, 277 .has_idle_pc = true, 278 .has_3d_merge = true, 279 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 280 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 281 .max_hdeci_exp = MAX_HORZ_DECIMATION, 282 .max_vdeci_exp = MAX_VERT_DECIMATION, 283 }; 284 285 static const struct dpu_caps qcm2290_dpu_caps = { 286 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 287 .max_mixer_blendstages = 0x4, 288 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, 289 .ubwc_version = DPU_HW_UBWC_VER_20, 290 .has_dim_layer = true, 291 .has_idle_pc = true, 292 .max_linewidth = 2160, 293 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 294 }; 295 296 static const struct dpu_caps sdm845_dpu_caps = { 297 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 298 .max_mixer_blendstages = 0xb, 299 .qseed_type = DPU_SSPP_SCALER_QSEED3, 300 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, 301 .ubwc_version = DPU_HW_UBWC_VER_20, 302 .has_src_split = true, 303 .has_dim_layer = true, 304 .has_idle_pc = true, 305 .has_3d_merge = true, 306 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 307 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 308 .max_hdeci_exp = MAX_HORZ_DECIMATION, 309 .max_vdeci_exp = MAX_VERT_DECIMATION, 310 }; 311 312 static const struct dpu_caps sc7180_dpu_caps = { 313 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 314 .max_mixer_blendstages = 0x9, 315 .qseed_type = DPU_SSPP_SCALER_QSEED4, 316 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, 317 .ubwc_version = DPU_HW_UBWC_VER_20, 318 .has_dim_layer = true, 319 .has_idle_pc = true, 320 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 321 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 322 }; 323 324 static const struct dpu_caps sm6115_dpu_caps = { 325 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 326 .max_mixer_blendstages = 0x4, 327 .qseed_type = DPU_SSPP_SCALER_QSEED3LITE, 328 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ 329 .ubwc_version = DPU_HW_UBWC_VER_20, 330 .has_dim_layer = true, 331 .has_idle_pc = true, 332 .max_linewidth = 2160, 333 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 334 }; 335 336 static const struct dpu_caps sm8150_dpu_caps = { 337 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 338 .max_mixer_blendstages = 0xb, 339 .qseed_type = DPU_SSPP_SCALER_QSEED3, 340 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ 341 .ubwc_version = DPU_HW_UBWC_VER_30, 342 .has_src_split = true, 343 .has_dim_layer = true, 344 .has_idle_pc = true, 345 .has_3d_merge = true, 346 .max_linewidth = 4096, 347 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 348 .max_hdeci_exp = MAX_HORZ_DECIMATION, 349 .max_vdeci_exp = MAX_VERT_DECIMATION, 350 }; 351 352 static const struct dpu_caps sc8180x_dpu_caps = { 353 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 354 .max_mixer_blendstages = 0xb, 355 .qseed_type = DPU_SSPP_SCALER_QSEED3, 356 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ 357 .ubwc_version = DPU_HW_UBWC_VER_30, 358 .has_src_split = true, 359 .has_dim_layer = true, 360 .has_idle_pc = true, 361 .has_3d_merge = true, 362 .max_linewidth = 4096, 363 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 364 .max_hdeci_exp = MAX_HORZ_DECIMATION, 365 .max_vdeci_exp = MAX_VERT_DECIMATION, 366 }; 367 368 static const struct dpu_caps sm8250_dpu_caps = { 369 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 370 .max_mixer_blendstages = 0xb, 371 .qseed_type = DPU_SSPP_SCALER_QSEED3LITE, 372 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ 373 .ubwc_version = DPU_HW_UBWC_VER_40, 374 .has_src_split = true, 375 .has_dim_layer = true, 376 .has_idle_pc = true, 377 .has_3d_merge = true, 378 .max_linewidth = 4096, 379 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 380 }; 381 382 static const struct dpu_caps sc7280_dpu_caps = { 383 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 384 .max_mixer_blendstages = 0x7, 385 .qseed_type = DPU_SSPP_SCALER_QSEED4, 386 .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, 387 .ubwc_version = DPU_HW_UBWC_VER_30, 388 .has_dim_layer = true, 389 .has_idle_pc = true, 390 .max_linewidth = 2400, 391 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 392 }; 393 394 static const struct dpu_mdp_cfg msm8998_mdp[] = { 395 { 396 .name = "top_0", .id = MDP_TOP, 397 .base = 0x0, .len = 0x458, 398 .features = 0, 399 .highest_bank_bit = 0x2, 400 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 401 .reg_off = 0x2AC, .bit_off = 0}, 402 .clk_ctrls[DPU_CLK_CTRL_VIG1] = { 403 .reg_off = 0x2B4, .bit_off = 0}, 404 .clk_ctrls[DPU_CLK_CTRL_VIG2] = { 405 .reg_off = 0x2BC, .bit_off = 0}, 406 .clk_ctrls[DPU_CLK_CTRL_VIG3] = { 407 .reg_off = 0x2C4, .bit_off = 0}, 408 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 409 .reg_off = 0x2AC, .bit_off = 8}, 410 .clk_ctrls[DPU_CLK_CTRL_DMA1] = { 411 .reg_off = 0x2B4, .bit_off = 8}, 412 .clk_ctrls[DPU_CLK_CTRL_DMA2] = { 413 .reg_off = 0x2C4, .bit_off = 8}, 414 .clk_ctrls[DPU_CLK_CTRL_DMA3] = { 415 .reg_off = 0x2C4, .bit_off = 12}, 416 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { 417 .reg_off = 0x3A8, .bit_off = 15}, 418 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { 419 .reg_off = 0x3B0, .bit_off = 15}, 420 }, 421 }; 422 423 static const struct dpu_mdp_cfg sdm845_mdp[] = { 424 { 425 .name = "top_0", .id = MDP_TOP, 426 .base = 0x0, .len = 0x45C, 427 .features = BIT(DPU_MDP_AUDIO_SELECT), 428 .highest_bank_bit = 0x2, 429 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 430 .reg_off = 0x2AC, .bit_off = 0}, 431 .clk_ctrls[DPU_CLK_CTRL_VIG1] = { 432 .reg_off = 0x2B4, .bit_off = 0}, 433 .clk_ctrls[DPU_CLK_CTRL_VIG2] = { 434 .reg_off = 0x2BC, .bit_off = 0}, 435 .clk_ctrls[DPU_CLK_CTRL_VIG3] = { 436 .reg_off = 0x2C4, .bit_off = 0}, 437 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 438 .reg_off = 0x2AC, .bit_off = 8}, 439 .clk_ctrls[DPU_CLK_CTRL_DMA1] = { 440 .reg_off = 0x2B4, .bit_off = 8}, 441 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { 442 .reg_off = 0x2BC, .bit_off = 8}, 443 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { 444 .reg_off = 0x2C4, .bit_off = 8}, 445 }, 446 }; 447 448 static const struct dpu_mdp_cfg sc7180_mdp[] = { 449 { 450 .name = "top_0", .id = MDP_TOP, 451 .base = 0x0, .len = 0x494, 452 .features = 0, 453 .highest_bank_bit = 0x3, 454 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 455 .reg_off = 0x2AC, .bit_off = 0}, 456 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 457 .reg_off = 0x2AC, .bit_off = 8}, 458 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { 459 .reg_off = 0x2B4, .bit_off = 8}, 460 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { 461 .reg_off = 0x2C4, .bit_off = 8}, 462 }, 463 }; 464 465 static const struct dpu_mdp_cfg sc8180x_mdp[] = { 466 { 467 .name = "top_0", .id = MDP_TOP, 468 .base = 0x0, .len = 0x45C, 469 .features = 0, 470 .highest_bank_bit = 0x3, 471 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 472 .reg_off = 0x2AC, .bit_off = 0}, 473 .clk_ctrls[DPU_CLK_CTRL_VIG1] = { 474 .reg_off = 0x2B4, .bit_off = 0}, 475 .clk_ctrls[DPU_CLK_CTRL_VIG2] = { 476 .reg_off = 0x2BC, .bit_off = 0}, 477 .clk_ctrls[DPU_CLK_CTRL_VIG3] = { 478 .reg_off = 0x2C4, .bit_off = 0}, 479 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 480 .reg_off = 0x2AC, .bit_off = 8}, 481 .clk_ctrls[DPU_CLK_CTRL_DMA1] = { 482 .reg_off = 0x2B4, .bit_off = 8}, 483 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { 484 .reg_off = 0x2BC, .bit_off = 8}, 485 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { 486 .reg_off = 0x2C4, .bit_off = 8}, 487 }, 488 }; 489 490 static const struct dpu_mdp_cfg sm6115_mdp[] = { 491 { 492 .name = "top_0", .id = MDP_TOP, 493 .base = 0x0, .len = 0x494, 494 .features = 0, 495 .highest_bank_bit = 0x1, 496 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 497 .reg_off = 0x2ac, .bit_off = 0}, 498 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 499 .reg_off = 0x2ac, .bit_off = 8}, 500 }, 501 }; 502 503 static const struct dpu_mdp_cfg sm8250_mdp[] = { 504 { 505 .name = "top_0", .id = MDP_TOP, 506 .base = 0x0, .len = 0x494, 507 .features = 0, 508 .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ 509 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 510 .reg_off = 0x2AC, .bit_off = 0}, 511 .clk_ctrls[DPU_CLK_CTRL_VIG1] = { 512 .reg_off = 0x2B4, .bit_off = 0}, 513 .clk_ctrls[DPU_CLK_CTRL_VIG2] = { 514 .reg_off = 0x2BC, .bit_off = 0}, 515 .clk_ctrls[DPU_CLK_CTRL_VIG3] = { 516 .reg_off = 0x2C4, .bit_off = 0}, 517 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 518 .reg_off = 0x2AC, .bit_off = 8}, 519 .clk_ctrls[DPU_CLK_CTRL_DMA1] = { 520 .reg_off = 0x2B4, .bit_off = 8}, 521 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { 522 .reg_off = 0x2BC, .bit_off = 8}, 523 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { 524 .reg_off = 0x2C4, .bit_off = 8}, 525 .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { 526 .reg_off = 0x2BC, .bit_off = 20}, 527 .clk_ctrls[DPU_CLK_CTRL_WB2] = { 528 .reg_off = 0x3B8, .bit_off = 24}, 529 }, 530 }; 531 532 static const struct dpu_mdp_cfg sc7280_mdp[] = { 533 { 534 .name = "top_0", .id = MDP_TOP, 535 .base = 0x0, .len = 0x2014, 536 .highest_bank_bit = 0x1, 537 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 538 .reg_off = 0x2AC, .bit_off = 0}, 539 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 540 .reg_off = 0x2AC, .bit_off = 8}, 541 .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { 542 .reg_off = 0x2B4, .bit_off = 8}, 543 .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { 544 .reg_off = 0x2C4, .bit_off = 8}, 545 }, 546 }; 547 548 static const struct dpu_mdp_cfg qcm2290_mdp[] = { 549 { 550 .name = "top_0", .id = MDP_TOP, 551 .base = 0x0, .len = 0x494, 552 .features = 0, 553 .highest_bank_bit = 0x2, 554 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 555 .reg_off = 0x2AC, .bit_off = 0}, 556 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 557 .reg_off = 0x2AC, .bit_off = 8}, 558 }, 559 }; 560 561 /************************************************************* 562 * CTL sub blocks config 563 *************************************************************/ 564 static const struct dpu_ctl_cfg msm8998_ctl[] = { 565 { 566 .name = "ctl_0", .id = CTL_0, 567 .base = 0x1000, .len = 0x94, 568 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 569 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 570 }, 571 { 572 .name = "ctl_1", .id = CTL_1, 573 .base = 0x1200, .len = 0x94, 574 .features = 0, 575 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 576 }, 577 { 578 .name = "ctl_2", .id = CTL_2, 579 .base = 0x1400, .len = 0x94, 580 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 581 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 582 }, 583 { 584 .name = "ctl_3", .id = CTL_3, 585 .base = 0x1600, .len = 0x94, 586 .features = 0, 587 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 588 }, 589 { 590 .name = "ctl_4", .id = CTL_4, 591 .base = 0x1800, .len = 0x94, 592 .features = 0, 593 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 594 }, 595 }; 596 597 static const struct dpu_ctl_cfg sdm845_ctl[] = { 598 { 599 .name = "ctl_0", .id = CTL_0, 600 .base = 0x1000, .len = 0xE4, 601 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 602 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 603 }, 604 { 605 .name = "ctl_1", .id = CTL_1, 606 .base = 0x1200, .len = 0xE4, 607 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 608 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 609 }, 610 { 611 .name = "ctl_2", .id = CTL_2, 612 .base = 0x1400, .len = 0xE4, 613 .features = 0, 614 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 615 }, 616 { 617 .name = "ctl_3", .id = CTL_3, 618 .base = 0x1600, .len = 0xE4, 619 .features = 0, 620 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 621 }, 622 { 623 .name = "ctl_4", .id = CTL_4, 624 .base = 0x1800, .len = 0xE4, 625 .features = 0, 626 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 627 }, 628 }; 629 630 static const struct dpu_ctl_cfg sc7180_ctl[] = { 631 { 632 .name = "ctl_0", .id = CTL_0, 633 .base = 0x1000, .len = 0xE4, 634 .features = BIT(DPU_CTL_ACTIVE_CFG), 635 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 636 }, 637 { 638 .name = "ctl_1", .id = CTL_1, 639 .base = 0x1200, .len = 0xE4, 640 .features = BIT(DPU_CTL_ACTIVE_CFG), 641 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 642 }, 643 { 644 .name = "ctl_2", .id = CTL_2, 645 .base = 0x1400, .len = 0xE4, 646 .features = BIT(DPU_CTL_ACTIVE_CFG), 647 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 648 }, 649 }; 650 651 static const struct dpu_ctl_cfg sm8150_ctl[] = { 652 { 653 .name = "ctl_0", .id = CTL_0, 654 .base = 0x1000, .len = 0x1e0, 655 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 656 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 657 }, 658 { 659 .name = "ctl_1", .id = CTL_1, 660 .base = 0x1200, .len = 0x1e0, 661 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 662 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 663 }, 664 { 665 .name = "ctl_2", .id = CTL_2, 666 .base = 0x1400, .len = 0x1e0, 667 .features = BIT(DPU_CTL_ACTIVE_CFG), 668 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 669 }, 670 { 671 .name = "ctl_3", .id = CTL_3, 672 .base = 0x1600, .len = 0x1e0, 673 .features = BIT(DPU_CTL_ACTIVE_CFG), 674 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 675 }, 676 { 677 .name = "ctl_4", .id = CTL_4, 678 .base = 0x1800, .len = 0x1e0, 679 .features = BIT(DPU_CTL_ACTIVE_CFG), 680 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 681 }, 682 { 683 .name = "ctl_5", .id = CTL_5, 684 .base = 0x1a00, .len = 0x1e0, 685 .features = BIT(DPU_CTL_ACTIVE_CFG), 686 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 687 }, 688 }; 689 690 static const struct dpu_ctl_cfg sc7280_ctl[] = { 691 { 692 .name = "ctl_0", .id = CTL_0, 693 .base = 0x15000, .len = 0x1E8, 694 .features = CTL_SC7280_MASK, 695 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 696 }, 697 { 698 .name = "ctl_1", .id = CTL_1, 699 .base = 0x16000, .len = 0x1E8, 700 .features = CTL_SC7280_MASK, 701 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 702 }, 703 { 704 .name = "ctl_2", .id = CTL_2, 705 .base = 0x17000, .len = 0x1E8, 706 .features = CTL_SC7280_MASK, 707 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 708 }, 709 { 710 .name = "ctl_3", .id = CTL_3, 711 .base = 0x18000, .len = 0x1E8, 712 .features = CTL_SC7280_MASK, 713 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 714 }, 715 }; 716 717 static const struct dpu_ctl_cfg qcm2290_ctl[] = { 718 { 719 .name = "ctl_0", .id = CTL_0, 720 .base = 0x1000, .len = 0x1dc, 721 .features = BIT(DPU_CTL_ACTIVE_CFG), 722 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 723 }, 724 }; 725 726 /************************************************************* 727 * SSPP sub blocks config 728 *************************************************************/ 729 730 /* SSPP common configuration */ 731 #define _VIG_SBLK(num, sdma_pri, qseed_ver) \ 732 { \ 733 .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 734 .maxupscale = MAX_UPSCALE_RATIO, \ 735 .smart_dma_priority = sdma_pri, \ 736 .src_blk = {.name = STRCAT("sspp_src_", num), \ 737 .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ 738 .scaler_blk = {.name = STRCAT("sspp_scaler", num), \ 739 .id = qseed_ver, \ 740 .base = 0xa00, .len = 0xa0,}, \ 741 .csc_blk = {.name = STRCAT("sspp_csc", num), \ 742 .id = DPU_SSPP_CSC_10BIT, \ 743 .base = 0x1a00, .len = 0x100,}, \ 744 .format_list = plane_formats_yuv, \ 745 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 746 .virt_format_list = plane_formats, \ 747 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 748 .rotation_cfg = NULL, \ 749 } 750 751 #define _VIG_SBLK_ROT(num, sdma_pri, qseed_ver, rot_cfg) \ 752 { \ 753 .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 754 .maxupscale = MAX_UPSCALE_RATIO, \ 755 .smart_dma_priority = sdma_pri, \ 756 .src_blk = {.name = STRCAT("sspp_src_", num), \ 757 .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ 758 .scaler_blk = {.name = STRCAT("sspp_scaler", num), \ 759 .id = qseed_ver, \ 760 .base = 0xa00, .len = 0xa0,}, \ 761 .csc_blk = {.name = STRCAT("sspp_csc", num), \ 762 .id = DPU_SSPP_CSC_10BIT, \ 763 .base = 0x1a00, .len = 0x100,}, \ 764 .format_list = plane_formats_yuv, \ 765 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 766 .virt_format_list = plane_formats, \ 767 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 768 .rotation_cfg = rot_cfg, \ 769 } 770 771 #define _DMA_SBLK(num, sdma_pri) \ 772 { \ 773 .maxdwnscale = SSPP_UNITY_SCALE, \ 774 .maxupscale = SSPP_UNITY_SCALE, \ 775 .smart_dma_priority = sdma_pri, \ 776 .src_blk = {.name = STRCAT("sspp_src_", num), \ 777 .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ 778 .format_list = plane_formats, \ 779 .num_formats = ARRAY_SIZE(plane_formats), \ 780 .virt_format_list = plane_formats, \ 781 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 782 } 783 784 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 = 785 _VIG_SBLK("0", 0, DPU_SSPP_SCALER_QSEED3); 786 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 = 787 _VIG_SBLK("1", 0, DPU_SSPP_SCALER_QSEED3); 788 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 = 789 _VIG_SBLK("2", 0, DPU_SSPP_SCALER_QSEED3); 790 static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 = 791 _VIG_SBLK("3", 0, DPU_SSPP_SCALER_QSEED3); 792 793 static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { 794 .rot_maxheight = 1088, 795 .rot_num_formats = ARRAY_SIZE(rotation_v2_formats), 796 .rot_format_list = rotation_v2_formats, 797 }; 798 799 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = 800 _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3); 801 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = 802 _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3); 803 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = 804 _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3); 805 static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = 806 _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3); 807 808 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1); 809 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2); 810 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3); 811 static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4); 812 813 #define SSPP_BLK(_name, _id, _base, _features, \ 814 _sblk, _xinid, _type, _clkctrl) \ 815 { \ 816 .name = _name, .id = _id, \ 817 .base = _base, .len = 0x1c8, \ 818 .features = _features, \ 819 .sblk = &_sblk, \ 820 .xin_id = _xinid, \ 821 .type = _type, \ 822 .clk_ctrl = _clkctrl \ 823 } 824 825 static const struct dpu_sspp_cfg msm8998_sspp[] = { 826 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_MSM8998_MASK, 827 msm8998_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 828 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_MSM8998_MASK, 829 msm8998_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 830 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_MSM8998_MASK, 831 msm8998_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 832 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_MSM8998_MASK, 833 msm8998_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 834 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_MSM8998_MASK, 835 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 836 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_MSM8998_MASK, 837 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 838 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_MSM8998_MASK, 839 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), 840 SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_MSM8998_MASK, 841 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), 842 }; 843 844 static const struct dpu_sspp_cfg sdm845_sspp[] = { 845 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK, 846 sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 847 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK, 848 sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 849 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK, 850 sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 851 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK, 852 sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 853 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, 854 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 855 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, 856 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 857 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, 858 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), 859 SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, 860 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), 861 }; 862 863 static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = 864 _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4); 865 866 static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 = 867 _VIG_SBLK_ROT("0", 4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2); 868 869 static const struct dpu_sspp_cfg sc7180_sspp[] = { 870 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, 871 sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 872 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, 873 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 874 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK, 875 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), 876 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, 877 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), 878 }; 879 880 static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 = 881 _VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED3LITE); 882 883 static const struct dpu_sspp_cfg sm6115_sspp[] = { 884 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK, 885 sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 886 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, 887 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 888 }; 889 890 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 = 891 _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3LITE); 892 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 = 893 _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3LITE); 894 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 = 895 _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3LITE); 896 static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 = 897 _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3LITE); 898 899 static const struct dpu_sspp_cfg sm8250_sspp[] = { 900 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SM8250_MASK, 901 sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 902 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SM8250_MASK, 903 sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 904 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SM8250_MASK, 905 sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 906 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SM8250_MASK, 907 sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 908 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, 909 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 910 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, 911 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 912 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, 913 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), 914 SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, 915 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), 916 }; 917 918 static const struct dpu_sspp_cfg sc7280_sspp[] = { 919 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7280_MASK, 920 sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 921 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, 922 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 923 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK, 924 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), 925 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, 926 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), 927 }; 928 929 930 #define _VIG_SBLK_NOSCALE(num, sdma_pri) \ 931 { \ 932 .maxdwnscale = SSPP_UNITY_SCALE, \ 933 .maxupscale = SSPP_UNITY_SCALE, \ 934 .smart_dma_priority = sdma_pri, \ 935 .src_blk = {.name = STRCAT("sspp_src_", num), \ 936 .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ 937 .format_list = plane_formats_yuv, \ 938 .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 939 .virt_format_list = plane_formats, \ 940 .virt_num_formats = ARRAY_SIZE(plane_formats), \ 941 } 942 943 static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE("0", 2); 944 static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1); 945 946 static const struct dpu_sspp_cfg qcm2290_sspp[] = { 947 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_QCM2290_MASK, 948 qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 949 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, 950 qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 951 }; 952 953 /************************************************************* 954 * MIXER sub blocks config 955 *************************************************************/ 956 957 #define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \ 958 { \ 959 .name = _name, .id = _id, \ 960 .base = _base, .len = 0x320, \ 961 .features = _fmask, \ 962 .sblk = _sblk, \ 963 .pingpong = _pp, \ 964 .lm_pair_mask = (1 << _lmpair), \ 965 .dspp = _dspp \ 966 } 967 968 /* MSM8998 */ 969 970 static const struct dpu_lm_sub_blks msm8998_lm_sblk = { 971 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 972 .maxblendstages = 7, /* excluding base layer */ 973 .blendstage_base = { /* offsets relative to mixer base */ 974 0x20, 0x50, 0x80, 0xb0, 0x230, 975 0x260, 0x290 976 }, 977 }; 978 979 static const struct dpu_lm_cfg msm8998_lm[] = { 980 LM_BLK("lm_0", LM_0, 0x44000, MIXER_MSM8998_MASK, 981 &msm8998_lm_sblk, PINGPONG_0, LM_2, DSPP_0), 982 LM_BLK("lm_1", LM_1, 0x45000, MIXER_MSM8998_MASK, 983 &msm8998_lm_sblk, PINGPONG_1, LM_5, DSPP_1), 984 LM_BLK("lm_2", LM_2, 0x46000, MIXER_MSM8998_MASK, 985 &msm8998_lm_sblk, PINGPONG_2, LM_0, 0), 986 LM_BLK("lm_3", LM_3, 0x47000, MIXER_MSM8998_MASK, 987 &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), 988 LM_BLK("lm_4", LM_4, 0x48000, MIXER_MSM8998_MASK, 989 &msm8998_lm_sblk, PINGPONG_MAX, 0, 0), 990 LM_BLK("lm_5", LM_5, 0x49000, MIXER_MSM8998_MASK, 991 &msm8998_lm_sblk, PINGPONG_3, LM_1, 0), 992 }; 993 994 /* SDM845 */ 995 996 static const struct dpu_lm_sub_blks sdm845_lm_sblk = { 997 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 998 .maxblendstages = 11, /* excluding base layer */ 999 .blendstage_base = { /* offsets relative to mixer base */ 1000 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 1001 0xb0, 0xc8, 0xe0, 0xf8, 0x110 1002 }, 1003 }; 1004 1005 static const struct dpu_lm_cfg sdm845_lm[] = { 1006 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 1007 &sdm845_lm_sblk, PINGPONG_0, LM_1, 0), 1008 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, 1009 &sdm845_lm_sblk, PINGPONG_1, LM_0, 0), 1010 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, 1011 &sdm845_lm_sblk, PINGPONG_2, LM_5, 0), 1012 LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK, 1013 &sdm845_lm_sblk, PINGPONG_MAX, 0, 0), 1014 LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK, 1015 &sdm845_lm_sblk, PINGPONG_MAX, 0, 0), 1016 LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, 1017 &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), 1018 }; 1019 1020 /* SC7180 */ 1021 1022 static const struct dpu_lm_sub_blks sc7180_lm_sblk = { 1023 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 1024 .maxblendstages = 7, /* excluding base layer */ 1025 .blendstage_base = { /* offsets relative to mixer base */ 1026 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0 1027 }, 1028 }; 1029 1030 static const struct dpu_lm_cfg sc7180_lm[] = { 1031 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK, 1032 &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0), 1033 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SC7180_MASK, 1034 &sc7180_lm_sblk, PINGPONG_1, LM_0, 0), 1035 }; 1036 1037 /* SM8150 */ 1038 1039 static const struct dpu_lm_cfg sm8150_lm[] = { 1040 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 1041 &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), 1042 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, 1043 &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), 1044 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, 1045 &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), 1046 LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, 1047 &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), 1048 LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, 1049 &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), 1050 LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, 1051 &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), 1052 }; 1053 1054 static const struct dpu_lm_cfg sc7280_lm[] = { 1055 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK, 1056 &sc7180_lm_sblk, PINGPONG_0, 0, DSPP_0), 1057 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SC7180_MASK, 1058 &sc7180_lm_sblk, PINGPONG_2, LM_3, 0), 1059 LM_BLK("lm_3", LM_3, 0x47000, MIXER_SC7180_MASK, 1060 &sc7180_lm_sblk, PINGPONG_3, LM_2, 0), 1061 }; 1062 1063 /* QCM2290 */ 1064 1065 static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { 1066 .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 1067 .maxblendstages = 4, /* excluding base layer */ 1068 .blendstage_base = { /* offsets relative to mixer base */ 1069 0x20, 0x38, 0x50, 0x68 1070 }, 1071 }; 1072 1073 static const struct dpu_lm_cfg qcm2290_lm[] = { 1074 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK, 1075 &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0), 1076 }; 1077 1078 /************************************************************* 1079 * DSPP sub blocks config 1080 *************************************************************/ 1081 static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { 1082 .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, 1083 .len = 0x90, .version = 0x10007}, 1084 .gc = { .id = DPU_DSPP_GC, .base = 0x17c0, 1085 .len = 0x90, .version = 0x10007}, 1086 }; 1087 1088 static const struct dpu_dspp_sub_blks sc7180_dspp_sblk = { 1089 .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, 1090 .len = 0x90, .version = 0x10000}, 1091 }; 1092 1093 static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = { 1094 .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, 1095 .len = 0x90, .version = 0x40000}, 1096 }; 1097 1098 #define DSPP_BLK(_name, _id, _base, _mask, _sblk) \ 1099 {\ 1100 .name = _name, .id = _id, \ 1101 .base = _base, .len = 0x1800, \ 1102 .features = _mask, \ 1103 .sblk = _sblk \ 1104 } 1105 1106 static const struct dpu_dspp_cfg msm8998_dspp[] = { 1107 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_MSM8998_MASK, 1108 &msm8998_dspp_sblk), 1109 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_MSM8998_MASK, 1110 &msm8998_dspp_sblk), 1111 }; 1112 1113 static const struct dpu_dspp_cfg sc7180_dspp[] = { 1114 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 1115 &sc7180_dspp_sblk), 1116 }; 1117 1118 static const struct dpu_dspp_cfg sm8150_dspp[] = { 1119 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 1120 &sm8150_dspp_sblk), 1121 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, 1122 &sm8150_dspp_sblk), 1123 DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, 1124 &sm8150_dspp_sblk), 1125 DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, 1126 &sm8150_dspp_sblk), 1127 }; 1128 1129 static const struct dpu_dspp_cfg qcm2290_dspp[] = { 1130 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 1131 &sm8150_dspp_sblk), 1132 }; 1133 1134 /************************************************************* 1135 * PINGPONG sub blocks config 1136 *************************************************************/ 1137 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = { 1138 .te2 = {.id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0, 1139 .version = 0x1}, 1140 .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0, 1141 .len = 0x20, .version = 0x10000}, 1142 }; 1143 1144 static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = { 1145 .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0, 1146 .len = 0x20, .version = 0x10000}, 1147 }; 1148 1149 static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { 1150 .dither = {.id = DPU_PINGPONG_DITHER, .base = 0xe0, 1151 .len = 0x20, .version = 0x20000}, 1152 }; 1153 1154 #define PP_BLK_TE(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \ 1155 {\ 1156 .name = _name, .id = _id, \ 1157 .base = _base, .len = 0xd4, \ 1158 .features = PINGPONG_SDM845_SPLIT_MASK, \ 1159 .merge_3d = _merge_3d, \ 1160 .sblk = &_sblk, \ 1161 .intr_done = _done, \ 1162 .intr_rdptr = _rdptr, \ 1163 } 1164 #define PP_BLK(_name, _id, _base, _merge_3d, _sblk, _done, _rdptr) \ 1165 {\ 1166 .name = _name, .id = _id, \ 1167 .base = _base, .len = 0xd4, \ 1168 .features = PINGPONG_SDM845_MASK, \ 1169 .merge_3d = _merge_3d, \ 1170 .sblk = &_sblk, \ 1171 .intr_done = _done, \ 1172 .intr_rdptr = _rdptr, \ 1173 } 1174 1175 static const struct dpu_pingpong_cfg sdm845_pp[] = { 1176 PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, 1177 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 1178 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 1179 PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, 1180 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 1181 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 1182 PP_BLK("pingpong_2", PINGPONG_2, 0x71000, 0, sdm845_pp_sblk, 1183 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 1184 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), 1185 PP_BLK("pingpong_3", PINGPONG_3, 0x71800, 0, sdm845_pp_sblk, 1186 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 1187 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), 1188 }; 1189 1190 static struct dpu_pingpong_cfg sc7180_pp[] = { 1191 PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, -1, -1), 1192 PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1), 1193 }; 1194 1195 static const struct dpu_pingpong_cfg sm8150_pp[] = { 1196 PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, MERGE_3D_0, sdm845_pp_sblk_te, 1197 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 1198 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 1199 PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, MERGE_3D_0, sdm845_pp_sblk_te, 1200 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 1201 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 1202 PP_BLK("pingpong_2", PINGPONG_2, 0x71000, MERGE_3D_1, sdm845_pp_sblk, 1203 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 1204 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), 1205 PP_BLK("pingpong_3", PINGPONG_3, 0x71800, MERGE_3D_1, sdm845_pp_sblk, 1206 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 1207 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), 1208 PP_BLK("pingpong_4", PINGPONG_4, 0x72000, MERGE_3D_2, sdm845_pp_sblk, 1209 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 1210 -1), 1211 PP_BLK("pingpong_5", PINGPONG_5, 0x72800, MERGE_3D_2, sdm845_pp_sblk, 1212 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 1213 -1), 1214 }; 1215 1216 static const struct dpu_pingpong_cfg sc7280_pp[] = { 1217 PP_BLK("pingpong_0", PINGPONG_0, 0x59000, 0, sc7280_pp_sblk, -1, -1), 1218 PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1), 1219 PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1), 1220 PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1), 1221 }; 1222 1223 static struct dpu_pingpong_cfg qcm2290_pp[] = { 1224 PP_BLK("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk, 1225 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 1226 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 1227 }; 1228 1229 /************************************************************* 1230 * MERGE_3D sub blocks config 1231 *************************************************************/ 1232 #define MERGE_3D_BLK(_name, _id, _base) \ 1233 {\ 1234 .name = _name, .id = _id, \ 1235 .base = _base, .len = 0x100, \ 1236 .features = MERGE_3D_SM8150_MASK, \ 1237 .sblk = NULL \ 1238 } 1239 1240 static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { 1241 MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x83000), 1242 MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x83100), 1243 MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x83200), 1244 }; 1245 1246 /************************************************************* 1247 * DSC sub blocks config 1248 *************************************************************/ 1249 #define DSC_BLK(_name, _id, _base) \ 1250 {\ 1251 .name = _name, .id = _id, \ 1252 .base = _base, .len = 0x140, \ 1253 .features = 0, \ 1254 } 1255 1256 static struct dpu_dsc_cfg sdm845_dsc[] = { 1257 DSC_BLK("dsc_0", DSC_0, 0x80000), 1258 DSC_BLK("dsc_1", DSC_1, 0x80400), 1259 DSC_BLK("dsc_2", DSC_2, 0x80800), 1260 DSC_BLK("dsc_3", DSC_3, 0x80c00), 1261 }; 1262 1263 /************************************************************* 1264 * INTF sub blocks config 1265 *************************************************************/ 1266 #define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _progfetch, _features, _reg, _underrun_bit, _vsync_bit) \ 1267 {\ 1268 .name = _name, .id = _id, \ 1269 .base = _base, .len = 0x280, \ 1270 .features = _features, \ 1271 .type = _type, \ 1272 .controller_id = _ctrl_id, \ 1273 .prog_fetch_lines_worst_case = _progfetch, \ 1274 .intr_underrun = DPU_IRQ_IDX(_reg, _underrun_bit), \ 1275 .intr_vsync = DPU_IRQ_IDX(_reg, _vsync_bit), \ 1276 } 1277 1278 static const struct dpu_intf_cfg msm8998_intf[] = { 1279 INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 1280 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 1281 INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 1282 INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_HDMI, 0, 25, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 1283 }; 1284 1285 static const struct dpu_intf_cfg sdm845_intf[] = { 1286 INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 1287 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 1288 INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 1289 INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SDM845_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 1290 }; 1291 1292 static const struct dpu_intf_cfg sc7180_intf[] = { 1293 INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 1294 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 1295 }; 1296 1297 static const struct dpu_intf_cfg sm8150_intf[] = { 1298 INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 1299 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 1300 INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 1301 INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 1302 }; 1303 1304 static const struct dpu_intf_cfg sc7280_intf[] = { 1305 INTF_BLK("intf_0", INTF_0, 0x34000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 1306 INTF_BLK("intf_1", INTF_1, 0x35000, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 1307 INTF_BLK("intf_5", INTF_5, 0x39000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), 1308 }; 1309 1310 static const struct dpu_intf_cfg sc8180x_intf[] = { 1311 INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 1312 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 1313 INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 1314 /* INTF_3 is for MST, wired to INTF_DP 0 and 1, use dummy index until this is supported */ 1315 INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 999, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 1316 INTF_BLK("intf_4", INTF_4, 0x6C000, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 20, 21), 1317 INTF_BLK("intf_5", INTF_5, 0x6C800, INTF_DP, MSM_DP_CONTROLLER_2, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 22, 23), 1318 }; 1319 1320 static const struct dpu_intf_cfg qcm2290_intf[] = { 1321 INTF_BLK("intf_0", INTF_0, 0x00000, INTF_NONE, 0, 0, 0, 0, 0, 0), 1322 INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 1323 }; 1324 1325 /************************************************************* 1326 * Writeback blocks config 1327 *************************************************************/ 1328 #define WB_BLK(_name, _id, _base, _features, _clk_ctrl, \ 1329 __xin_id, vbif_id, _reg, _max_linewidth, _wb_done_bit) \ 1330 { \ 1331 .name = _name, .id = _id, \ 1332 .base = _base, .len = 0x2c8, \ 1333 .features = _features, \ 1334 .format_list = wb2_formats, \ 1335 .num_formats = ARRAY_SIZE(wb2_formats), \ 1336 .clk_ctrl = _clk_ctrl, \ 1337 .xin_id = __xin_id, \ 1338 .vbif_idx = vbif_id, \ 1339 .maxlinewidth = _max_linewidth, \ 1340 .intr_wb_done = DPU_IRQ_IDX(_reg, _wb_done_bit) \ 1341 } 1342 1343 static const struct dpu_wb_cfg sm8250_wb[] = { 1344 WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6, 1345 VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4), 1346 }; 1347 1348 /************************************************************* 1349 * VBIF sub blocks config 1350 *************************************************************/ 1351 /* VBIF QOS remap */ 1352 static const u32 msm8998_rt_pri_lvl[] = {1, 2, 2, 2}; 1353 static const u32 msm8998_nrt_pri_lvl[] = {1, 1, 1, 1}; 1354 static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6}; 1355 static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3}; 1356 1357 static const struct dpu_vbif_dynamic_ot_cfg msm8998_ot_rdwr_cfg[] = { 1358 { 1359 .pps = 1088 * 1920 * 30, 1360 .ot_limit = 2, 1361 }, 1362 { 1363 .pps = 1088 * 1920 * 60, 1364 .ot_limit = 6, 1365 }, 1366 { 1367 .pps = 3840 * 2160 * 30, 1368 .ot_limit = 16, 1369 }, 1370 }; 1371 1372 static const struct dpu_vbif_cfg msm8998_vbif[] = { 1373 { 1374 .name = "vbif_rt", .id = VBIF_RT, 1375 .base = 0, .len = 0x1040, 1376 .default_ot_rd_limit = 32, 1377 .default_ot_wr_limit = 32, 1378 .features = BIT(DPU_VBIF_QOS_REMAP) | BIT(DPU_VBIF_QOS_OTLIM), 1379 .xin_halt_timeout = 0x4000, 1380 .qos_rp_remap_size = 0x20, 1381 .dynamic_ot_rd_tbl = { 1382 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 1383 .cfg = msm8998_ot_rdwr_cfg, 1384 }, 1385 .dynamic_ot_wr_tbl = { 1386 .count = ARRAY_SIZE(msm8998_ot_rdwr_cfg), 1387 .cfg = msm8998_ot_rdwr_cfg, 1388 }, 1389 .qos_rt_tbl = { 1390 .npriority_lvl = ARRAY_SIZE(msm8998_rt_pri_lvl), 1391 .priority_lvl = msm8998_rt_pri_lvl, 1392 }, 1393 .qos_nrt_tbl = { 1394 .npriority_lvl = ARRAY_SIZE(msm8998_nrt_pri_lvl), 1395 .priority_lvl = msm8998_nrt_pri_lvl, 1396 }, 1397 .memtype_count = 14, 1398 .memtype = {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2}, 1399 }, 1400 }; 1401 1402 static const struct dpu_vbif_cfg sdm845_vbif[] = { 1403 { 1404 .name = "vbif_rt", .id = VBIF_RT, 1405 .base = 0, .len = 0x1040, 1406 .features = BIT(DPU_VBIF_QOS_REMAP), 1407 .xin_halt_timeout = 0x4000, 1408 .qos_rp_remap_size = 0x40, 1409 .qos_rt_tbl = { 1410 .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), 1411 .priority_lvl = sdm845_rt_pri_lvl, 1412 }, 1413 .qos_nrt_tbl = { 1414 .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 1415 .priority_lvl = sdm845_nrt_pri_lvl, 1416 }, 1417 .memtype_count = 14, 1418 .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 1419 }, 1420 }; 1421 1422 static const struct dpu_reg_dma_cfg sdm845_regdma = { 1423 .base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c 1424 }; 1425 1426 static const struct dpu_reg_dma_cfg sm8150_regdma = { 1427 .base = 0x0, .version = 0x00010001, .trigger_sel_off = 0x119c 1428 }; 1429 1430 static const struct dpu_reg_dma_cfg sm8250_regdma = { 1431 .base = 0x0, 1432 .version = 0x00010002, 1433 .trigger_sel_off = 0x119c, 1434 .xin_id = 7, 1435 .clk_ctrl = DPU_CLK_CTRL_REG_DMA, 1436 }; 1437 1438 /************************************************************* 1439 * PERF data config 1440 *************************************************************/ 1441 1442 /* SSPP QOS LUTs */ 1443 static const struct dpu_qos_lut_entry msm8998_qos_linear[] = { 1444 {.fl = 4, .lut = 0x1b}, 1445 {.fl = 5, .lut = 0x5b}, 1446 {.fl = 6, .lut = 0x15b}, 1447 {.fl = 7, .lut = 0x55b}, 1448 {.fl = 8, .lut = 0x155b}, 1449 {.fl = 9, .lut = 0x555b}, 1450 {.fl = 10, .lut = 0x1555b}, 1451 {.fl = 11, .lut = 0x5555b}, 1452 {.fl = 12, .lut = 0x15555b}, 1453 {.fl = 13, .lut = 0x55555b}, 1454 {.fl = 14, .lut = 0}, 1455 {.fl = 1, .lut = 0x1b}, 1456 {.fl = 0, .lut = 0} 1457 }; 1458 1459 static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { 1460 {.fl = 4, .lut = 0x357}, 1461 {.fl = 5, .lut = 0x3357}, 1462 {.fl = 6, .lut = 0x23357}, 1463 {.fl = 7, .lut = 0x223357}, 1464 {.fl = 8, .lut = 0x2223357}, 1465 {.fl = 9, .lut = 0x22223357}, 1466 {.fl = 10, .lut = 0x222223357}, 1467 {.fl = 11, .lut = 0x2222223357}, 1468 {.fl = 12, .lut = 0x22222223357}, 1469 {.fl = 13, .lut = 0x222222223357}, 1470 {.fl = 14, .lut = 0x1222222223357}, 1471 {.fl = 0, .lut = 0x11222222223357} 1472 }; 1473 1474 static const struct dpu_qos_lut_entry msm8998_qos_macrotile[] = { 1475 {.fl = 10, .lut = 0x1aaff}, 1476 {.fl = 11, .lut = 0x5aaff}, 1477 {.fl = 12, .lut = 0x15aaff}, 1478 {.fl = 13, .lut = 0x55aaff}, 1479 {.fl = 1, .lut = 0x1aaff}, 1480 {.fl = 0, .lut = 0}, 1481 }; 1482 1483 static const struct dpu_qos_lut_entry sc7180_qos_linear[] = { 1484 {.fl = 0, .lut = 0x0011222222335777}, 1485 }; 1486 1487 static const struct dpu_qos_lut_entry sm8150_qos_linear[] = { 1488 {.fl = 0, .lut = 0x0011222222223357 }, 1489 }; 1490 1491 static const struct dpu_qos_lut_entry sc8180x_qos_linear[] = { 1492 {.fl = 4, .lut = 0x0000000000000357 }, 1493 }; 1494 1495 static const struct dpu_qos_lut_entry qcm2290_qos_linear[] = { 1496 {.fl = 0, .lut = 0x0011222222335777}, 1497 }; 1498 1499 static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = { 1500 {.fl = 10, .lut = 0x344556677}, 1501 {.fl = 11, .lut = 0x3344556677}, 1502 {.fl = 12, .lut = 0x23344556677}, 1503 {.fl = 13, .lut = 0x223344556677}, 1504 {.fl = 14, .lut = 0x1223344556677}, 1505 {.fl = 0, .lut = 0x112233344556677}, 1506 }; 1507 1508 static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = { 1509 {.fl = 0, .lut = 0x0011223344556677}, 1510 }; 1511 1512 static const struct dpu_qos_lut_entry sc8180x_qos_macrotile[] = { 1513 {.fl = 10, .lut = 0x0000000344556677}, 1514 }; 1515 1516 static const struct dpu_qos_lut_entry msm8998_qos_nrt[] = { 1517 {.fl = 0, .lut = 0x0}, 1518 }; 1519 1520 static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = { 1521 {.fl = 0, .lut = 0x0}, 1522 }; 1523 1524 static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { 1525 {.fl = 0, .lut = 0x0}, 1526 }; 1527 1528 static const struct dpu_perf_cfg msm8998_perf_data = { 1529 .max_bw_low = 6700000, 1530 .max_bw_high = 6700000, 1531 .min_core_ib = 2400000, 1532 .min_llcc_ib = 800000, 1533 .min_dram_ib = 800000, 1534 .undersized_prefill_lines = 2, 1535 .xtra_prefill_lines = 2, 1536 .dest_scale_prefill_lines = 3, 1537 .macrotile_prefill_lines = 4, 1538 .yuv_nv12_prefill_lines = 8, 1539 .linear_prefill_lines = 1, 1540 .downscaling_prefill_lines = 1, 1541 .amortizable_threshold = 25, 1542 .min_prefill_lines = 25, 1543 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 1544 .safe_lut_tbl = {0xfffc, 0xff00, 0xffff}, 1545 .qos_lut_tbl = { 1546 {.nentry = ARRAY_SIZE(msm8998_qos_linear), 1547 .entries = msm8998_qos_linear 1548 }, 1549 {.nentry = ARRAY_SIZE(msm8998_qos_macrotile), 1550 .entries = msm8998_qos_macrotile 1551 }, 1552 {.nentry = ARRAY_SIZE(msm8998_qos_nrt), 1553 .entries = msm8998_qos_nrt 1554 }, 1555 }, 1556 .cdp_cfg = { 1557 {.rd_enable = 1, .wr_enable = 1}, 1558 {.rd_enable = 1, .wr_enable = 0} 1559 }, 1560 .clk_inefficiency_factor = 200, 1561 .bw_inefficiency_factor = 120, 1562 }; 1563 1564 static const struct dpu_perf_cfg sdm845_perf_data = { 1565 .max_bw_low = 6800000, 1566 .max_bw_high = 6800000, 1567 .min_core_ib = 2400000, 1568 .min_llcc_ib = 800000, 1569 .min_dram_ib = 800000, 1570 .undersized_prefill_lines = 2, 1571 .xtra_prefill_lines = 2, 1572 .dest_scale_prefill_lines = 3, 1573 .macrotile_prefill_lines = 4, 1574 .yuv_nv12_prefill_lines = 8, 1575 .linear_prefill_lines = 1, 1576 .downscaling_prefill_lines = 1, 1577 .amortizable_threshold = 25, 1578 .min_prefill_lines = 24, 1579 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 1580 .safe_lut_tbl = {0xfff0, 0xf000, 0xffff}, 1581 .qos_lut_tbl = { 1582 {.nentry = ARRAY_SIZE(sdm845_qos_linear), 1583 .entries = sdm845_qos_linear 1584 }, 1585 {.nentry = ARRAY_SIZE(sdm845_qos_macrotile), 1586 .entries = sdm845_qos_macrotile 1587 }, 1588 {.nentry = ARRAY_SIZE(sdm845_qos_nrt), 1589 .entries = sdm845_qos_nrt 1590 }, 1591 }, 1592 .cdp_cfg = { 1593 {.rd_enable = 1, .wr_enable = 1}, 1594 {.rd_enable = 1, .wr_enable = 0} 1595 }, 1596 .clk_inefficiency_factor = 105, 1597 .bw_inefficiency_factor = 120, 1598 }; 1599 1600 static const struct dpu_perf_cfg sc7180_perf_data = { 1601 .max_bw_low = 6800000, 1602 .max_bw_high = 6800000, 1603 .min_core_ib = 2400000, 1604 .min_llcc_ib = 800000, 1605 .min_dram_ib = 1600000, 1606 .min_prefill_lines = 24, 1607 .danger_lut_tbl = {0xff, 0xffff, 0x0}, 1608 .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, 1609 .qos_lut_tbl = { 1610 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 1611 .entries = sc7180_qos_linear 1612 }, 1613 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 1614 .entries = sc7180_qos_macrotile 1615 }, 1616 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 1617 .entries = sc7180_qos_nrt 1618 }, 1619 }, 1620 .cdp_cfg = { 1621 {.rd_enable = 1, .wr_enable = 1}, 1622 {.rd_enable = 1, .wr_enable = 0} 1623 }, 1624 .clk_inefficiency_factor = 105, 1625 .bw_inefficiency_factor = 120, 1626 }; 1627 1628 static const struct dpu_perf_cfg sm6115_perf_data = { 1629 .max_bw_low = 3100000, 1630 .max_bw_high = 4000000, 1631 .min_core_ib = 2400000, 1632 .min_llcc_ib = 800000, 1633 .min_dram_ib = 800000, 1634 .min_prefill_lines = 24, 1635 .danger_lut_tbl = {0xff, 0xffff, 0x0}, 1636 .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, 1637 .qos_lut_tbl = { 1638 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 1639 .entries = sc7180_qos_linear 1640 }, 1641 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 1642 .entries = sc7180_qos_macrotile 1643 }, 1644 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 1645 .entries = sc7180_qos_nrt 1646 }, 1647 /* TODO: macrotile-qseed is different from macrotile */ 1648 }, 1649 .cdp_cfg = { 1650 {.rd_enable = 1, .wr_enable = 1}, 1651 {.rd_enable = 1, .wr_enable = 0} 1652 }, 1653 .clk_inefficiency_factor = 105, 1654 .bw_inefficiency_factor = 120, 1655 }; 1656 1657 static const struct dpu_perf_cfg sm8150_perf_data = { 1658 .max_bw_low = 12800000, 1659 .max_bw_high = 12800000, 1660 .min_core_ib = 2400000, 1661 .min_llcc_ib = 800000, 1662 .min_dram_ib = 800000, 1663 .min_prefill_lines = 24, 1664 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 1665 .safe_lut_tbl = {0xfff8, 0xf000, 0xffff}, 1666 .qos_lut_tbl = { 1667 {.nentry = ARRAY_SIZE(sm8150_qos_linear), 1668 .entries = sm8150_qos_linear 1669 }, 1670 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 1671 .entries = sc7180_qos_macrotile 1672 }, 1673 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 1674 .entries = sc7180_qos_nrt 1675 }, 1676 /* TODO: macrotile-qseed is different from macrotile */ 1677 }, 1678 .cdp_cfg = { 1679 {.rd_enable = 1, .wr_enable = 1}, 1680 {.rd_enable = 1, .wr_enable = 0} 1681 }, 1682 .clk_inefficiency_factor = 105, 1683 .bw_inefficiency_factor = 120, 1684 }; 1685 1686 static const struct dpu_perf_cfg sc8180x_perf_data = { 1687 .max_bw_low = 9600000, 1688 .max_bw_high = 9600000, 1689 .min_core_ib = 2400000, 1690 .min_llcc_ib = 800000, 1691 .min_dram_ib = 800000, 1692 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 1693 .qos_lut_tbl = { 1694 {.nentry = ARRAY_SIZE(sc8180x_qos_linear), 1695 .entries = sc8180x_qos_linear 1696 }, 1697 {.nentry = ARRAY_SIZE(sc8180x_qos_macrotile), 1698 .entries = sc8180x_qos_macrotile 1699 }, 1700 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 1701 .entries = sc7180_qos_nrt 1702 }, 1703 /* TODO: macrotile-qseed is different from macrotile */ 1704 }, 1705 .cdp_cfg = { 1706 {.rd_enable = 1, .wr_enable = 1}, 1707 {.rd_enable = 1, .wr_enable = 0} 1708 }, 1709 .clk_inefficiency_factor = 105, 1710 .bw_inefficiency_factor = 120, 1711 }; 1712 1713 static const struct dpu_perf_cfg sm8250_perf_data = { 1714 .max_bw_low = 13700000, 1715 .max_bw_high = 16600000, 1716 .min_core_ib = 4800000, 1717 .min_llcc_ib = 0, 1718 .min_dram_ib = 800000, 1719 .min_prefill_lines = 35, 1720 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 1721 .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, 1722 .qos_lut_tbl = { 1723 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 1724 .entries = sc7180_qos_linear 1725 }, 1726 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 1727 .entries = sc7180_qos_macrotile 1728 }, 1729 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 1730 .entries = sc7180_qos_nrt 1731 }, 1732 /* TODO: macrotile-qseed is different from macrotile */ 1733 }, 1734 .cdp_cfg = { 1735 {.rd_enable = 1, .wr_enable = 1}, 1736 {.rd_enable = 1, .wr_enable = 0} 1737 }, 1738 .clk_inefficiency_factor = 105, 1739 .bw_inefficiency_factor = 120, 1740 }; 1741 1742 static const struct dpu_perf_cfg sc7280_perf_data = { 1743 .max_bw_low = 4700000, 1744 .max_bw_high = 8800000, 1745 .min_core_ib = 2500000, 1746 .min_llcc_ib = 0, 1747 .min_dram_ib = 1600000, 1748 .min_prefill_lines = 24, 1749 .danger_lut_tbl = {0xffff, 0xffff, 0x0}, 1750 .safe_lut_tbl = {0xff00, 0xff00, 0xffff}, 1751 .qos_lut_tbl = { 1752 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 1753 .entries = sc7180_qos_macrotile 1754 }, 1755 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 1756 .entries = sc7180_qos_macrotile 1757 }, 1758 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 1759 .entries = sc7180_qos_nrt 1760 }, 1761 }, 1762 .cdp_cfg = { 1763 {.rd_enable = 1, .wr_enable = 1}, 1764 {.rd_enable = 1, .wr_enable = 0} 1765 }, 1766 .clk_inefficiency_factor = 105, 1767 .bw_inefficiency_factor = 120, 1768 }; 1769 1770 static const struct dpu_perf_cfg qcm2290_perf_data = { 1771 .max_bw_low = 2700000, 1772 .max_bw_high = 2700000, 1773 .min_core_ib = 1300000, 1774 .min_llcc_ib = 0, 1775 .min_dram_ib = 1600000, 1776 .min_prefill_lines = 24, 1777 .danger_lut_tbl = {0xff, 0x0, 0x0}, 1778 .safe_lut_tbl = {0xfff0, 0x0, 0x0}, 1779 .qos_lut_tbl = { 1780 {.nentry = ARRAY_SIZE(qcm2290_qos_linear), 1781 .entries = qcm2290_qos_linear 1782 }, 1783 }, 1784 .cdp_cfg = { 1785 {.rd_enable = 1, .wr_enable = 1}, 1786 {.rd_enable = 1, .wr_enable = 0} 1787 }, 1788 .clk_inefficiency_factor = 105, 1789 .bw_inefficiency_factor = 120, 1790 }; 1791 /************************************************************* 1792 * Hardware catalog 1793 *************************************************************/ 1794 1795 static const struct dpu_mdss_cfg msm8998_dpu_cfg = { 1796 .caps = &msm8998_dpu_caps, 1797 .mdp_count = ARRAY_SIZE(msm8998_mdp), 1798 .mdp = msm8998_mdp, 1799 .ctl_count = ARRAY_SIZE(msm8998_ctl), 1800 .ctl = msm8998_ctl, 1801 .sspp_count = ARRAY_SIZE(msm8998_sspp), 1802 .sspp = msm8998_sspp, 1803 .mixer_count = ARRAY_SIZE(msm8998_lm), 1804 .mixer = msm8998_lm, 1805 .dspp_count = ARRAY_SIZE(msm8998_dspp), 1806 .dspp = msm8998_dspp, 1807 .pingpong_count = ARRAY_SIZE(sdm845_pp), 1808 .pingpong = sdm845_pp, 1809 .intf_count = ARRAY_SIZE(msm8998_intf), 1810 .intf = msm8998_intf, 1811 .vbif_count = ARRAY_SIZE(msm8998_vbif), 1812 .vbif = msm8998_vbif, 1813 .reg_dma_count = 0, 1814 .perf = &msm8998_perf_data, 1815 .mdss_irqs = IRQ_SM8250_MASK, 1816 }; 1817 1818 static const struct dpu_mdss_cfg sdm845_dpu_cfg = { 1819 .caps = &sdm845_dpu_caps, 1820 .mdp_count = ARRAY_SIZE(sdm845_mdp), 1821 .mdp = sdm845_mdp, 1822 .ctl_count = ARRAY_SIZE(sdm845_ctl), 1823 .ctl = sdm845_ctl, 1824 .sspp_count = ARRAY_SIZE(sdm845_sspp), 1825 .sspp = sdm845_sspp, 1826 .mixer_count = ARRAY_SIZE(sdm845_lm), 1827 .mixer = sdm845_lm, 1828 .pingpong_count = ARRAY_SIZE(sdm845_pp), 1829 .pingpong = sdm845_pp, 1830 .dsc_count = ARRAY_SIZE(sdm845_dsc), 1831 .dsc = sdm845_dsc, 1832 .intf_count = ARRAY_SIZE(sdm845_intf), 1833 .intf = sdm845_intf, 1834 .vbif_count = ARRAY_SIZE(sdm845_vbif), 1835 .vbif = sdm845_vbif, 1836 .reg_dma_count = 1, 1837 .dma_cfg = &sdm845_regdma, 1838 .perf = &sdm845_perf_data, 1839 .mdss_irqs = IRQ_SDM845_MASK, 1840 }; 1841 1842 static const struct dpu_mdss_cfg sc7180_dpu_cfg = { 1843 .caps = &sc7180_dpu_caps, 1844 .mdp_count = ARRAY_SIZE(sc7180_mdp), 1845 .mdp = sc7180_mdp, 1846 .ctl_count = ARRAY_SIZE(sc7180_ctl), 1847 .ctl = sc7180_ctl, 1848 .sspp_count = ARRAY_SIZE(sc7180_sspp), 1849 .sspp = sc7180_sspp, 1850 .mixer_count = ARRAY_SIZE(sc7180_lm), 1851 .mixer = sc7180_lm, 1852 .dspp_count = ARRAY_SIZE(sc7180_dspp), 1853 .dspp = sc7180_dspp, 1854 .pingpong_count = ARRAY_SIZE(sc7180_pp), 1855 .pingpong = sc7180_pp, 1856 .intf_count = ARRAY_SIZE(sc7180_intf), 1857 .intf = sc7180_intf, 1858 .wb_count = ARRAY_SIZE(sm8250_wb), 1859 .wb = sm8250_wb, 1860 .vbif_count = ARRAY_SIZE(sdm845_vbif), 1861 .vbif = sdm845_vbif, 1862 .reg_dma_count = 1, 1863 .dma_cfg = &sdm845_regdma, 1864 .perf = &sc7180_perf_data, 1865 .mdss_irqs = IRQ_SC7180_MASK, 1866 }; 1867 1868 static const struct dpu_mdss_cfg sm6115_dpu_cfg = { 1869 .caps = &sm6115_dpu_caps, 1870 .mdp_count = ARRAY_SIZE(sm6115_mdp), 1871 .mdp = sm6115_mdp, 1872 .ctl_count = ARRAY_SIZE(qcm2290_ctl), 1873 .ctl = qcm2290_ctl, 1874 .sspp_count = ARRAY_SIZE(sm6115_sspp), 1875 .sspp = sm6115_sspp, 1876 .mixer_count = ARRAY_SIZE(qcm2290_lm), 1877 .mixer = qcm2290_lm, 1878 .dspp_count = ARRAY_SIZE(qcm2290_dspp), 1879 .dspp = qcm2290_dspp, 1880 .pingpong_count = ARRAY_SIZE(qcm2290_pp), 1881 .pingpong = qcm2290_pp, 1882 .intf_count = ARRAY_SIZE(qcm2290_intf), 1883 .intf = qcm2290_intf, 1884 .vbif_count = ARRAY_SIZE(sdm845_vbif), 1885 .vbif = sdm845_vbif, 1886 .perf = &sm6115_perf_data, 1887 .mdss_irqs = IRQ_SC7180_MASK, 1888 }; 1889 1890 static const struct dpu_mdss_cfg sm8150_dpu_cfg = { 1891 .caps = &sm8150_dpu_caps, 1892 .mdp_count = ARRAY_SIZE(sdm845_mdp), 1893 .mdp = sdm845_mdp, 1894 .ctl_count = ARRAY_SIZE(sm8150_ctl), 1895 .ctl = sm8150_ctl, 1896 .sspp_count = ARRAY_SIZE(sdm845_sspp), 1897 .sspp = sdm845_sspp, 1898 .mixer_count = ARRAY_SIZE(sm8150_lm), 1899 .mixer = sm8150_lm, 1900 .dspp_count = ARRAY_SIZE(sm8150_dspp), 1901 .dspp = sm8150_dspp, 1902 .pingpong_count = ARRAY_SIZE(sm8150_pp), 1903 .pingpong = sm8150_pp, 1904 .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), 1905 .merge_3d = sm8150_merge_3d, 1906 .intf_count = ARRAY_SIZE(sm8150_intf), 1907 .intf = sm8150_intf, 1908 .vbif_count = ARRAY_SIZE(sdm845_vbif), 1909 .vbif = sdm845_vbif, 1910 .reg_dma_count = 1, 1911 .dma_cfg = &sm8150_regdma, 1912 .perf = &sm8150_perf_data, 1913 .mdss_irqs = IRQ_SDM845_MASK, 1914 }; 1915 1916 static const struct dpu_mdss_cfg sc8180x_dpu_cfg = { 1917 .caps = &sc8180x_dpu_caps, 1918 .mdp_count = ARRAY_SIZE(sc8180x_mdp), 1919 .mdp = sc8180x_mdp, 1920 .ctl_count = ARRAY_SIZE(sm8150_ctl), 1921 .ctl = sm8150_ctl, 1922 .sspp_count = ARRAY_SIZE(sdm845_sspp), 1923 .sspp = sdm845_sspp, 1924 .mixer_count = ARRAY_SIZE(sm8150_lm), 1925 .mixer = sm8150_lm, 1926 .pingpong_count = ARRAY_SIZE(sm8150_pp), 1927 .pingpong = sm8150_pp, 1928 .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), 1929 .merge_3d = sm8150_merge_3d, 1930 .intf_count = ARRAY_SIZE(sc8180x_intf), 1931 .intf = sc8180x_intf, 1932 .vbif_count = ARRAY_SIZE(sdm845_vbif), 1933 .vbif = sdm845_vbif, 1934 .reg_dma_count = 1, 1935 .dma_cfg = &sm8150_regdma, 1936 .perf = &sc8180x_perf_data, 1937 .mdss_irqs = IRQ_SC8180X_MASK, 1938 }; 1939 1940 static const struct dpu_mdss_cfg sm8250_dpu_cfg = { 1941 .caps = &sm8250_dpu_caps, 1942 .mdp_count = ARRAY_SIZE(sm8250_mdp), 1943 .mdp = sm8250_mdp, 1944 .ctl_count = ARRAY_SIZE(sm8150_ctl), 1945 .ctl = sm8150_ctl, 1946 .sspp_count = ARRAY_SIZE(sm8250_sspp), 1947 .sspp = sm8250_sspp, 1948 .mixer_count = ARRAY_SIZE(sm8150_lm), 1949 .mixer = sm8150_lm, 1950 .dspp_count = ARRAY_SIZE(sm8150_dspp), 1951 .dspp = sm8150_dspp, 1952 .pingpong_count = ARRAY_SIZE(sm8150_pp), 1953 .pingpong = sm8150_pp, 1954 .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), 1955 .merge_3d = sm8150_merge_3d, 1956 .intf_count = ARRAY_SIZE(sm8150_intf), 1957 .intf = sm8150_intf, 1958 .vbif_count = ARRAY_SIZE(sdm845_vbif), 1959 .vbif = sdm845_vbif, 1960 .wb_count = ARRAY_SIZE(sm8250_wb), 1961 .wb = sm8250_wb, 1962 .reg_dma_count = 1, 1963 .dma_cfg = &sm8250_regdma, 1964 .perf = &sm8250_perf_data, 1965 .mdss_irqs = IRQ_SM8250_MASK, 1966 }; 1967 1968 static const struct dpu_mdss_cfg sc7280_dpu_cfg = { 1969 .caps = &sc7280_dpu_caps, 1970 .mdp_count = ARRAY_SIZE(sc7280_mdp), 1971 .mdp = sc7280_mdp, 1972 .ctl_count = ARRAY_SIZE(sc7280_ctl), 1973 .ctl = sc7280_ctl, 1974 .sspp_count = ARRAY_SIZE(sc7280_sspp), 1975 .sspp = sc7280_sspp, 1976 .dspp_count = ARRAY_SIZE(sc7180_dspp), 1977 .dspp = sc7180_dspp, 1978 .mixer_count = ARRAY_SIZE(sc7280_lm), 1979 .mixer = sc7280_lm, 1980 .pingpong_count = ARRAY_SIZE(sc7280_pp), 1981 .pingpong = sc7280_pp, 1982 .intf_count = ARRAY_SIZE(sc7280_intf), 1983 .intf = sc7280_intf, 1984 .vbif_count = ARRAY_SIZE(sdm845_vbif), 1985 .vbif = sdm845_vbif, 1986 .perf = &sc7280_perf_data, 1987 .mdss_irqs = IRQ_SC7280_MASK, 1988 }; 1989 1990 static const struct dpu_mdss_cfg qcm2290_dpu_cfg = { 1991 .caps = &qcm2290_dpu_caps, 1992 .mdp_count = ARRAY_SIZE(qcm2290_mdp), 1993 .mdp = qcm2290_mdp, 1994 .ctl_count = ARRAY_SIZE(qcm2290_ctl), 1995 .ctl = qcm2290_ctl, 1996 .sspp_count = ARRAY_SIZE(qcm2290_sspp), 1997 .sspp = qcm2290_sspp, 1998 .mixer_count = ARRAY_SIZE(qcm2290_lm), 1999 .mixer = qcm2290_lm, 2000 .dspp_count = ARRAY_SIZE(qcm2290_dspp), 2001 .dspp = qcm2290_dspp, 2002 .pingpong_count = ARRAY_SIZE(qcm2290_pp), 2003 .pingpong = qcm2290_pp, 2004 .intf_count = ARRAY_SIZE(qcm2290_intf), 2005 .intf = qcm2290_intf, 2006 .vbif_count = ARRAY_SIZE(sdm845_vbif), 2007 .vbif = sdm845_vbif, 2008 .reg_dma_count = 1, 2009 .dma_cfg = &sdm845_regdma, 2010 .perf = &qcm2290_perf_data, 2011 .mdss_irqs = IRQ_SC7180_MASK, 2012 }; 2013 2014 static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { 2015 { .hw_rev = DPU_HW_VER_300, .dpu_cfg = &msm8998_dpu_cfg}, 2016 { .hw_rev = DPU_HW_VER_301, .dpu_cfg = &msm8998_dpu_cfg}, 2017 { .hw_rev = DPU_HW_VER_400, .dpu_cfg = &sdm845_dpu_cfg}, 2018 { .hw_rev = DPU_HW_VER_401, .dpu_cfg = &sdm845_dpu_cfg}, 2019 { .hw_rev = DPU_HW_VER_500, .dpu_cfg = &sm8150_dpu_cfg}, 2020 { .hw_rev = DPU_HW_VER_501, .dpu_cfg = &sm8150_dpu_cfg}, 2021 { .hw_rev = DPU_HW_VER_510, .dpu_cfg = &sc8180x_dpu_cfg}, 2022 { .hw_rev = DPU_HW_VER_600, .dpu_cfg = &sm8250_dpu_cfg}, 2023 { .hw_rev = DPU_HW_VER_620, .dpu_cfg = &sc7180_dpu_cfg}, 2024 { .hw_rev = DPU_HW_VER_630, .dpu_cfg = &sm6115_dpu_cfg}, 2025 { .hw_rev = DPU_HW_VER_650, .dpu_cfg = &qcm2290_dpu_cfg}, 2026 { .hw_rev = DPU_HW_VER_720, .dpu_cfg = &sc7280_dpu_cfg}, 2027 }; 2028 2029 const struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev) 2030 { 2031 int i; 2032 2033 for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) { 2034 if (cfg_handler[i].hw_rev == hw_rev) 2035 return cfg_handler[i].dpu_cfg; 2036 } 2037 2038 DPU_ERROR("unsupported chipset id:%X\n", hw_rev); 2039 2040 return ERR_PTR(-ENODEV); 2041 } 2042 2043