125fdd593SJeykumar Sankaran /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 225fdd593SJeykumar Sankaran * 325fdd593SJeykumar Sankaran * This program is free software; you can redistribute it and/or modify 425fdd593SJeykumar Sankaran * it under the terms of the GNU General Public License version 2 and 525fdd593SJeykumar Sankaran * only version 2 as published by the Free Software Foundation. 625fdd593SJeykumar Sankaran * 725fdd593SJeykumar Sankaran * This program is distributed in the hope that it will be useful, 825fdd593SJeykumar Sankaran * but WITHOUT ANY WARRANTY; without even the implied warranty of 925fdd593SJeykumar Sankaran * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1025fdd593SJeykumar Sankaran * GNU General Public License for more details. 1125fdd593SJeykumar Sankaran */ 1225fdd593SJeykumar Sankaran 1325fdd593SJeykumar Sankaran #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 1425fdd593SJeykumar Sankaran #include <linux/slab.h> 1525fdd593SJeykumar Sankaran #include <linux/of_address.h> 1625fdd593SJeykumar Sankaran #include <linux/platform_device.h> 1725fdd593SJeykumar Sankaran #include "dpu_hw_mdss.h" 1825fdd593SJeykumar Sankaran #include "dpu_hw_catalog.h" 1925fdd593SJeykumar Sankaran #include "dpu_hw_catalog_format.h" 2025fdd593SJeykumar Sankaran #include "dpu_kms.h" 2125fdd593SJeykumar Sankaran 2225fdd593SJeykumar Sankaran #define VIG_SDM845_MASK \ 2325fdd593SJeykumar Sankaran (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_SCALER_QSEED3) | BIT(DPU_SSPP_QOS) |\ 2425fdd593SJeykumar Sankaran BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_QOS_8LVL) |\ 2525fdd593SJeykumar Sankaran BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) 2625fdd593SJeykumar Sankaran 2725fdd593SJeykumar Sankaran #define DMA_SDM845_MASK \ 2825fdd593SJeykumar Sankaran (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ 2925fdd593SJeykumar Sankaran BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 3025fdd593SJeykumar Sankaran BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 3125fdd593SJeykumar Sankaran 3207ca1fc0SSravanthi Kollukuduru #define DMA_CURSOR_SDM845_MASK \ 3307ca1fc0SSravanthi Kollukuduru (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR)) 3407ca1fc0SSravanthi Kollukuduru 3525fdd593SJeykumar Sankaran #define MIXER_SDM845_MASK \ 3625fdd593SJeykumar Sankaran (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER)) 3725fdd593SJeykumar Sankaran 3825fdd593SJeykumar Sankaran #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER) 3925fdd593SJeykumar Sankaran 4025fdd593SJeykumar Sankaran #define PINGPONG_SDM845_SPLIT_MASK \ 4125fdd593SJeykumar Sankaran (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) 4225fdd593SJeykumar Sankaran 4325fdd593SJeykumar Sankaran #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024) 4425fdd593SJeykumar Sankaran #define DEFAULT_DPU_LINE_WIDTH 2048 4525fdd593SJeykumar Sankaran #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560 4625fdd593SJeykumar Sankaran 4725fdd593SJeykumar Sankaran #define MAX_HORZ_DECIMATION 4 4825fdd593SJeykumar Sankaran #define MAX_VERT_DECIMATION 4 4925fdd593SJeykumar Sankaran 5025fdd593SJeykumar Sankaran #define MAX_UPSCALE_RATIO 20 5125fdd593SJeykumar Sankaran #define MAX_DOWNSCALE_RATIO 4 5225fdd593SJeykumar Sankaran #define SSPP_UNITY_SCALE 1 5325fdd593SJeykumar Sankaran 5425fdd593SJeykumar Sankaran #define STRCAT(X, Y) (X Y) 5525fdd593SJeykumar Sankaran 5625fdd593SJeykumar Sankaran /************************************************************* 5725fdd593SJeykumar Sankaran * DPU sub blocks config 5825fdd593SJeykumar Sankaran *************************************************************/ 5925fdd593SJeykumar Sankaran /* DPU top level caps */ 6025fdd593SJeykumar Sankaran static const struct dpu_caps sdm845_dpu_caps = { 6125fdd593SJeykumar Sankaran .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 6225fdd593SJeykumar Sankaran .max_mixer_blendstages = 0xb, 6325fdd593SJeykumar Sankaran .qseed_type = DPU_SSPP_SCALER_QSEED3, 6425fdd593SJeykumar Sankaran .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, 6525fdd593SJeykumar Sankaran .ubwc_version = DPU_HW_UBWC_VER_20, 6625fdd593SJeykumar Sankaran .has_src_split = true, 6725fdd593SJeykumar Sankaran .has_dim_layer = true, 6825fdd593SJeykumar Sankaran .has_idle_pc = true, 6925fdd593SJeykumar Sankaran }; 7025fdd593SJeykumar Sankaran 7125fdd593SJeykumar Sankaran static struct dpu_mdp_cfg sdm845_mdp[] = { 7225fdd593SJeykumar Sankaran { 7325fdd593SJeykumar Sankaran .name = "top_0", .id = MDP_TOP, 7425fdd593SJeykumar Sankaran .base = 0x0, .len = 0x45C, 7525fdd593SJeykumar Sankaran .features = 0, 7625fdd593SJeykumar Sankaran .highest_bank_bit = 0x2, 7725fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 7825fdd593SJeykumar Sankaran .reg_off = 0x2AC, .bit_off = 0}, 7925fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_VIG1] = { 8025fdd593SJeykumar Sankaran .reg_off = 0x2B4, .bit_off = 0}, 8125fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_VIG2] = { 8225fdd593SJeykumar Sankaran .reg_off = 0x2BC, .bit_off = 0}, 8325fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_VIG3] = { 8425fdd593SJeykumar Sankaran .reg_off = 0x2C4, .bit_off = 0}, 8525fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 8625fdd593SJeykumar Sankaran .reg_off = 0x2AC, .bit_off = 8}, 8725fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_DMA1] = { 8825fdd593SJeykumar Sankaran .reg_off = 0x2B4, .bit_off = 8}, 8925fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { 9025fdd593SJeykumar Sankaran .reg_off = 0x2BC, .bit_off = 8}, 9125fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { 9225fdd593SJeykumar Sankaran .reg_off = 0x2C4, .bit_off = 8}, 9325fdd593SJeykumar Sankaran }, 9425fdd593SJeykumar Sankaran }; 9525fdd593SJeykumar Sankaran 9625fdd593SJeykumar Sankaran /************************************************************* 9725fdd593SJeykumar Sankaran * CTL sub blocks config 9825fdd593SJeykumar Sankaran *************************************************************/ 9925fdd593SJeykumar Sankaran static struct dpu_ctl_cfg sdm845_ctl[] = { 10025fdd593SJeykumar Sankaran { 10125fdd593SJeykumar Sankaran .name = "ctl_0", .id = CTL_0, 10225fdd593SJeykumar Sankaran .base = 0x1000, .len = 0xE4, 10325fdd593SJeykumar Sankaran .features = BIT(DPU_CTL_SPLIT_DISPLAY) 10425fdd593SJeykumar Sankaran }, 10525fdd593SJeykumar Sankaran { 10625fdd593SJeykumar Sankaran .name = "ctl_1", .id = CTL_1, 10725fdd593SJeykumar Sankaran .base = 0x1200, .len = 0xE4, 10825fdd593SJeykumar Sankaran .features = BIT(DPU_CTL_SPLIT_DISPLAY) 10925fdd593SJeykumar Sankaran }, 11025fdd593SJeykumar Sankaran { 11125fdd593SJeykumar Sankaran .name = "ctl_2", .id = CTL_2, 11225fdd593SJeykumar Sankaran .base = 0x1400, .len = 0xE4, 11325fdd593SJeykumar Sankaran .features = 0 11425fdd593SJeykumar Sankaran }, 11525fdd593SJeykumar Sankaran { 11625fdd593SJeykumar Sankaran .name = "ctl_3", .id = CTL_3, 11725fdd593SJeykumar Sankaran .base = 0x1600, .len = 0xE4, 11825fdd593SJeykumar Sankaran .features = 0 11925fdd593SJeykumar Sankaran }, 12025fdd593SJeykumar Sankaran { 12125fdd593SJeykumar Sankaran .name = "ctl_4", .id = CTL_4, 12225fdd593SJeykumar Sankaran .base = 0x1800, .len = 0xE4, 12325fdd593SJeykumar Sankaran .features = 0 12425fdd593SJeykumar Sankaran }, 12525fdd593SJeykumar Sankaran }; 12625fdd593SJeykumar Sankaran 12725fdd593SJeykumar Sankaran /************************************************************* 12825fdd593SJeykumar Sankaran * SSPP sub blocks config 12925fdd593SJeykumar Sankaran *************************************************************/ 13025fdd593SJeykumar Sankaran 13125fdd593SJeykumar Sankaran /* SSPP common configuration */ 13225fdd593SJeykumar Sankaran static const struct dpu_sspp_blks_common sdm845_sspp_common = { 13325fdd593SJeykumar Sankaran .maxlinewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 13425fdd593SJeykumar Sankaran .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 13525fdd593SJeykumar Sankaran .maxhdeciexp = MAX_HORZ_DECIMATION, 13625fdd593SJeykumar Sankaran .maxvdeciexp = MAX_VERT_DECIMATION, 13725fdd593SJeykumar Sankaran }; 13825fdd593SJeykumar Sankaran 13925fdd593SJeykumar Sankaran #define _VIG_SBLK(num, sdma_pri) \ 14025fdd593SJeykumar Sankaran { \ 14125fdd593SJeykumar Sankaran .common = &sdm845_sspp_common, \ 14225fdd593SJeykumar Sankaran .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 14325fdd593SJeykumar Sankaran .maxupscale = MAX_UPSCALE_RATIO, \ 14425fdd593SJeykumar Sankaran .smart_dma_priority = sdma_pri, \ 14525fdd593SJeykumar Sankaran .src_blk = {.name = STRCAT("sspp_src_", num), \ 14625fdd593SJeykumar Sankaran .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ 14725fdd593SJeykumar Sankaran .scaler_blk = {.name = STRCAT("sspp_scaler", num), \ 14825fdd593SJeykumar Sankaran .id = DPU_SSPP_SCALER_QSEED3, \ 14925fdd593SJeykumar Sankaran .base = 0xa00, .len = 0xa0,}, \ 15025fdd593SJeykumar Sankaran .csc_blk = {.name = STRCAT("sspp_csc", num), \ 15125fdd593SJeykumar Sankaran .id = DPU_SSPP_CSC_10BIT, \ 15225fdd593SJeykumar Sankaran .base = 0x1a00, .len = 0x100,}, \ 15325fdd593SJeykumar Sankaran .format_list = plane_formats_yuv, \ 154e6b63a7bSFritz Koenig .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 15525fdd593SJeykumar Sankaran .virt_format_list = plane_formats, \ 156e6b63a7bSFritz Koenig .virt_num_formats = ARRAY_SIZE(plane_formats), \ 15725fdd593SJeykumar Sankaran } 15825fdd593SJeykumar Sankaran 15925fdd593SJeykumar Sankaran #define _DMA_SBLK(num, sdma_pri) \ 16025fdd593SJeykumar Sankaran { \ 16125fdd593SJeykumar Sankaran .common = &sdm845_sspp_common, \ 16225fdd593SJeykumar Sankaran .maxdwnscale = SSPP_UNITY_SCALE, \ 16325fdd593SJeykumar Sankaran .maxupscale = SSPP_UNITY_SCALE, \ 16425fdd593SJeykumar Sankaran .smart_dma_priority = sdma_pri, \ 16525fdd593SJeykumar Sankaran .src_blk = {.name = STRCAT("sspp_src_", num), \ 16625fdd593SJeykumar Sankaran .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ 16725fdd593SJeykumar Sankaran .format_list = plane_formats, \ 168e6b63a7bSFritz Koenig .num_formats = ARRAY_SIZE(plane_formats), \ 16925fdd593SJeykumar Sankaran .virt_format_list = plane_formats, \ 170e6b63a7bSFritz Koenig .virt_num_formats = ARRAY_SIZE(plane_formats), \ 17125fdd593SJeykumar Sankaran } 17225fdd593SJeykumar Sankaran 17325fdd593SJeykumar Sankaran static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = _VIG_SBLK("0", 5); 17425fdd593SJeykumar Sankaran static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = _VIG_SBLK("1", 6); 17525fdd593SJeykumar Sankaran static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = _VIG_SBLK("2", 7); 17625fdd593SJeykumar Sankaran static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = _VIG_SBLK("3", 8); 17725fdd593SJeykumar Sankaran 17825fdd593SJeykumar Sankaran static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1); 17925fdd593SJeykumar Sankaran static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2); 18025fdd593SJeykumar Sankaran static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3); 18125fdd593SJeykumar Sankaran static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4); 18225fdd593SJeykumar Sankaran 18307ca1fc0SSravanthi Kollukuduru #define SSPP_BLK(_name, _id, _base, _features, \ 18407ca1fc0SSravanthi Kollukuduru _sblk, _xinid, _type, _clkctrl) \ 18525fdd593SJeykumar Sankaran { \ 18625fdd593SJeykumar Sankaran .name = _name, .id = _id, \ 18725fdd593SJeykumar Sankaran .base = _base, .len = 0x1c8, \ 18807ca1fc0SSravanthi Kollukuduru .features = _features, \ 18925fdd593SJeykumar Sankaran .sblk = &_sblk, \ 19025fdd593SJeykumar Sankaran .xin_id = _xinid, \ 19107ca1fc0SSravanthi Kollukuduru .type = _type, \ 19225fdd593SJeykumar Sankaran .clk_ctrl = _clkctrl \ 19325fdd593SJeykumar Sankaran } 19425fdd593SJeykumar Sankaran 19525fdd593SJeykumar Sankaran static struct dpu_sspp_cfg sdm845_sspp[] = { 19607ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK, 19707ca1fc0SSravanthi Kollukuduru sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 19807ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK, 19907ca1fc0SSravanthi Kollukuduru sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 20007ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK, 20107ca1fc0SSravanthi Kollukuduru sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 20207ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK, 20307ca1fc0SSravanthi Kollukuduru sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 20407ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, 20507ca1fc0SSravanthi Kollukuduru sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 20607ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, 20707ca1fc0SSravanthi Kollukuduru sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 20807ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, 20907ca1fc0SSravanthi Kollukuduru sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), 21007ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, 21107ca1fc0SSravanthi Kollukuduru sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), 21225fdd593SJeykumar Sankaran }; 21325fdd593SJeykumar Sankaran 21425fdd593SJeykumar Sankaran /************************************************************* 21525fdd593SJeykumar Sankaran * MIXER sub blocks config 21625fdd593SJeykumar Sankaran *************************************************************/ 21725fdd593SJeykumar Sankaran static const struct dpu_lm_sub_blks sdm845_lm_sblk = { 21825fdd593SJeykumar Sankaran .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 21925fdd593SJeykumar Sankaran .maxblendstages = 11, /* excluding base layer */ 22025fdd593SJeykumar Sankaran .blendstage_base = { /* offsets relative to mixer base */ 22125fdd593SJeykumar Sankaran 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 22225fdd593SJeykumar Sankaran 0xb0, 0xc8, 0xe0, 0xf8, 0x110 22325fdd593SJeykumar Sankaran }, 22425fdd593SJeykumar Sankaran }; 22525fdd593SJeykumar Sankaran 226b033def8SJeykumar Sankaran #define LM_BLK(_name, _id, _base, _pp, _lmpair) \ 22725fdd593SJeykumar Sankaran { \ 22825fdd593SJeykumar Sankaran .name = _name, .id = _id, \ 22925fdd593SJeykumar Sankaran .base = _base, .len = 0x320, \ 23025fdd593SJeykumar Sankaran .features = MIXER_SDM845_MASK, \ 23125fdd593SJeykumar Sankaran .sblk = &sdm845_lm_sblk, \ 23225fdd593SJeykumar Sankaran .pingpong = _pp, \ 23325fdd593SJeykumar Sankaran .lm_pair_mask = (1 << _lmpair) \ 23425fdd593SJeykumar Sankaran } 23525fdd593SJeykumar Sankaran 23625fdd593SJeykumar Sankaran static struct dpu_lm_cfg sdm845_lm[] = { 237b033def8SJeykumar Sankaran LM_BLK("lm_0", LM_0, 0x44000, PINGPONG_0, LM_1), 238b033def8SJeykumar Sankaran LM_BLK("lm_1", LM_1, 0x45000, PINGPONG_1, LM_0), 239b033def8SJeykumar Sankaran LM_BLK("lm_2", LM_2, 0x46000, PINGPONG_2, LM_5), 240b033def8SJeykumar Sankaran LM_BLK("lm_3", LM_3, 0x0, PINGPONG_MAX, 0), 241b033def8SJeykumar Sankaran LM_BLK("lm_4", LM_4, 0x0, PINGPONG_MAX, 0), 242b033def8SJeykumar Sankaran LM_BLK("lm_5", LM_5, 0x49000, PINGPONG_3, LM_2), 24325fdd593SJeykumar Sankaran }; 24425fdd593SJeykumar Sankaran 24525fdd593SJeykumar Sankaran /************************************************************* 24625fdd593SJeykumar Sankaran * PINGPONG sub blocks config 24725fdd593SJeykumar Sankaran *************************************************************/ 24825fdd593SJeykumar Sankaran static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = { 24925fdd593SJeykumar Sankaran .te2 = {.id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0, 25025fdd593SJeykumar Sankaran .version = 0x1}, 25125fdd593SJeykumar Sankaran .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0, 25225fdd593SJeykumar Sankaran .len = 0x20, .version = 0x10000}, 25325fdd593SJeykumar Sankaran }; 25425fdd593SJeykumar Sankaran 25525fdd593SJeykumar Sankaran static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = { 25625fdd593SJeykumar Sankaran .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0, 25725fdd593SJeykumar Sankaran .len = 0x20, .version = 0x10000}, 25825fdd593SJeykumar Sankaran }; 25925fdd593SJeykumar Sankaran 26025fdd593SJeykumar Sankaran #define PP_BLK_TE(_name, _id, _base) \ 26125fdd593SJeykumar Sankaran {\ 26225fdd593SJeykumar Sankaran .name = _name, .id = _id, \ 26325fdd593SJeykumar Sankaran .base = _base, .len = 0xd4, \ 26425fdd593SJeykumar Sankaran .features = PINGPONG_SDM845_SPLIT_MASK, \ 26525fdd593SJeykumar Sankaran .sblk = &sdm845_pp_sblk_te \ 26625fdd593SJeykumar Sankaran } 26725fdd593SJeykumar Sankaran #define PP_BLK(_name, _id, _base) \ 26825fdd593SJeykumar Sankaran {\ 26925fdd593SJeykumar Sankaran .name = _name, .id = _id, \ 27025fdd593SJeykumar Sankaran .base = _base, .len = 0xd4, \ 27125fdd593SJeykumar Sankaran .features = PINGPONG_SDM845_MASK, \ 27225fdd593SJeykumar Sankaran .sblk = &sdm845_pp_sblk \ 27325fdd593SJeykumar Sankaran } 27425fdd593SJeykumar Sankaran 27525fdd593SJeykumar Sankaran static struct dpu_pingpong_cfg sdm845_pp[] = { 27625fdd593SJeykumar Sankaran PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000), 27725fdd593SJeykumar Sankaran PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800), 27825fdd593SJeykumar Sankaran PP_BLK("pingpong_2", PINGPONG_2, 0x71000), 27925fdd593SJeykumar Sankaran PP_BLK("pingpong_3", PINGPONG_3, 0x71800), 28025fdd593SJeykumar Sankaran }; 28125fdd593SJeykumar Sankaran 28225fdd593SJeykumar Sankaran /************************************************************* 28325fdd593SJeykumar Sankaran * INTF sub blocks config 28425fdd593SJeykumar Sankaran *************************************************************/ 28525fdd593SJeykumar Sankaran #define INTF_BLK(_name, _id, _base, _type, _ctrl_id) \ 28625fdd593SJeykumar Sankaran {\ 28725fdd593SJeykumar Sankaran .name = _name, .id = _id, \ 28825fdd593SJeykumar Sankaran .base = _base, .len = 0x280, \ 28925fdd593SJeykumar Sankaran .type = _type, \ 29025fdd593SJeykumar Sankaran .controller_id = _ctrl_id, \ 29125fdd593SJeykumar Sankaran .prog_fetch_lines_worst_case = 24 \ 29225fdd593SJeykumar Sankaran } 29325fdd593SJeykumar Sankaran 29425fdd593SJeykumar Sankaran static struct dpu_intf_cfg sdm845_intf[] = { 29525fdd593SJeykumar Sankaran INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0), 29625fdd593SJeykumar Sankaran INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0), 29725fdd593SJeykumar Sankaran INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1), 29825fdd593SJeykumar Sankaran INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1), 29925fdd593SJeykumar Sankaran }; 30025fdd593SJeykumar Sankaran 30125fdd593SJeykumar Sankaran /************************************************************* 30225fdd593SJeykumar Sankaran * VBIF sub blocks config 30325fdd593SJeykumar Sankaran *************************************************************/ 30425fdd593SJeykumar Sankaran /* VBIF QOS remap */ 30525fdd593SJeykumar Sankaran static u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6}; 30625fdd593SJeykumar Sankaran static u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3}; 30725fdd593SJeykumar Sankaran 30825fdd593SJeykumar Sankaran static struct dpu_vbif_cfg sdm845_vbif[] = { 30925fdd593SJeykumar Sankaran { 31025fdd593SJeykumar Sankaran .name = "vbif_0", .id = VBIF_0, 31125fdd593SJeykumar Sankaran .base = 0, .len = 0x1040, 31225fdd593SJeykumar Sankaran .features = BIT(DPU_VBIF_QOS_REMAP), 31325fdd593SJeykumar Sankaran .xin_halt_timeout = 0x4000, 31425fdd593SJeykumar Sankaran .qos_rt_tbl = { 31525fdd593SJeykumar Sankaran .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), 31625fdd593SJeykumar Sankaran .priority_lvl = sdm845_rt_pri_lvl, 31725fdd593SJeykumar Sankaran }, 31825fdd593SJeykumar Sankaran .qos_nrt_tbl = { 31925fdd593SJeykumar Sankaran .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 32025fdd593SJeykumar Sankaran .priority_lvl = sdm845_nrt_pri_lvl, 32125fdd593SJeykumar Sankaran }, 32225fdd593SJeykumar Sankaran .memtype_count = 14, 32325fdd593SJeykumar Sankaran .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 32425fdd593SJeykumar Sankaran }, 32525fdd593SJeykumar Sankaran }; 32625fdd593SJeykumar Sankaran 32725fdd593SJeykumar Sankaran static struct dpu_reg_dma_cfg sdm845_regdma = { 32825fdd593SJeykumar Sankaran .base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c 32925fdd593SJeykumar Sankaran }; 33025fdd593SJeykumar Sankaran 33125fdd593SJeykumar Sankaran /************************************************************* 33225fdd593SJeykumar Sankaran * PERF data config 33325fdd593SJeykumar Sankaran *************************************************************/ 33425fdd593SJeykumar Sankaran 33525fdd593SJeykumar Sankaran /* SSPP QOS LUTs */ 33625fdd593SJeykumar Sankaran static struct dpu_qos_lut_entry sdm845_qos_linear[] = { 33725fdd593SJeykumar Sankaran {.fl = 4, .lut = 0x357}, 33825fdd593SJeykumar Sankaran {.fl = 5, .lut = 0x3357}, 33925fdd593SJeykumar Sankaran {.fl = 6, .lut = 0x23357}, 34025fdd593SJeykumar Sankaran {.fl = 7, .lut = 0x223357}, 34125fdd593SJeykumar Sankaran {.fl = 8, .lut = 0x2223357}, 34225fdd593SJeykumar Sankaran {.fl = 9, .lut = 0x22223357}, 34325fdd593SJeykumar Sankaran {.fl = 10, .lut = 0x222223357}, 34425fdd593SJeykumar Sankaran {.fl = 11, .lut = 0x2222223357}, 34525fdd593SJeykumar Sankaran {.fl = 12, .lut = 0x22222223357}, 34625fdd593SJeykumar Sankaran {.fl = 13, .lut = 0x222222223357}, 34725fdd593SJeykumar Sankaran {.fl = 14, .lut = 0x1222222223357}, 34825fdd593SJeykumar Sankaran {.fl = 0, .lut = 0x11222222223357} 34925fdd593SJeykumar Sankaran }; 35025fdd593SJeykumar Sankaran 35125fdd593SJeykumar Sankaran static struct dpu_qos_lut_entry sdm845_qos_macrotile[] = { 35225fdd593SJeykumar Sankaran {.fl = 10, .lut = 0x344556677}, 35325fdd593SJeykumar Sankaran {.fl = 11, .lut = 0x3344556677}, 35425fdd593SJeykumar Sankaran {.fl = 12, .lut = 0x23344556677}, 35525fdd593SJeykumar Sankaran {.fl = 13, .lut = 0x223344556677}, 35625fdd593SJeykumar Sankaran {.fl = 14, .lut = 0x1223344556677}, 35725fdd593SJeykumar Sankaran {.fl = 0, .lut = 0x112233344556677}, 35825fdd593SJeykumar Sankaran }; 35925fdd593SJeykumar Sankaran 36025fdd593SJeykumar Sankaran static struct dpu_qos_lut_entry sdm845_qos_nrt[] = { 36125fdd593SJeykumar Sankaran {.fl = 0, .lut = 0x0}, 36225fdd593SJeykumar Sankaran }; 36325fdd593SJeykumar Sankaran 36425fdd593SJeykumar Sankaran static struct dpu_perf_cfg sdm845_perf_data = { 36525fdd593SJeykumar Sankaran .max_bw_low = 6800000, 36625fdd593SJeykumar Sankaran .max_bw_high = 6800000, 36725fdd593SJeykumar Sankaran .min_core_ib = 2400000, 36825fdd593SJeykumar Sankaran .min_llcc_ib = 800000, 36925fdd593SJeykumar Sankaran .min_dram_ib = 800000, 37025fdd593SJeykumar Sankaran .core_ib_ff = "6.0", 37125fdd593SJeykumar Sankaran .core_clk_ff = "1.0", 37225fdd593SJeykumar Sankaran .comp_ratio_rt = 37325fdd593SJeykumar Sankaran "NV12/5/1/1.23 AB24/5/1/1.23 XB24/5/1/1.23", 37425fdd593SJeykumar Sankaran .comp_ratio_nrt = 37525fdd593SJeykumar Sankaran "NV12/5/1/1.25 AB24/5/1/1.25 XB24/5/1/1.25", 37625fdd593SJeykumar Sankaran .undersized_prefill_lines = 2, 37725fdd593SJeykumar Sankaran .xtra_prefill_lines = 2, 37825fdd593SJeykumar Sankaran .dest_scale_prefill_lines = 3, 37925fdd593SJeykumar Sankaran .macrotile_prefill_lines = 4, 38025fdd593SJeykumar Sankaran .yuv_nv12_prefill_lines = 8, 38125fdd593SJeykumar Sankaran .linear_prefill_lines = 1, 38225fdd593SJeykumar Sankaran .downscaling_prefill_lines = 1, 38325fdd593SJeykumar Sankaran .amortizable_threshold = 25, 38425fdd593SJeykumar Sankaran .min_prefill_lines = 24, 38525fdd593SJeykumar Sankaran .danger_lut_tbl = {0xf, 0xffff, 0x0}, 38625fdd593SJeykumar Sankaran .qos_lut_tbl = { 38725fdd593SJeykumar Sankaran {.nentry = ARRAY_SIZE(sdm845_qos_linear), 38825fdd593SJeykumar Sankaran .entries = sdm845_qos_linear 38925fdd593SJeykumar Sankaran }, 39025fdd593SJeykumar Sankaran {.nentry = ARRAY_SIZE(sdm845_qos_macrotile), 39125fdd593SJeykumar Sankaran .entries = sdm845_qos_macrotile 39225fdd593SJeykumar Sankaran }, 39325fdd593SJeykumar Sankaran {.nentry = ARRAY_SIZE(sdm845_qos_nrt), 39425fdd593SJeykumar Sankaran .entries = sdm845_qos_nrt 39525fdd593SJeykumar Sankaran }, 39625fdd593SJeykumar Sankaran }, 39725fdd593SJeykumar Sankaran .cdp_cfg = { 39825fdd593SJeykumar Sankaran {.rd_enable = 1, .wr_enable = 1}, 39925fdd593SJeykumar Sankaran {.rd_enable = 1, .wr_enable = 0} 40025fdd593SJeykumar Sankaran }, 40125fdd593SJeykumar Sankaran }; 40225fdd593SJeykumar Sankaran 40325fdd593SJeykumar Sankaran /************************************************************* 40425fdd593SJeykumar Sankaran * Hardware catalog init 40525fdd593SJeykumar Sankaran *************************************************************/ 40625fdd593SJeykumar Sankaran 40725fdd593SJeykumar Sankaran /* 40825fdd593SJeykumar Sankaran * sdm845_cfg_init(): populate sdm845 dpu sub-blocks reg offsets 40925fdd593SJeykumar Sankaran * and instance counts. 41025fdd593SJeykumar Sankaran */ 411fba33caeSJordan Crouse static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg) 41225fdd593SJeykumar Sankaran { 41325fdd593SJeykumar Sankaran *dpu_cfg = (struct dpu_mdss_cfg){ 41425fdd593SJeykumar Sankaran .caps = &sdm845_dpu_caps, 41525fdd593SJeykumar Sankaran .mdp_count = ARRAY_SIZE(sdm845_mdp), 41625fdd593SJeykumar Sankaran .mdp = sdm845_mdp, 41725fdd593SJeykumar Sankaran .ctl_count = ARRAY_SIZE(sdm845_ctl), 41825fdd593SJeykumar Sankaran .ctl = sdm845_ctl, 41925fdd593SJeykumar Sankaran .sspp_count = ARRAY_SIZE(sdm845_sspp), 42025fdd593SJeykumar Sankaran .sspp = sdm845_sspp, 42125fdd593SJeykumar Sankaran .mixer_count = ARRAY_SIZE(sdm845_lm), 42225fdd593SJeykumar Sankaran .mixer = sdm845_lm, 42325fdd593SJeykumar Sankaran .pingpong_count = ARRAY_SIZE(sdm845_pp), 42425fdd593SJeykumar Sankaran .pingpong = sdm845_pp, 42525fdd593SJeykumar Sankaran .intf_count = ARRAY_SIZE(sdm845_intf), 42625fdd593SJeykumar Sankaran .intf = sdm845_intf, 42725fdd593SJeykumar Sankaran .vbif_count = ARRAY_SIZE(sdm845_vbif), 42825fdd593SJeykumar Sankaran .vbif = sdm845_vbif, 42925fdd593SJeykumar Sankaran .reg_dma_count = 1, 43025fdd593SJeykumar Sankaran .dma_cfg = sdm845_regdma, 43125fdd593SJeykumar Sankaran .perf = sdm845_perf_data, 43225fdd593SJeykumar Sankaran }; 43325fdd593SJeykumar Sankaran } 43425fdd593SJeykumar Sankaran 43525fdd593SJeykumar Sankaran static struct dpu_mdss_hw_cfg_handler cfg_handler[] = { 43625fdd593SJeykumar Sankaran { .hw_rev = DPU_HW_VER_400, .cfg_init = sdm845_cfg_init}, 43725fdd593SJeykumar Sankaran { .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init}, 43825fdd593SJeykumar Sankaran }; 43925fdd593SJeykumar Sankaran 44025fdd593SJeykumar Sankaran void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg) 44125fdd593SJeykumar Sankaran { 44225fdd593SJeykumar Sankaran kfree(dpu_cfg); 44325fdd593SJeykumar Sankaran } 44425fdd593SJeykumar Sankaran 44525fdd593SJeykumar Sankaran struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev) 44625fdd593SJeykumar Sankaran { 44725fdd593SJeykumar Sankaran int i; 44825fdd593SJeykumar Sankaran struct dpu_mdss_cfg *dpu_cfg; 44925fdd593SJeykumar Sankaran 45025fdd593SJeykumar Sankaran dpu_cfg = kzalloc(sizeof(*dpu_cfg), GFP_KERNEL); 45125fdd593SJeykumar Sankaran if (!dpu_cfg) 45225fdd593SJeykumar Sankaran return ERR_PTR(-ENOMEM); 45325fdd593SJeykumar Sankaran 45425fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) { 45525fdd593SJeykumar Sankaran if (cfg_handler[i].hw_rev == hw_rev) { 45625fdd593SJeykumar Sankaran cfg_handler[i].cfg_init(dpu_cfg); 45725fdd593SJeykumar Sankaran dpu_cfg->hwversion = hw_rev; 45825fdd593SJeykumar Sankaran return dpu_cfg; 45925fdd593SJeykumar Sankaran } 46025fdd593SJeykumar Sankaran } 46125fdd593SJeykumar Sankaran 46225fdd593SJeykumar Sankaran DPU_ERROR("unsupported chipset id:%X\n", hw_rev); 46325fdd593SJeykumar Sankaran dpu_hw_catalog_deinit(dpu_cfg); 46425fdd593SJeykumar Sankaran return ERR_PTR(-ENODEV); 46525fdd593SJeykumar Sankaran } 46625fdd593SJeykumar Sankaran 467