197fb5e8dSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 225fdd593SJeykumar Sankaran /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 325fdd593SJeykumar Sankaran */ 425fdd593SJeykumar Sankaran 525fdd593SJeykumar Sankaran #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 625fdd593SJeykumar Sankaran #include <linux/slab.h> 725fdd593SJeykumar Sankaran #include <linux/of_address.h> 825fdd593SJeykumar Sankaran #include <linux/platform_device.h> 925fdd593SJeykumar Sankaran #include "dpu_hw_mdss.h" 1025fdd593SJeykumar Sankaran #include "dpu_hw_catalog.h" 1125fdd593SJeykumar Sankaran #include "dpu_hw_catalog_format.h" 1225fdd593SJeykumar Sankaran #include "dpu_kms.h" 1325fdd593SJeykumar Sankaran 147bdc0c4bSKalyan Thota #define VIG_MASK \ 157bdc0c4bSKalyan Thota (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\ 1625fdd593SJeykumar Sankaran BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_QOS_8LVL) |\ 1725fdd593SJeykumar Sankaran BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) 1825fdd593SJeykumar Sankaran 197bdc0c4bSKalyan Thota #define VIG_SDM845_MASK \ 207bdc0c4bSKalyan Thota (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3)) 217bdc0c4bSKalyan Thota 227bdc0c4bSKalyan Thota #define VIG_SC7180_MASK \ 237bdc0c4bSKalyan Thota (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED4)) 247bdc0c4bSKalyan Thota 2525fdd593SJeykumar Sankaran #define DMA_SDM845_MASK \ 2625fdd593SJeykumar Sankaran (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ 2725fdd593SJeykumar Sankaran BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 2825fdd593SJeykumar Sankaran BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 2925fdd593SJeykumar Sankaran 3007ca1fc0SSravanthi Kollukuduru #define DMA_CURSOR_SDM845_MASK \ 3107ca1fc0SSravanthi Kollukuduru (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR)) 3207ca1fc0SSravanthi Kollukuduru 3325fdd593SJeykumar Sankaran #define MIXER_SDM845_MASK \ 3425fdd593SJeykumar Sankaran (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER)) 3525fdd593SJeykumar Sankaran 367bdc0c4bSKalyan Thota #define MIXER_SC7180_MASK \ 377bdc0c4bSKalyan Thota (BIT(DPU_DIM_LAYER)) 387bdc0c4bSKalyan Thota 3925fdd593SJeykumar Sankaran #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER) 4025fdd593SJeykumar Sankaran 4125fdd593SJeykumar Sankaran #define PINGPONG_SDM845_SPLIT_MASK \ 4225fdd593SJeykumar Sankaran (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) 4325fdd593SJeykumar Sankaran 44e47616dfSKalyan Thota #define DSPP_SC7180_MASK 0 45e47616dfSKalyan Thota 4625fdd593SJeykumar Sankaran #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024) 4725fdd593SJeykumar Sankaran #define DEFAULT_DPU_LINE_WIDTH 2048 4825fdd593SJeykumar Sankaran #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560 4925fdd593SJeykumar Sankaran 5025fdd593SJeykumar Sankaran #define MAX_HORZ_DECIMATION 4 5125fdd593SJeykumar Sankaran #define MAX_VERT_DECIMATION 4 5225fdd593SJeykumar Sankaran 5325fdd593SJeykumar Sankaran #define MAX_UPSCALE_RATIO 20 5425fdd593SJeykumar Sankaran #define MAX_DOWNSCALE_RATIO 4 5525fdd593SJeykumar Sankaran #define SSPP_UNITY_SCALE 1 5625fdd593SJeykumar Sankaran 5725fdd593SJeykumar Sankaran #define STRCAT(X, Y) (X Y) 5825fdd593SJeykumar Sankaran 5925fdd593SJeykumar Sankaran /************************************************************* 6025fdd593SJeykumar Sankaran * DPU sub blocks config 6125fdd593SJeykumar Sankaran *************************************************************/ 6225fdd593SJeykumar Sankaran /* DPU top level caps */ 6325fdd593SJeykumar Sankaran static const struct dpu_caps sdm845_dpu_caps = { 6425fdd593SJeykumar Sankaran .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 6525fdd593SJeykumar Sankaran .max_mixer_blendstages = 0xb, 6625fdd593SJeykumar Sankaran .qseed_type = DPU_SSPP_SCALER_QSEED3, 6725fdd593SJeykumar Sankaran .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, 6825fdd593SJeykumar Sankaran .ubwc_version = DPU_HW_UBWC_VER_20, 6925fdd593SJeykumar Sankaran .has_src_split = true, 7025fdd593SJeykumar Sankaran .has_dim_layer = true, 7125fdd593SJeykumar Sankaran .has_idle_pc = true, 7242a558b7SKalyan Thota .has_3d_merge = true, 7325fdd593SJeykumar Sankaran }; 7425fdd593SJeykumar Sankaran 757bdc0c4bSKalyan Thota static const struct dpu_caps sc7180_dpu_caps = { 767bdc0c4bSKalyan Thota .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 777bdc0c4bSKalyan Thota .max_mixer_blendstages = 0x9, 787bdc0c4bSKalyan Thota .qseed_type = DPU_SSPP_SCALER_QSEED4, 797bdc0c4bSKalyan Thota .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, 807bdc0c4bSKalyan Thota .ubwc_version = DPU_HW_UBWC_VER_20, 817bdc0c4bSKalyan Thota .has_dim_layer = true, 827bdc0c4bSKalyan Thota .has_idle_pc = true, 837bdc0c4bSKalyan Thota }; 847bdc0c4bSKalyan Thota 85abda0d92SStephen Boyd static const struct dpu_mdp_cfg sdm845_mdp[] = { 8625fdd593SJeykumar Sankaran { 8725fdd593SJeykumar Sankaran .name = "top_0", .id = MDP_TOP, 8825fdd593SJeykumar Sankaran .base = 0x0, .len = 0x45C, 8925fdd593SJeykumar Sankaran .features = 0, 9025fdd593SJeykumar Sankaran .highest_bank_bit = 0x2, 9125fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 9225fdd593SJeykumar Sankaran .reg_off = 0x2AC, .bit_off = 0}, 9325fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_VIG1] = { 9425fdd593SJeykumar Sankaran .reg_off = 0x2B4, .bit_off = 0}, 9525fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_VIG2] = { 9625fdd593SJeykumar Sankaran .reg_off = 0x2BC, .bit_off = 0}, 9725fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_VIG3] = { 9825fdd593SJeykumar Sankaran .reg_off = 0x2C4, .bit_off = 0}, 9925fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 10025fdd593SJeykumar Sankaran .reg_off = 0x2AC, .bit_off = 8}, 10125fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_DMA1] = { 10225fdd593SJeykumar Sankaran .reg_off = 0x2B4, .bit_off = 8}, 10325fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { 10425fdd593SJeykumar Sankaran .reg_off = 0x2BC, .bit_off = 8}, 10525fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { 10625fdd593SJeykumar Sankaran .reg_off = 0x2C4, .bit_off = 8}, 10725fdd593SJeykumar Sankaran }, 10825fdd593SJeykumar Sankaran }; 10925fdd593SJeykumar Sankaran 1107bdc0c4bSKalyan Thota static const struct dpu_mdp_cfg sc7180_mdp[] = { 1117bdc0c4bSKalyan Thota { 1127bdc0c4bSKalyan Thota .name = "top_0", .id = MDP_TOP, 1137bdc0c4bSKalyan Thota .base = 0x0, .len = 0x494, 1147bdc0c4bSKalyan Thota .features = 0, 1157bdc0c4bSKalyan Thota .highest_bank_bit = 0x3, 1167bdc0c4bSKalyan Thota .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 1177bdc0c4bSKalyan Thota .reg_off = 0x2AC, .bit_off = 0}, 1187bdc0c4bSKalyan Thota .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 1197bdc0c4bSKalyan Thota .reg_off = 0x2AC, .bit_off = 8}, 1207bdc0c4bSKalyan Thota .clk_ctrls[DPU_CLK_CTRL_DMA1] = { 1217bdc0c4bSKalyan Thota .reg_off = 0x2B4, .bit_off = 8}, 1227bdc0c4bSKalyan Thota .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { 1237bdc0c4bSKalyan Thota .reg_off = 0x2BC, .bit_off = 8}, 1247bdc0c4bSKalyan Thota }, 1257bdc0c4bSKalyan Thota }; 1267bdc0c4bSKalyan Thota 12725fdd593SJeykumar Sankaran /************************************************************* 12825fdd593SJeykumar Sankaran * CTL sub blocks config 12925fdd593SJeykumar Sankaran *************************************************************/ 130abda0d92SStephen Boyd static const struct dpu_ctl_cfg sdm845_ctl[] = { 13125fdd593SJeykumar Sankaran { 13225fdd593SJeykumar Sankaran .name = "ctl_0", .id = CTL_0, 13325fdd593SJeykumar Sankaran .base = 0x1000, .len = 0xE4, 13425fdd593SJeykumar Sankaran .features = BIT(DPU_CTL_SPLIT_DISPLAY) 13525fdd593SJeykumar Sankaran }, 13625fdd593SJeykumar Sankaran { 13725fdd593SJeykumar Sankaran .name = "ctl_1", .id = CTL_1, 13825fdd593SJeykumar Sankaran .base = 0x1200, .len = 0xE4, 13925fdd593SJeykumar Sankaran .features = BIT(DPU_CTL_SPLIT_DISPLAY) 14025fdd593SJeykumar Sankaran }, 14125fdd593SJeykumar Sankaran { 14225fdd593SJeykumar Sankaran .name = "ctl_2", .id = CTL_2, 14325fdd593SJeykumar Sankaran .base = 0x1400, .len = 0xE4, 14425fdd593SJeykumar Sankaran .features = 0 14525fdd593SJeykumar Sankaran }, 14625fdd593SJeykumar Sankaran { 14725fdd593SJeykumar Sankaran .name = "ctl_3", .id = CTL_3, 14825fdd593SJeykumar Sankaran .base = 0x1600, .len = 0xE4, 14925fdd593SJeykumar Sankaran .features = 0 15025fdd593SJeykumar Sankaran }, 15125fdd593SJeykumar Sankaran { 15225fdd593SJeykumar Sankaran .name = "ctl_4", .id = CTL_4, 15325fdd593SJeykumar Sankaran .base = 0x1800, .len = 0xE4, 15425fdd593SJeykumar Sankaran .features = 0 15525fdd593SJeykumar Sankaran }, 15625fdd593SJeykumar Sankaran }; 15725fdd593SJeykumar Sankaran 1587bdc0c4bSKalyan Thota static const struct dpu_ctl_cfg sc7180_ctl[] = { 1597bdc0c4bSKalyan Thota { 1607bdc0c4bSKalyan Thota .name = "ctl_0", .id = CTL_0, 1617bdc0c4bSKalyan Thota .base = 0x1000, .len = 0xE4, 1627bdc0c4bSKalyan Thota .features = BIT(DPU_CTL_ACTIVE_CFG) 1637bdc0c4bSKalyan Thota }, 1647bdc0c4bSKalyan Thota { 1657bdc0c4bSKalyan Thota .name = "ctl_1", .id = CTL_1, 1667bdc0c4bSKalyan Thota .base = 0x1200, .len = 0xE4, 1677bdc0c4bSKalyan Thota .features = BIT(DPU_CTL_ACTIVE_CFG) 1687bdc0c4bSKalyan Thota }, 1697bdc0c4bSKalyan Thota { 1707bdc0c4bSKalyan Thota .name = "ctl_2", .id = CTL_2, 1717bdc0c4bSKalyan Thota .base = 0x1400, .len = 0xE4, 1727bdc0c4bSKalyan Thota .features = BIT(DPU_CTL_ACTIVE_CFG) 1737bdc0c4bSKalyan Thota }, 1747bdc0c4bSKalyan Thota }; 1757bdc0c4bSKalyan Thota 17625fdd593SJeykumar Sankaran /************************************************************* 17725fdd593SJeykumar Sankaran * SSPP sub blocks config 17825fdd593SJeykumar Sankaran *************************************************************/ 17925fdd593SJeykumar Sankaran 18025fdd593SJeykumar Sankaran /* SSPP common configuration */ 18125fdd593SJeykumar Sankaran static const struct dpu_sspp_blks_common sdm845_sspp_common = { 18225fdd593SJeykumar Sankaran .maxlinewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 18325fdd593SJeykumar Sankaran .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18425fdd593SJeykumar Sankaran .maxhdeciexp = MAX_HORZ_DECIMATION, 18525fdd593SJeykumar Sankaran .maxvdeciexp = MAX_VERT_DECIMATION, 18625fdd593SJeykumar Sankaran }; 18725fdd593SJeykumar Sankaran 188b75ab05aSShubhashree Dhar #define _VIG_SBLK(num, sdma_pri, qseed_ver) \ 18925fdd593SJeykumar Sankaran { \ 19025fdd593SJeykumar Sankaran .common = &sdm845_sspp_common, \ 19125fdd593SJeykumar Sankaran .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 19225fdd593SJeykumar Sankaran .maxupscale = MAX_UPSCALE_RATIO, \ 19325fdd593SJeykumar Sankaran .smart_dma_priority = sdma_pri, \ 19425fdd593SJeykumar Sankaran .src_blk = {.name = STRCAT("sspp_src_", num), \ 19525fdd593SJeykumar Sankaran .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ 19625fdd593SJeykumar Sankaran .scaler_blk = {.name = STRCAT("sspp_scaler", num), \ 197b75ab05aSShubhashree Dhar .id = qseed_ver, \ 19825fdd593SJeykumar Sankaran .base = 0xa00, .len = 0xa0,}, \ 19925fdd593SJeykumar Sankaran .csc_blk = {.name = STRCAT("sspp_csc", num), \ 20025fdd593SJeykumar Sankaran .id = DPU_SSPP_CSC_10BIT, \ 20125fdd593SJeykumar Sankaran .base = 0x1a00, .len = 0x100,}, \ 20225fdd593SJeykumar Sankaran .format_list = plane_formats_yuv, \ 203e6b63a7bSFritz Koenig .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 20425fdd593SJeykumar Sankaran .virt_format_list = plane_formats, \ 205e6b63a7bSFritz Koenig .virt_num_formats = ARRAY_SIZE(plane_formats), \ 20625fdd593SJeykumar Sankaran } 20725fdd593SJeykumar Sankaran 20825fdd593SJeykumar Sankaran #define _DMA_SBLK(num, sdma_pri) \ 20925fdd593SJeykumar Sankaran { \ 21025fdd593SJeykumar Sankaran .common = &sdm845_sspp_common, \ 21125fdd593SJeykumar Sankaran .maxdwnscale = SSPP_UNITY_SCALE, \ 21225fdd593SJeykumar Sankaran .maxupscale = SSPP_UNITY_SCALE, \ 21325fdd593SJeykumar Sankaran .smart_dma_priority = sdma_pri, \ 21425fdd593SJeykumar Sankaran .src_blk = {.name = STRCAT("sspp_src_", num), \ 21525fdd593SJeykumar Sankaran .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ 21625fdd593SJeykumar Sankaran .format_list = plane_formats, \ 217e6b63a7bSFritz Koenig .num_formats = ARRAY_SIZE(plane_formats), \ 21825fdd593SJeykumar Sankaran .virt_format_list = plane_formats, \ 219e6b63a7bSFritz Koenig .virt_num_formats = ARRAY_SIZE(plane_formats), \ 22025fdd593SJeykumar Sankaran } 22125fdd593SJeykumar Sankaran 222b75ab05aSShubhashree Dhar static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = 223b75ab05aSShubhashree Dhar _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3); 224b75ab05aSShubhashree Dhar static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = 225b75ab05aSShubhashree Dhar _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3); 226b75ab05aSShubhashree Dhar static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = 227b75ab05aSShubhashree Dhar _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3); 228b75ab05aSShubhashree Dhar static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = 229b75ab05aSShubhashree Dhar _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3); 23025fdd593SJeykumar Sankaran 23125fdd593SJeykumar Sankaran static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1); 23225fdd593SJeykumar Sankaran static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2); 23325fdd593SJeykumar Sankaran static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3); 23425fdd593SJeykumar Sankaran static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4); 23525fdd593SJeykumar Sankaran 23607ca1fc0SSravanthi Kollukuduru #define SSPP_BLK(_name, _id, _base, _features, \ 23707ca1fc0SSravanthi Kollukuduru _sblk, _xinid, _type, _clkctrl) \ 23825fdd593SJeykumar Sankaran { \ 23925fdd593SJeykumar Sankaran .name = _name, .id = _id, \ 24025fdd593SJeykumar Sankaran .base = _base, .len = 0x1c8, \ 24107ca1fc0SSravanthi Kollukuduru .features = _features, \ 24225fdd593SJeykumar Sankaran .sblk = &_sblk, \ 24325fdd593SJeykumar Sankaran .xin_id = _xinid, \ 24407ca1fc0SSravanthi Kollukuduru .type = _type, \ 24525fdd593SJeykumar Sankaran .clk_ctrl = _clkctrl \ 24625fdd593SJeykumar Sankaran } 24725fdd593SJeykumar Sankaran 248abda0d92SStephen Boyd static const struct dpu_sspp_cfg sdm845_sspp[] = { 24907ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK, 25007ca1fc0SSravanthi Kollukuduru sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 25107ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK, 25207ca1fc0SSravanthi Kollukuduru sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 25307ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK, 25407ca1fc0SSravanthi Kollukuduru sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 25507ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK, 25607ca1fc0SSravanthi Kollukuduru sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 25707ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, 25807ca1fc0SSravanthi Kollukuduru sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 25907ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, 26007ca1fc0SSravanthi Kollukuduru sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 26107ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, 26207ca1fc0SSravanthi Kollukuduru sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), 26307ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, 26407ca1fc0SSravanthi Kollukuduru sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), 26525fdd593SJeykumar Sankaran }; 26625fdd593SJeykumar Sankaran 267b75ab05aSShubhashree Dhar static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = 268b75ab05aSShubhashree Dhar _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4); 269b75ab05aSShubhashree Dhar 2707bdc0c4bSKalyan Thota static const struct dpu_sspp_cfg sc7180_sspp[] = { 2717bdc0c4bSKalyan Thota SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, 272b75ab05aSShubhashree Dhar sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 2737bdc0c4bSKalyan Thota SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, 2747bdc0c4bSKalyan Thota sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 2757bdc0c4bSKalyan Thota SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, 2767bdc0c4bSKalyan Thota sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 2777bdc0c4bSKalyan Thota SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, 2787bdc0c4bSKalyan Thota sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), 2797bdc0c4bSKalyan Thota }; 2807bdc0c4bSKalyan Thota 28125fdd593SJeykumar Sankaran /************************************************************* 28225fdd593SJeykumar Sankaran * MIXER sub blocks config 28325fdd593SJeykumar Sankaran *************************************************************/ 2847bdc0c4bSKalyan Thota 2857bdc0c4bSKalyan Thota /* SDM845 */ 2867bdc0c4bSKalyan Thota 28725fdd593SJeykumar Sankaran static const struct dpu_lm_sub_blks sdm845_lm_sblk = { 28825fdd593SJeykumar Sankaran .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 28925fdd593SJeykumar Sankaran .maxblendstages = 11, /* excluding base layer */ 29025fdd593SJeykumar Sankaran .blendstage_base = { /* offsets relative to mixer base */ 29125fdd593SJeykumar Sankaran 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 29225fdd593SJeykumar Sankaran 0xb0, 0xc8, 0xe0, 0xf8, 0x110 29325fdd593SJeykumar Sankaran }, 29425fdd593SJeykumar Sankaran }; 29525fdd593SJeykumar Sankaran 296e47616dfSKalyan Thota #define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \ 29725fdd593SJeykumar Sankaran { \ 29825fdd593SJeykumar Sankaran .name = _name, .id = _id, \ 29925fdd593SJeykumar Sankaran .base = _base, .len = 0x320, \ 3007bdc0c4bSKalyan Thota .features = _fmask, \ 3017bdc0c4bSKalyan Thota .sblk = _sblk, \ 30225fdd593SJeykumar Sankaran .pingpong = _pp, \ 303e47616dfSKalyan Thota .lm_pair_mask = (1 << _lmpair), \ 304e47616dfSKalyan Thota .dspp = _dspp \ 30525fdd593SJeykumar Sankaran } 30625fdd593SJeykumar Sankaran 307abda0d92SStephen Boyd static const struct dpu_lm_cfg sdm845_lm[] = { 3087bdc0c4bSKalyan Thota LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 309e47616dfSKalyan Thota &sdm845_lm_sblk, PINGPONG_0, LM_1, 0), 3107bdc0c4bSKalyan Thota LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, 311e47616dfSKalyan Thota &sdm845_lm_sblk, PINGPONG_1, LM_0, 0), 3127bdc0c4bSKalyan Thota LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, 313e47616dfSKalyan Thota &sdm845_lm_sblk, PINGPONG_2, LM_5, 0), 3147bdc0c4bSKalyan Thota LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK, 315e47616dfSKalyan Thota &sdm845_lm_sblk, PINGPONG_MAX, 0, 0), 3167bdc0c4bSKalyan Thota LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK, 317e47616dfSKalyan Thota &sdm845_lm_sblk, PINGPONG_MAX, 0, 0), 3187bdc0c4bSKalyan Thota LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, 319e47616dfSKalyan Thota &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), 3207bdc0c4bSKalyan Thota }; 3217bdc0c4bSKalyan Thota 3227bdc0c4bSKalyan Thota /* SC7180 */ 3237bdc0c4bSKalyan Thota 3247bdc0c4bSKalyan Thota static const struct dpu_lm_sub_blks sc7180_lm_sblk = { 3257bdc0c4bSKalyan Thota .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 3267bdc0c4bSKalyan Thota .maxblendstages = 7, /* excluding base layer */ 3277bdc0c4bSKalyan Thota .blendstage_base = { /* offsets relative to mixer base */ 3287bdc0c4bSKalyan Thota 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0 3297bdc0c4bSKalyan Thota }, 3307bdc0c4bSKalyan Thota }; 3317bdc0c4bSKalyan Thota 3327bdc0c4bSKalyan Thota static const struct dpu_lm_cfg sc7180_lm[] = { 3337bdc0c4bSKalyan Thota LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK, 334e47616dfSKalyan Thota &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0), 3357bdc0c4bSKalyan Thota LM_BLK("lm_1", LM_1, 0x45000, MIXER_SC7180_MASK, 336e47616dfSKalyan Thota &sc7180_lm_sblk, PINGPONG_1, LM_0, 0), 33725fdd593SJeykumar Sankaran }; 33825fdd593SJeykumar Sankaran 33925fdd593SJeykumar Sankaran /************************************************************* 340e47616dfSKalyan Thota * DSPP sub blocks config 341e47616dfSKalyan Thota *************************************************************/ 342e47616dfSKalyan Thota #define DSPP_BLK(_name, _id, _base) \ 343e47616dfSKalyan Thota {\ 344e47616dfSKalyan Thota .name = _name, .id = _id, \ 345e47616dfSKalyan Thota .base = _base, .len = 0x1800, \ 346e47616dfSKalyan Thota .features = DSPP_SC7180_MASK, \ 347e47616dfSKalyan Thota .sblk = NULL, \ 348e47616dfSKalyan Thota } 349e47616dfSKalyan Thota 350e47616dfSKalyan Thota static const struct dpu_dspp_cfg sc7180_dspp[] = { 351e47616dfSKalyan Thota DSPP_BLK("dspp_0", DSPP_0, 0x54000), 352e47616dfSKalyan Thota }; 353e47616dfSKalyan Thota /************************************************************* 35425fdd593SJeykumar Sankaran * PINGPONG sub blocks config 35525fdd593SJeykumar Sankaran *************************************************************/ 35625fdd593SJeykumar Sankaran static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = { 35725fdd593SJeykumar Sankaran .te2 = {.id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0, 35825fdd593SJeykumar Sankaran .version = 0x1}, 35925fdd593SJeykumar Sankaran .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0, 36025fdd593SJeykumar Sankaran .len = 0x20, .version = 0x10000}, 36125fdd593SJeykumar Sankaran }; 36225fdd593SJeykumar Sankaran 36325fdd593SJeykumar Sankaran static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = { 36425fdd593SJeykumar Sankaran .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0, 36525fdd593SJeykumar Sankaran .len = 0x20, .version = 0x10000}, 36625fdd593SJeykumar Sankaran }; 36725fdd593SJeykumar Sankaran 36825fdd593SJeykumar Sankaran #define PP_BLK_TE(_name, _id, _base) \ 36925fdd593SJeykumar Sankaran {\ 37025fdd593SJeykumar Sankaran .name = _name, .id = _id, \ 37125fdd593SJeykumar Sankaran .base = _base, .len = 0xd4, \ 37225fdd593SJeykumar Sankaran .features = PINGPONG_SDM845_SPLIT_MASK, \ 37325fdd593SJeykumar Sankaran .sblk = &sdm845_pp_sblk_te \ 37425fdd593SJeykumar Sankaran } 37525fdd593SJeykumar Sankaran #define PP_BLK(_name, _id, _base) \ 37625fdd593SJeykumar Sankaran {\ 37725fdd593SJeykumar Sankaran .name = _name, .id = _id, \ 37825fdd593SJeykumar Sankaran .base = _base, .len = 0xd4, \ 37925fdd593SJeykumar Sankaran .features = PINGPONG_SDM845_MASK, \ 38025fdd593SJeykumar Sankaran .sblk = &sdm845_pp_sblk \ 38125fdd593SJeykumar Sankaran } 38225fdd593SJeykumar Sankaran 383abda0d92SStephen Boyd static const struct dpu_pingpong_cfg sdm845_pp[] = { 38425fdd593SJeykumar Sankaran PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000), 38525fdd593SJeykumar Sankaran PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800), 38625fdd593SJeykumar Sankaran PP_BLK("pingpong_2", PINGPONG_2, 0x71000), 38725fdd593SJeykumar Sankaran PP_BLK("pingpong_3", PINGPONG_3, 0x71800), 38825fdd593SJeykumar Sankaran }; 38925fdd593SJeykumar Sankaran 3907bdc0c4bSKalyan Thota static struct dpu_pingpong_cfg sc7180_pp[] = { 3917bdc0c4bSKalyan Thota PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000), 3927bdc0c4bSKalyan Thota PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800), 3937bdc0c4bSKalyan Thota }; 3947bdc0c4bSKalyan Thota 39525fdd593SJeykumar Sankaran /************************************************************* 39625fdd593SJeykumar Sankaran * INTF sub blocks config 39725fdd593SJeykumar Sankaran *************************************************************/ 39825fdd593SJeykumar Sankaran #define INTF_BLK(_name, _id, _base, _type, _ctrl_id) \ 39925fdd593SJeykumar Sankaran {\ 40025fdd593SJeykumar Sankaran .name = _name, .id = _id, \ 40125fdd593SJeykumar Sankaran .base = _base, .len = 0x280, \ 40273bfb790SKalyan Thota .features = BIT(DPU_CTL_ACTIVE_CFG), \ 40325fdd593SJeykumar Sankaran .type = _type, \ 40425fdd593SJeykumar Sankaran .controller_id = _ctrl_id, \ 40525fdd593SJeykumar Sankaran .prog_fetch_lines_worst_case = 24 \ 40625fdd593SJeykumar Sankaran } 40725fdd593SJeykumar Sankaran 408abda0d92SStephen Boyd static const struct dpu_intf_cfg sdm845_intf[] = { 40925fdd593SJeykumar Sankaran INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0), 41025fdd593SJeykumar Sankaran INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0), 41125fdd593SJeykumar Sankaran INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1), 41225fdd593SJeykumar Sankaran INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1), 41325fdd593SJeykumar Sankaran }; 41425fdd593SJeykumar Sankaran 4157bdc0c4bSKalyan Thota static const struct dpu_intf_cfg sc7180_intf[] = { 4167bdc0c4bSKalyan Thota INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0), 4177bdc0c4bSKalyan Thota INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0), 4187bdc0c4bSKalyan Thota }; 4197bdc0c4bSKalyan Thota 42025fdd593SJeykumar Sankaran /************************************************************* 42125fdd593SJeykumar Sankaran * VBIF sub blocks config 42225fdd593SJeykumar Sankaran *************************************************************/ 42325fdd593SJeykumar Sankaran /* VBIF QOS remap */ 424abda0d92SStephen Boyd static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6}; 425abda0d92SStephen Boyd static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3}; 42625fdd593SJeykumar Sankaran 427abda0d92SStephen Boyd static const struct dpu_vbif_cfg sdm845_vbif[] = { 42825fdd593SJeykumar Sankaran { 42925fdd593SJeykumar Sankaran .name = "vbif_0", .id = VBIF_0, 43025fdd593SJeykumar Sankaran .base = 0, .len = 0x1040, 43125fdd593SJeykumar Sankaran .features = BIT(DPU_VBIF_QOS_REMAP), 43225fdd593SJeykumar Sankaran .xin_halt_timeout = 0x4000, 43325fdd593SJeykumar Sankaran .qos_rt_tbl = { 43425fdd593SJeykumar Sankaran .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), 43525fdd593SJeykumar Sankaran .priority_lvl = sdm845_rt_pri_lvl, 43625fdd593SJeykumar Sankaran }, 43725fdd593SJeykumar Sankaran .qos_nrt_tbl = { 43825fdd593SJeykumar Sankaran .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 43925fdd593SJeykumar Sankaran .priority_lvl = sdm845_nrt_pri_lvl, 44025fdd593SJeykumar Sankaran }, 44125fdd593SJeykumar Sankaran .memtype_count = 14, 44225fdd593SJeykumar Sankaran .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 44325fdd593SJeykumar Sankaran }, 44425fdd593SJeykumar Sankaran }; 44525fdd593SJeykumar Sankaran 446abda0d92SStephen Boyd static const struct dpu_reg_dma_cfg sdm845_regdma = { 44725fdd593SJeykumar Sankaran .base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c 44825fdd593SJeykumar Sankaran }; 44925fdd593SJeykumar Sankaran 45025fdd593SJeykumar Sankaran /************************************************************* 45125fdd593SJeykumar Sankaran * PERF data config 45225fdd593SJeykumar Sankaran *************************************************************/ 45325fdd593SJeykumar Sankaran 45425fdd593SJeykumar Sankaran /* SSPP QOS LUTs */ 455abda0d92SStephen Boyd static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { 45625fdd593SJeykumar Sankaran {.fl = 4, .lut = 0x357}, 45725fdd593SJeykumar Sankaran {.fl = 5, .lut = 0x3357}, 45825fdd593SJeykumar Sankaran {.fl = 6, .lut = 0x23357}, 45925fdd593SJeykumar Sankaran {.fl = 7, .lut = 0x223357}, 46025fdd593SJeykumar Sankaran {.fl = 8, .lut = 0x2223357}, 46125fdd593SJeykumar Sankaran {.fl = 9, .lut = 0x22223357}, 46225fdd593SJeykumar Sankaran {.fl = 10, .lut = 0x222223357}, 46325fdd593SJeykumar Sankaran {.fl = 11, .lut = 0x2222223357}, 46425fdd593SJeykumar Sankaran {.fl = 12, .lut = 0x22222223357}, 46525fdd593SJeykumar Sankaran {.fl = 13, .lut = 0x222222223357}, 46625fdd593SJeykumar Sankaran {.fl = 14, .lut = 0x1222222223357}, 46725fdd593SJeykumar Sankaran {.fl = 0, .lut = 0x11222222223357} 46825fdd593SJeykumar Sankaran }; 46925fdd593SJeykumar Sankaran 4707bdc0c4bSKalyan Thota static const struct dpu_qos_lut_entry sc7180_qos_linear[] = { 4717bdc0c4bSKalyan Thota {.fl = 0, .lut = 0x0011222222335777}, 4727bdc0c4bSKalyan Thota }; 4737bdc0c4bSKalyan Thota 474abda0d92SStephen Boyd static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = { 47525fdd593SJeykumar Sankaran {.fl = 10, .lut = 0x344556677}, 47625fdd593SJeykumar Sankaran {.fl = 11, .lut = 0x3344556677}, 47725fdd593SJeykumar Sankaran {.fl = 12, .lut = 0x23344556677}, 47825fdd593SJeykumar Sankaran {.fl = 13, .lut = 0x223344556677}, 47925fdd593SJeykumar Sankaran {.fl = 14, .lut = 0x1223344556677}, 48025fdd593SJeykumar Sankaran {.fl = 0, .lut = 0x112233344556677}, 48125fdd593SJeykumar Sankaran }; 48225fdd593SJeykumar Sankaran 4837bdc0c4bSKalyan Thota static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = { 4847bdc0c4bSKalyan Thota {.fl = 0, .lut = 0x0011223344556677}, 4857bdc0c4bSKalyan Thota }; 4867bdc0c4bSKalyan Thota 487abda0d92SStephen Boyd static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = { 48825fdd593SJeykumar Sankaran {.fl = 0, .lut = 0x0}, 48925fdd593SJeykumar Sankaran }; 49025fdd593SJeykumar Sankaran 4917bdc0c4bSKalyan Thota static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { 4927bdc0c4bSKalyan Thota {.fl = 0, .lut = 0x0}, 4937bdc0c4bSKalyan Thota }; 4947bdc0c4bSKalyan Thota 495abda0d92SStephen Boyd static const struct dpu_perf_cfg sdm845_perf_data = { 49625fdd593SJeykumar Sankaran .max_bw_low = 6800000, 49725fdd593SJeykumar Sankaran .max_bw_high = 6800000, 49825fdd593SJeykumar Sankaran .min_core_ib = 2400000, 49925fdd593SJeykumar Sankaran .min_llcc_ib = 800000, 50025fdd593SJeykumar Sankaran .min_dram_ib = 800000, 50125fdd593SJeykumar Sankaran .core_ib_ff = "6.0", 50225fdd593SJeykumar Sankaran .core_clk_ff = "1.0", 50325fdd593SJeykumar Sankaran .comp_ratio_rt = 50425fdd593SJeykumar Sankaran "NV12/5/1/1.23 AB24/5/1/1.23 XB24/5/1/1.23", 50525fdd593SJeykumar Sankaran .comp_ratio_nrt = 50625fdd593SJeykumar Sankaran "NV12/5/1/1.25 AB24/5/1/1.25 XB24/5/1/1.25", 50725fdd593SJeykumar Sankaran .undersized_prefill_lines = 2, 50825fdd593SJeykumar Sankaran .xtra_prefill_lines = 2, 50925fdd593SJeykumar Sankaran .dest_scale_prefill_lines = 3, 51025fdd593SJeykumar Sankaran .macrotile_prefill_lines = 4, 51125fdd593SJeykumar Sankaran .yuv_nv12_prefill_lines = 8, 51225fdd593SJeykumar Sankaran .linear_prefill_lines = 1, 51325fdd593SJeykumar Sankaran .downscaling_prefill_lines = 1, 51425fdd593SJeykumar Sankaran .amortizable_threshold = 25, 51525fdd593SJeykumar Sankaran .min_prefill_lines = 24, 51625fdd593SJeykumar Sankaran .danger_lut_tbl = {0xf, 0xffff, 0x0}, 51725fdd593SJeykumar Sankaran .qos_lut_tbl = { 51825fdd593SJeykumar Sankaran {.nentry = ARRAY_SIZE(sdm845_qos_linear), 51925fdd593SJeykumar Sankaran .entries = sdm845_qos_linear 52025fdd593SJeykumar Sankaran }, 52125fdd593SJeykumar Sankaran {.nentry = ARRAY_SIZE(sdm845_qos_macrotile), 52225fdd593SJeykumar Sankaran .entries = sdm845_qos_macrotile 52325fdd593SJeykumar Sankaran }, 52425fdd593SJeykumar Sankaran {.nentry = ARRAY_SIZE(sdm845_qos_nrt), 52525fdd593SJeykumar Sankaran .entries = sdm845_qos_nrt 52625fdd593SJeykumar Sankaran }, 52725fdd593SJeykumar Sankaran }, 52825fdd593SJeykumar Sankaran .cdp_cfg = { 52925fdd593SJeykumar Sankaran {.rd_enable = 1, .wr_enable = 1}, 53025fdd593SJeykumar Sankaran {.rd_enable = 1, .wr_enable = 0} 53125fdd593SJeykumar Sankaran }, 53225fdd593SJeykumar Sankaran }; 53325fdd593SJeykumar Sankaran 5347bdc0c4bSKalyan Thota static const struct dpu_perf_cfg sc7180_perf_data = { 5357bdc0c4bSKalyan Thota .max_bw_low = 3900000, 5367bdc0c4bSKalyan Thota .max_bw_high = 5500000, 5377bdc0c4bSKalyan Thota .min_core_ib = 2400000, 5387bdc0c4bSKalyan Thota .min_llcc_ib = 800000, 5397bdc0c4bSKalyan Thota .min_dram_ib = 800000, 5407bdc0c4bSKalyan Thota .danger_lut_tbl = {0xff, 0xffff, 0x0}, 5417bdc0c4bSKalyan Thota .qos_lut_tbl = { 5427bdc0c4bSKalyan Thota {.nentry = ARRAY_SIZE(sc7180_qos_linear), 5437bdc0c4bSKalyan Thota .entries = sc7180_qos_linear 5447bdc0c4bSKalyan Thota }, 5457bdc0c4bSKalyan Thota {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 5467bdc0c4bSKalyan Thota .entries = sc7180_qos_macrotile 5477bdc0c4bSKalyan Thota }, 5487bdc0c4bSKalyan Thota {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 5497bdc0c4bSKalyan Thota .entries = sc7180_qos_nrt 5507bdc0c4bSKalyan Thota }, 5517bdc0c4bSKalyan Thota }, 5527bdc0c4bSKalyan Thota .cdp_cfg = { 5537bdc0c4bSKalyan Thota {.rd_enable = 1, .wr_enable = 1}, 5547bdc0c4bSKalyan Thota {.rd_enable = 1, .wr_enable = 0} 5557bdc0c4bSKalyan Thota }, 5567bdc0c4bSKalyan Thota }; 5577bdc0c4bSKalyan Thota 55825fdd593SJeykumar Sankaran /************************************************************* 55925fdd593SJeykumar Sankaran * Hardware catalog init 56025fdd593SJeykumar Sankaran *************************************************************/ 56125fdd593SJeykumar Sankaran 56225fdd593SJeykumar Sankaran /* 56325fdd593SJeykumar Sankaran * sdm845_cfg_init(): populate sdm845 dpu sub-blocks reg offsets 56425fdd593SJeykumar Sankaran * and instance counts. 56525fdd593SJeykumar Sankaran */ 566fba33caeSJordan Crouse static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg) 56725fdd593SJeykumar Sankaran { 56825fdd593SJeykumar Sankaran *dpu_cfg = (struct dpu_mdss_cfg){ 56925fdd593SJeykumar Sankaran .caps = &sdm845_dpu_caps, 57025fdd593SJeykumar Sankaran .mdp_count = ARRAY_SIZE(sdm845_mdp), 57125fdd593SJeykumar Sankaran .mdp = sdm845_mdp, 57225fdd593SJeykumar Sankaran .ctl_count = ARRAY_SIZE(sdm845_ctl), 57325fdd593SJeykumar Sankaran .ctl = sdm845_ctl, 57425fdd593SJeykumar Sankaran .sspp_count = ARRAY_SIZE(sdm845_sspp), 57525fdd593SJeykumar Sankaran .sspp = sdm845_sspp, 57625fdd593SJeykumar Sankaran .mixer_count = ARRAY_SIZE(sdm845_lm), 57725fdd593SJeykumar Sankaran .mixer = sdm845_lm, 57825fdd593SJeykumar Sankaran .pingpong_count = ARRAY_SIZE(sdm845_pp), 57925fdd593SJeykumar Sankaran .pingpong = sdm845_pp, 58025fdd593SJeykumar Sankaran .intf_count = ARRAY_SIZE(sdm845_intf), 58125fdd593SJeykumar Sankaran .intf = sdm845_intf, 58225fdd593SJeykumar Sankaran .vbif_count = ARRAY_SIZE(sdm845_vbif), 58325fdd593SJeykumar Sankaran .vbif = sdm845_vbif, 58425fdd593SJeykumar Sankaran .reg_dma_count = 1, 58525fdd593SJeykumar Sankaran .dma_cfg = sdm845_regdma, 58625fdd593SJeykumar Sankaran .perf = sdm845_perf_data, 5870846cca3SShubhashree Dhar .mdss_irqs = 0x3ff, 58825fdd593SJeykumar Sankaran }; 58925fdd593SJeykumar Sankaran } 59025fdd593SJeykumar Sankaran 5917bdc0c4bSKalyan Thota /* 5927bdc0c4bSKalyan Thota * sc7180_cfg_init(): populate sc7180 dpu sub-blocks reg offsets 5937bdc0c4bSKalyan Thota * and instance counts. 5947bdc0c4bSKalyan Thota */ 5957bdc0c4bSKalyan Thota static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg) 5967bdc0c4bSKalyan Thota { 5977bdc0c4bSKalyan Thota *dpu_cfg = (struct dpu_mdss_cfg){ 5987bdc0c4bSKalyan Thota .caps = &sc7180_dpu_caps, 5997bdc0c4bSKalyan Thota .mdp_count = ARRAY_SIZE(sc7180_mdp), 6007bdc0c4bSKalyan Thota .mdp = sc7180_mdp, 6017bdc0c4bSKalyan Thota .ctl_count = ARRAY_SIZE(sc7180_ctl), 6027bdc0c4bSKalyan Thota .ctl = sc7180_ctl, 6037bdc0c4bSKalyan Thota .sspp_count = ARRAY_SIZE(sc7180_sspp), 6047bdc0c4bSKalyan Thota .sspp = sc7180_sspp, 6057bdc0c4bSKalyan Thota .mixer_count = ARRAY_SIZE(sc7180_lm), 6067bdc0c4bSKalyan Thota .mixer = sc7180_lm, 607e47616dfSKalyan Thota .dspp_count = ARRAY_SIZE(sc7180_dspp), 608e47616dfSKalyan Thota .dspp = sc7180_dspp, 6097bdc0c4bSKalyan Thota .pingpong_count = ARRAY_SIZE(sc7180_pp), 6107bdc0c4bSKalyan Thota .pingpong = sc7180_pp, 6117bdc0c4bSKalyan Thota .intf_count = ARRAY_SIZE(sc7180_intf), 6127bdc0c4bSKalyan Thota .intf = sc7180_intf, 6137bdc0c4bSKalyan Thota .vbif_count = ARRAY_SIZE(sdm845_vbif), 6147bdc0c4bSKalyan Thota .vbif = sdm845_vbif, 6157bdc0c4bSKalyan Thota .reg_dma_count = 1, 6167bdc0c4bSKalyan Thota .dma_cfg = sdm845_regdma, 6177bdc0c4bSKalyan Thota .perf = sc7180_perf_data, 6187bdc0c4bSKalyan Thota .mdss_irqs = 0x3f, 6197bdc0c4bSKalyan Thota }; 6207bdc0c4bSKalyan Thota } 6217bdc0c4bSKalyan Thota 622abda0d92SStephen Boyd static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { 62325fdd593SJeykumar Sankaran { .hw_rev = DPU_HW_VER_400, .cfg_init = sdm845_cfg_init}, 62425fdd593SJeykumar Sankaran { .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init}, 6257bdc0c4bSKalyan Thota { .hw_rev = DPU_HW_VER_620, .cfg_init = sc7180_cfg_init}, 62625fdd593SJeykumar Sankaran }; 62725fdd593SJeykumar Sankaran 62825fdd593SJeykumar Sankaran void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg) 62925fdd593SJeykumar Sankaran { 63025fdd593SJeykumar Sankaran kfree(dpu_cfg); 63125fdd593SJeykumar Sankaran } 63225fdd593SJeykumar Sankaran 63325fdd593SJeykumar Sankaran struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev) 63425fdd593SJeykumar Sankaran { 63525fdd593SJeykumar Sankaran int i; 63625fdd593SJeykumar Sankaran struct dpu_mdss_cfg *dpu_cfg; 63725fdd593SJeykumar Sankaran 63825fdd593SJeykumar Sankaran dpu_cfg = kzalloc(sizeof(*dpu_cfg), GFP_KERNEL); 63925fdd593SJeykumar Sankaran if (!dpu_cfg) 64025fdd593SJeykumar Sankaran return ERR_PTR(-ENOMEM); 64125fdd593SJeykumar Sankaran 64225fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) { 64325fdd593SJeykumar Sankaran if (cfg_handler[i].hw_rev == hw_rev) { 64425fdd593SJeykumar Sankaran cfg_handler[i].cfg_init(dpu_cfg); 64525fdd593SJeykumar Sankaran dpu_cfg->hwversion = hw_rev; 64625fdd593SJeykumar Sankaran return dpu_cfg; 64725fdd593SJeykumar Sankaran } 64825fdd593SJeykumar Sankaran } 64925fdd593SJeykumar Sankaran 65025fdd593SJeykumar Sankaran DPU_ERROR("unsupported chipset id:%X\n", hw_rev); 65125fdd593SJeykumar Sankaran dpu_hw_catalog_deinit(dpu_cfg); 65225fdd593SJeykumar Sankaran return ERR_PTR(-ENODEV); 65325fdd593SJeykumar Sankaran } 65425fdd593SJeykumar Sankaran 655