197fb5e8dSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 225fdd593SJeykumar Sankaran /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 325fdd593SJeykumar Sankaran */ 425fdd593SJeykumar Sankaran 525fdd593SJeykumar Sankaran #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 625fdd593SJeykumar Sankaran #include <linux/slab.h> 725fdd593SJeykumar Sankaran #include <linux/of_address.h> 825fdd593SJeykumar Sankaran #include <linux/platform_device.h> 925fdd593SJeykumar Sankaran #include "dpu_hw_mdss.h" 1025fdd593SJeykumar Sankaran #include "dpu_hw_catalog.h" 1125fdd593SJeykumar Sankaran #include "dpu_hw_catalog_format.h" 1225fdd593SJeykumar Sankaran #include "dpu_kms.h" 1325fdd593SJeykumar Sankaran 147bdc0c4bSKalyan Thota #define VIG_MASK \ 157bdc0c4bSKalyan Thota (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) |\ 1625fdd593SJeykumar Sankaran BIT(DPU_SSPP_CSC_10BIT) | BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_QOS_8LVL) |\ 1725fdd593SJeykumar Sankaran BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_EXCL_RECT)) 1825fdd593SJeykumar Sankaran 197bdc0c4bSKalyan Thota #define VIG_SDM845_MASK \ 207bdc0c4bSKalyan Thota (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED3)) 217bdc0c4bSKalyan Thota 227bdc0c4bSKalyan Thota #define VIG_SC7180_MASK \ 237bdc0c4bSKalyan Thota (VIG_MASK | BIT(DPU_SSPP_SCALER_QSEED4)) 247bdc0c4bSKalyan Thota 2525fdd593SJeykumar Sankaran #define DMA_SDM845_MASK \ 2625fdd593SJeykumar Sankaran (BIT(DPU_SSPP_SRC) | BIT(DPU_SSPP_QOS) | BIT(DPU_SSPP_QOS_8LVL) |\ 2725fdd593SJeykumar Sankaran BIT(DPU_SSPP_TS_PREFILL) | BIT(DPU_SSPP_TS_PREFILL_REC1) |\ 2825fdd593SJeykumar Sankaran BIT(DPU_SSPP_CDP) | BIT(DPU_SSPP_EXCL_RECT)) 2925fdd593SJeykumar Sankaran 3007ca1fc0SSravanthi Kollukuduru #define DMA_CURSOR_SDM845_MASK \ 3107ca1fc0SSravanthi Kollukuduru (DMA_SDM845_MASK | BIT(DPU_SSPP_CURSOR)) 3207ca1fc0SSravanthi Kollukuduru 3325fdd593SJeykumar Sankaran #define MIXER_SDM845_MASK \ 3425fdd593SJeykumar Sankaran (BIT(DPU_MIXER_SOURCESPLIT) | BIT(DPU_DIM_LAYER)) 3525fdd593SJeykumar Sankaran 367bdc0c4bSKalyan Thota #define MIXER_SC7180_MASK \ 377bdc0c4bSKalyan Thota (BIT(DPU_DIM_LAYER)) 387bdc0c4bSKalyan Thota 3925fdd593SJeykumar Sankaran #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER) 4025fdd593SJeykumar Sankaran 4125fdd593SJeykumar Sankaran #define PINGPONG_SDM845_SPLIT_MASK \ 4225fdd593SJeykumar Sankaran (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) 4325fdd593SJeykumar Sankaran 444259ff7aSKalyan Thota #define DSPP_SC7180_MASK BIT(DPU_DSPP_PCC) 45e47616dfSKalyan Thota 46cace3ac4SJonathan Marek #define INTF_SDM845_MASK (0) 47cace3ac4SJonathan Marek 48cace3ac4SJonathan Marek #define INTF_SC7180_MASK BIT(DPU_INTF_INPUT_CTRL) | BIT(DPU_INTF_TE) 49cace3ac4SJonathan Marek 5025fdd593SJeykumar Sankaran #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024) 5125fdd593SJeykumar Sankaran #define DEFAULT_DPU_LINE_WIDTH 2048 5225fdd593SJeykumar Sankaran #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560 5325fdd593SJeykumar Sankaran 5425fdd593SJeykumar Sankaran #define MAX_HORZ_DECIMATION 4 5525fdd593SJeykumar Sankaran #define MAX_VERT_DECIMATION 4 5625fdd593SJeykumar Sankaran 5725fdd593SJeykumar Sankaran #define MAX_UPSCALE_RATIO 20 5825fdd593SJeykumar Sankaran #define MAX_DOWNSCALE_RATIO 4 5925fdd593SJeykumar Sankaran #define SSPP_UNITY_SCALE 1 6025fdd593SJeykumar Sankaran 6125fdd593SJeykumar Sankaran #define STRCAT(X, Y) (X Y) 6225fdd593SJeykumar Sankaran 6325fdd593SJeykumar Sankaran /************************************************************* 6425fdd593SJeykumar Sankaran * DPU sub blocks config 6525fdd593SJeykumar Sankaran *************************************************************/ 6625fdd593SJeykumar Sankaran /* DPU top level caps */ 6725fdd593SJeykumar Sankaran static const struct dpu_caps sdm845_dpu_caps = { 6825fdd593SJeykumar Sankaran .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 6925fdd593SJeykumar Sankaran .max_mixer_blendstages = 0xb, 7025fdd593SJeykumar Sankaran .qseed_type = DPU_SSPP_SCALER_QSEED3, 7125fdd593SJeykumar Sankaran .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, 7225fdd593SJeykumar Sankaran .ubwc_version = DPU_HW_UBWC_VER_20, 7325fdd593SJeykumar Sankaran .has_src_split = true, 7425fdd593SJeykumar Sankaran .has_dim_layer = true, 7525fdd593SJeykumar Sankaran .has_idle_pc = true, 7642a558b7SKalyan Thota .has_3d_merge = true, 777e9d4cddSJonathan Marek .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 787e9d4cddSJonathan Marek .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 797e9d4cddSJonathan Marek .max_hdeci_exp = MAX_HORZ_DECIMATION, 807e9d4cddSJonathan Marek .max_vdeci_exp = MAX_VERT_DECIMATION, 8125fdd593SJeykumar Sankaran }; 8225fdd593SJeykumar Sankaran 837bdc0c4bSKalyan Thota static const struct dpu_caps sc7180_dpu_caps = { 847bdc0c4bSKalyan Thota .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 857bdc0c4bSKalyan Thota .max_mixer_blendstages = 0x9, 867bdc0c4bSKalyan Thota .qseed_type = DPU_SSPP_SCALER_QSEED4, 877bdc0c4bSKalyan Thota .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, 887bdc0c4bSKalyan Thota .ubwc_version = DPU_HW_UBWC_VER_20, 897bdc0c4bSKalyan Thota .has_dim_layer = true, 907bdc0c4bSKalyan Thota .has_idle_pc = true, 917e9d4cddSJonathan Marek .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 927e9d4cddSJonathan Marek .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 937bdc0c4bSKalyan Thota }; 947bdc0c4bSKalyan Thota 95386fced3SJonathan Marek static const struct dpu_caps sm8150_dpu_caps = { 96386fced3SJonathan Marek .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 97386fced3SJonathan Marek .max_mixer_blendstages = 0xb, 98386fced3SJonathan Marek .qseed_type = DPU_SSPP_SCALER_QSEED3, 99386fced3SJonathan Marek .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ 100386fced3SJonathan Marek .ubwc_version = DPU_HW_UBWC_VER_30, 101386fced3SJonathan Marek .has_src_split = true, 102386fced3SJonathan Marek .has_dim_layer = true, 103386fced3SJonathan Marek .has_idle_pc = true, 104386fced3SJonathan Marek .has_3d_merge = true, 105386fced3SJonathan Marek .max_linewidth = 4096, 106386fced3SJonathan Marek .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 107386fced3SJonathan Marek .max_hdeci_exp = MAX_HORZ_DECIMATION, 108386fced3SJonathan Marek .max_vdeci_exp = MAX_VERT_DECIMATION, 109386fced3SJonathan Marek }; 110386fced3SJonathan Marek 111af776a3eSJonathan Marek static const struct dpu_caps sm8250_dpu_caps = { 112af776a3eSJonathan Marek .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 113af776a3eSJonathan Marek .max_mixer_blendstages = 0xb, 114af776a3eSJonathan Marek .max_linewidth = 4096, 115af776a3eSJonathan Marek .qseed_type = DPU_SSPP_SCALER_QSEED3, /* TODO: qseed3 lite */ 116af776a3eSJonathan Marek .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, /* TODO: v2.5 */ 117af776a3eSJonathan Marek .ubwc_version = DPU_HW_UBWC_VER_40, 118af776a3eSJonathan Marek .has_src_split = true, 119af776a3eSJonathan Marek .has_dim_layer = true, 120af776a3eSJonathan Marek .has_idle_pc = true, 121af776a3eSJonathan Marek .has_3d_merge = true, 122af776a3eSJonathan Marek .max_linewidth = 4096, 123af776a3eSJonathan Marek .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 124af776a3eSJonathan Marek }; 125af776a3eSJonathan Marek 126abda0d92SStephen Boyd static const struct dpu_mdp_cfg sdm845_mdp[] = { 12725fdd593SJeykumar Sankaran { 12825fdd593SJeykumar Sankaran .name = "top_0", .id = MDP_TOP, 12925fdd593SJeykumar Sankaran .base = 0x0, .len = 0x45C, 13025fdd593SJeykumar Sankaran .features = 0, 13125fdd593SJeykumar Sankaran .highest_bank_bit = 0x2, 13225fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 13325fdd593SJeykumar Sankaran .reg_off = 0x2AC, .bit_off = 0}, 13425fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_VIG1] = { 13525fdd593SJeykumar Sankaran .reg_off = 0x2B4, .bit_off = 0}, 13625fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_VIG2] = { 13725fdd593SJeykumar Sankaran .reg_off = 0x2BC, .bit_off = 0}, 13825fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_VIG3] = { 13925fdd593SJeykumar Sankaran .reg_off = 0x2C4, .bit_off = 0}, 14025fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 14125fdd593SJeykumar Sankaran .reg_off = 0x2AC, .bit_off = 8}, 14225fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_DMA1] = { 14325fdd593SJeykumar Sankaran .reg_off = 0x2B4, .bit_off = 8}, 14425fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { 14525fdd593SJeykumar Sankaran .reg_off = 0x2BC, .bit_off = 8}, 14625fdd593SJeykumar Sankaran .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { 14725fdd593SJeykumar Sankaran .reg_off = 0x2C4, .bit_off = 8}, 14825fdd593SJeykumar Sankaran }, 14925fdd593SJeykumar Sankaran }; 15025fdd593SJeykumar Sankaran 1517bdc0c4bSKalyan Thota static const struct dpu_mdp_cfg sc7180_mdp[] = { 1527bdc0c4bSKalyan Thota { 1537bdc0c4bSKalyan Thota .name = "top_0", .id = MDP_TOP, 1547bdc0c4bSKalyan Thota .base = 0x0, .len = 0x494, 1557bdc0c4bSKalyan Thota .features = 0, 1567bdc0c4bSKalyan Thota .highest_bank_bit = 0x3, 1577bdc0c4bSKalyan Thota .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 1587bdc0c4bSKalyan Thota .reg_off = 0x2AC, .bit_off = 0}, 1597bdc0c4bSKalyan Thota .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 1607bdc0c4bSKalyan Thota .reg_off = 0x2AC, .bit_off = 8}, 1617bdc0c4bSKalyan Thota .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { 1627b149f2bSKalyan Thota .reg_off = 0x2B4, .bit_off = 8}, 1637b149f2bSKalyan Thota .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { 1647b149f2bSKalyan Thota .reg_off = 0x2C4, .bit_off = 8}, 1657bdc0c4bSKalyan Thota }, 1667bdc0c4bSKalyan Thota }; 1677bdc0c4bSKalyan Thota 168af776a3eSJonathan Marek static const struct dpu_mdp_cfg sm8250_mdp[] = { 169af776a3eSJonathan Marek { 170af776a3eSJonathan Marek .name = "top_0", .id = MDP_TOP, 171af776a3eSJonathan Marek .base = 0x0, .len = 0x45C, 172af776a3eSJonathan Marek .features = 0, 173af776a3eSJonathan Marek .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ 174af776a3eSJonathan Marek .clk_ctrls[DPU_CLK_CTRL_VIG0] = { 175af776a3eSJonathan Marek .reg_off = 0x2AC, .bit_off = 0}, 176af776a3eSJonathan Marek .clk_ctrls[DPU_CLK_CTRL_VIG1] = { 177af776a3eSJonathan Marek .reg_off = 0x2B4, .bit_off = 0}, 178af776a3eSJonathan Marek .clk_ctrls[DPU_CLK_CTRL_VIG2] = { 179af776a3eSJonathan Marek .reg_off = 0x2BC, .bit_off = 0}, 180af776a3eSJonathan Marek .clk_ctrls[DPU_CLK_CTRL_VIG3] = { 181af776a3eSJonathan Marek .reg_off = 0x2C4, .bit_off = 0}, 182af776a3eSJonathan Marek .clk_ctrls[DPU_CLK_CTRL_DMA0] = { 183af776a3eSJonathan Marek .reg_off = 0x2AC, .bit_off = 8}, 184af776a3eSJonathan Marek .clk_ctrls[DPU_CLK_CTRL_DMA1] = { 185af776a3eSJonathan Marek .reg_off = 0x2B4, .bit_off = 8}, 186af776a3eSJonathan Marek .clk_ctrls[DPU_CLK_CTRL_CURSOR0] = { 187af776a3eSJonathan Marek .reg_off = 0x2BC, .bit_off = 8}, 188af776a3eSJonathan Marek .clk_ctrls[DPU_CLK_CTRL_CURSOR1] = { 189af776a3eSJonathan Marek .reg_off = 0x2C4, .bit_off = 8}, 190af776a3eSJonathan Marek .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { 191af776a3eSJonathan Marek .reg_off = 0x2BC, .bit_off = 20}, 192af776a3eSJonathan Marek }, 193af776a3eSJonathan Marek }; 194af776a3eSJonathan Marek 19525fdd593SJeykumar Sankaran /************************************************************* 19625fdd593SJeykumar Sankaran * CTL sub blocks config 19725fdd593SJeykumar Sankaran *************************************************************/ 198abda0d92SStephen Boyd static const struct dpu_ctl_cfg sdm845_ctl[] = { 19925fdd593SJeykumar Sankaran { 20025fdd593SJeykumar Sankaran .name = "ctl_0", .id = CTL_0, 20125fdd593SJeykumar Sankaran .base = 0x1000, .len = 0xE4, 20225fdd593SJeykumar Sankaran .features = BIT(DPU_CTL_SPLIT_DISPLAY) 20325fdd593SJeykumar Sankaran }, 20425fdd593SJeykumar Sankaran { 20525fdd593SJeykumar Sankaran .name = "ctl_1", .id = CTL_1, 20625fdd593SJeykumar Sankaran .base = 0x1200, .len = 0xE4, 20725fdd593SJeykumar Sankaran .features = BIT(DPU_CTL_SPLIT_DISPLAY) 20825fdd593SJeykumar Sankaran }, 20925fdd593SJeykumar Sankaran { 21025fdd593SJeykumar Sankaran .name = "ctl_2", .id = CTL_2, 21125fdd593SJeykumar Sankaran .base = 0x1400, .len = 0xE4, 21225fdd593SJeykumar Sankaran .features = 0 21325fdd593SJeykumar Sankaran }, 21425fdd593SJeykumar Sankaran { 21525fdd593SJeykumar Sankaran .name = "ctl_3", .id = CTL_3, 21625fdd593SJeykumar Sankaran .base = 0x1600, .len = 0xE4, 21725fdd593SJeykumar Sankaran .features = 0 21825fdd593SJeykumar Sankaran }, 21925fdd593SJeykumar Sankaran { 22025fdd593SJeykumar Sankaran .name = "ctl_4", .id = CTL_4, 22125fdd593SJeykumar Sankaran .base = 0x1800, .len = 0xE4, 22225fdd593SJeykumar Sankaran .features = 0 22325fdd593SJeykumar Sankaran }, 22425fdd593SJeykumar Sankaran }; 22525fdd593SJeykumar Sankaran 2267bdc0c4bSKalyan Thota static const struct dpu_ctl_cfg sc7180_ctl[] = { 2277bdc0c4bSKalyan Thota { 2287bdc0c4bSKalyan Thota .name = "ctl_0", .id = CTL_0, 2297bdc0c4bSKalyan Thota .base = 0x1000, .len = 0xE4, 2307bdc0c4bSKalyan Thota .features = BIT(DPU_CTL_ACTIVE_CFG) 2317bdc0c4bSKalyan Thota }, 2327bdc0c4bSKalyan Thota { 2337bdc0c4bSKalyan Thota .name = "ctl_1", .id = CTL_1, 2347bdc0c4bSKalyan Thota .base = 0x1200, .len = 0xE4, 2357bdc0c4bSKalyan Thota .features = BIT(DPU_CTL_ACTIVE_CFG) 2367bdc0c4bSKalyan Thota }, 2377bdc0c4bSKalyan Thota { 2387bdc0c4bSKalyan Thota .name = "ctl_2", .id = CTL_2, 2397bdc0c4bSKalyan Thota .base = 0x1400, .len = 0xE4, 2407bdc0c4bSKalyan Thota .features = BIT(DPU_CTL_ACTIVE_CFG) 2417bdc0c4bSKalyan Thota }, 2427bdc0c4bSKalyan Thota }; 2437bdc0c4bSKalyan Thota 244386fced3SJonathan Marek static const struct dpu_ctl_cfg sm8150_ctl[] = { 245386fced3SJonathan Marek { 246386fced3SJonathan Marek .name = "ctl_0", .id = CTL_0, 247386fced3SJonathan Marek .base = 0x1000, .len = 0x1e0, 248386fced3SJonathan Marek .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) 249386fced3SJonathan Marek }, 250386fced3SJonathan Marek { 251386fced3SJonathan Marek .name = "ctl_1", .id = CTL_1, 252386fced3SJonathan Marek .base = 0x1200, .len = 0x1e0, 253386fced3SJonathan Marek .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) 254386fced3SJonathan Marek }, 255386fced3SJonathan Marek { 256386fced3SJonathan Marek .name = "ctl_2", .id = CTL_2, 257386fced3SJonathan Marek .base = 0x1400, .len = 0x1e0, 258386fced3SJonathan Marek .features = BIT(DPU_CTL_ACTIVE_CFG) 259386fced3SJonathan Marek }, 260386fced3SJonathan Marek { 261386fced3SJonathan Marek .name = "ctl_3", .id = CTL_3, 262386fced3SJonathan Marek .base = 0x1600, .len = 0x1e0, 263386fced3SJonathan Marek .features = BIT(DPU_CTL_ACTIVE_CFG) 264386fced3SJonathan Marek }, 265386fced3SJonathan Marek { 266386fced3SJonathan Marek .name = "ctl_4", .id = CTL_4, 267386fced3SJonathan Marek .base = 0x1800, .len = 0x1e0, 268386fced3SJonathan Marek .features = BIT(DPU_CTL_ACTIVE_CFG) 269386fced3SJonathan Marek }, 270386fced3SJonathan Marek { 271386fced3SJonathan Marek .name = "ctl_5", .id = CTL_5, 272386fced3SJonathan Marek .base = 0x1a00, .len = 0x1e0, 273386fced3SJonathan Marek .features = BIT(DPU_CTL_ACTIVE_CFG) 274386fced3SJonathan Marek }, 275386fced3SJonathan Marek }; 276386fced3SJonathan Marek 27725fdd593SJeykumar Sankaran /************************************************************* 27825fdd593SJeykumar Sankaran * SSPP sub blocks config 27925fdd593SJeykumar Sankaran *************************************************************/ 28025fdd593SJeykumar Sankaran 28125fdd593SJeykumar Sankaran /* SSPP common configuration */ 28225fdd593SJeykumar Sankaran 283b75ab05aSShubhashree Dhar #define _VIG_SBLK(num, sdma_pri, qseed_ver) \ 28425fdd593SJeykumar Sankaran { \ 28525fdd593SJeykumar Sankaran .maxdwnscale = MAX_DOWNSCALE_RATIO, \ 28625fdd593SJeykumar Sankaran .maxupscale = MAX_UPSCALE_RATIO, \ 28725fdd593SJeykumar Sankaran .smart_dma_priority = sdma_pri, \ 28825fdd593SJeykumar Sankaran .src_blk = {.name = STRCAT("sspp_src_", num), \ 28925fdd593SJeykumar Sankaran .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ 29025fdd593SJeykumar Sankaran .scaler_blk = {.name = STRCAT("sspp_scaler", num), \ 291b75ab05aSShubhashree Dhar .id = qseed_ver, \ 29225fdd593SJeykumar Sankaran .base = 0xa00, .len = 0xa0,}, \ 29325fdd593SJeykumar Sankaran .csc_blk = {.name = STRCAT("sspp_csc", num), \ 29425fdd593SJeykumar Sankaran .id = DPU_SSPP_CSC_10BIT, \ 29525fdd593SJeykumar Sankaran .base = 0x1a00, .len = 0x100,}, \ 29625fdd593SJeykumar Sankaran .format_list = plane_formats_yuv, \ 297e6b63a7bSFritz Koenig .num_formats = ARRAY_SIZE(plane_formats_yuv), \ 29825fdd593SJeykumar Sankaran .virt_format_list = plane_formats, \ 299e6b63a7bSFritz Koenig .virt_num_formats = ARRAY_SIZE(plane_formats), \ 30025fdd593SJeykumar Sankaran } 30125fdd593SJeykumar Sankaran 30225fdd593SJeykumar Sankaran #define _DMA_SBLK(num, sdma_pri) \ 30325fdd593SJeykumar Sankaran { \ 30425fdd593SJeykumar Sankaran .maxdwnscale = SSPP_UNITY_SCALE, \ 30525fdd593SJeykumar Sankaran .maxupscale = SSPP_UNITY_SCALE, \ 30625fdd593SJeykumar Sankaran .smart_dma_priority = sdma_pri, \ 30725fdd593SJeykumar Sankaran .src_blk = {.name = STRCAT("sspp_src_", num), \ 30825fdd593SJeykumar Sankaran .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ 30925fdd593SJeykumar Sankaran .format_list = plane_formats, \ 310e6b63a7bSFritz Koenig .num_formats = ARRAY_SIZE(plane_formats), \ 31125fdd593SJeykumar Sankaran .virt_format_list = plane_formats, \ 312e6b63a7bSFritz Koenig .virt_num_formats = ARRAY_SIZE(plane_formats), \ 31325fdd593SJeykumar Sankaran } 31425fdd593SJeykumar Sankaran 315b75ab05aSShubhashree Dhar static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = 316b75ab05aSShubhashree Dhar _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3); 317b75ab05aSShubhashree Dhar static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = 318b75ab05aSShubhashree Dhar _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3); 319b75ab05aSShubhashree Dhar static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = 320b75ab05aSShubhashree Dhar _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3); 321b75ab05aSShubhashree Dhar static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = 322b75ab05aSShubhashree Dhar _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3); 32325fdd593SJeykumar Sankaran 32425fdd593SJeykumar Sankaran static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1); 32525fdd593SJeykumar Sankaran static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2); 32625fdd593SJeykumar Sankaran static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3); 32725fdd593SJeykumar Sankaran static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4); 32825fdd593SJeykumar Sankaran 32907ca1fc0SSravanthi Kollukuduru #define SSPP_BLK(_name, _id, _base, _features, \ 33007ca1fc0SSravanthi Kollukuduru _sblk, _xinid, _type, _clkctrl) \ 33125fdd593SJeykumar Sankaran { \ 33225fdd593SJeykumar Sankaran .name = _name, .id = _id, \ 33325fdd593SJeykumar Sankaran .base = _base, .len = 0x1c8, \ 33407ca1fc0SSravanthi Kollukuduru .features = _features, \ 33525fdd593SJeykumar Sankaran .sblk = &_sblk, \ 33625fdd593SJeykumar Sankaran .xin_id = _xinid, \ 33707ca1fc0SSravanthi Kollukuduru .type = _type, \ 33825fdd593SJeykumar Sankaran .clk_ctrl = _clkctrl \ 33925fdd593SJeykumar Sankaran } 34025fdd593SJeykumar Sankaran 341abda0d92SStephen Boyd static const struct dpu_sspp_cfg sdm845_sspp[] = { 34207ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SDM845_MASK, 34307ca1fc0SSravanthi Kollukuduru sdm845_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 34407ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, VIG_SDM845_MASK, 34507ca1fc0SSravanthi Kollukuduru sdm845_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 34607ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, VIG_SDM845_MASK, 34707ca1fc0SSravanthi Kollukuduru sdm845_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 34807ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, VIG_SDM845_MASK, 34907ca1fc0SSravanthi Kollukuduru sdm845_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 35007ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, 35107ca1fc0SSravanthi Kollukuduru sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 35207ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_SDM845_MASK, 35307ca1fc0SSravanthi Kollukuduru sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 35407ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, 35507ca1fc0SSravanthi Kollukuduru sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), 35607ca1fc0SSravanthi Kollukuduru SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, DMA_CURSOR_SDM845_MASK, 35707ca1fc0SSravanthi Kollukuduru sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), 35825fdd593SJeykumar Sankaran }; 35925fdd593SJeykumar Sankaran 360b75ab05aSShubhashree Dhar static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = 361b75ab05aSShubhashree Dhar _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4); 362b75ab05aSShubhashree Dhar 3637bdc0c4bSKalyan Thota static const struct dpu_sspp_cfg sc7180_sspp[] = { 3647bdc0c4bSKalyan Thota SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, VIG_SC7180_MASK, 365b75ab05aSShubhashree Dhar sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 3667bdc0c4bSKalyan Thota SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, DMA_SDM845_MASK, 3677bdc0c4bSKalyan Thota sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 3687b149f2bSKalyan Thota SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, DMA_CURSOR_SDM845_MASK, 3697b149f2bSKalyan Thota sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR0), 3707bdc0c4bSKalyan Thota SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, DMA_CURSOR_SDM845_MASK, 3717b149f2bSKalyan Thota sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_CURSOR1), 3727bdc0c4bSKalyan Thota }; 3737bdc0c4bSKalyan Thota 37425fdd593SJeykumar Sankaran /************************************************************* 37525fdd593SJeykumar Sankaran * MIXER sub blocks config 37625fdd593SJeykumar Sankaran *************************************************************/ 3777bdc0c4bSKalyan Thota 3787bdc0c4bSKalyan Thota /* SDM845 */ 3797bdc0c4bSKalyan Thota 38025fdd593SJeykumar Sankaran static const struct dpu_lm_sub_blks sdm845_lm_sblk = { 38125fdd593SJeykumar Sankaran .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 38225fdd593SJeykumar Sankaran .maxblendstages = 11, /* excluding base layer */ 38325fdd593SJeykumar Sankaran .blendstage_base = { /* offsets relative to mixer base */ 38425fdd593SJeykumar Sankaran 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 38525fdd593SJeykumar Sankaran 0xb0, 0xc8, 0xe0, 0xf8, 0x110 38625fdd593SJeykumar Sankaran }, 38725fdd593SJeykumar Sankaran }; 38825fdd593SJeykumar Sankaran 389e47616dfSKalyan Thota #define LM_BLK(_name, _id, _base, _fmask, _sblk, _pp, _lmpair, _dspp) \ 39025fdd593SJeykumar Sankaran { \ 39125fdd593SJeykumar Sankaran .name = _name, .id = _id, \ 39225fdd593SJeykumar Sankaran .base = _base, .len = 0x320, \ 3937bdc0c4bSKalyan Thota .features = _fmask, \ 3947bdc0c4bSKalyan Thota .sblk = _sblk, \ 39525fdd593SJeykumar Sankaran .pingpong = _pp, \ 396e47616dfSKalyan Thota .lm_pair_mask = (1 << _lmpair), \ 397e47616dfSKalyan Thota .dspp = _dspp \ 39825fdd593SJeykumar Sankaran } 39925fdd593SJeykumar Sankaran 400abda0d92SStephen Boyd static const struct dpu_lm_cfg sdm845_lm[] = { 4017bdc0c4bSKalyan Thota LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 402e47616dfSKalyan Thota &sdm845_lm_sblk, PINGPONG_0, LM_1, 0), 4037bdc0c4bSKalyan Thota LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, 404e47616dfSKalyan Thota &sdm845_lm_sblk, PINGPONG_1, LM_0, 0), 4057bdc0c4bSKalyan Thota LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, 406e47616dfSKalyan Thota &sdm845_lm_sblk, PINGPONG_2, LM_5, 0), 4077bdc0c4bSKalyan Thota LM_BLK("lm_3", LM_3, 0x0, MIXER_SDM845_MASK, 408e47616dfSKalyan Thota &sdm845_lm_sblk, PINGPONG_MAX, 0, 0), 4097bdc0c4bSKalyan Thota LM_BLK("lm_4", LM_4, 0x0, MIXER_SDM845_MASK, 410e47616dfSKalyan Thota &sdm845_lm_sblk, PINGPONG_MAX, 0, 0), 4117bdc0c4bSKalyan Thota LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, 412e47616dfSKalyan Thota &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), 4137bdc0c4bSKalyan Thota }; 4147bdc0c4bSKalyan Thota 4157bdc0c4bSKalyan Thota /* SC7180 */ 4167bdc0c4bSKalyan Thota 4177bdc0c4bSKalyan Thota static const struct dpu_lm_sub_blks sc7180_lm_sblk = { 4187bdc0c4bSKalyan Thota .maxwidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 4197bdc0c4bSKalyan Thota .maxblendstages = 7, /* excluding base layer */ 4207bdc0c4bSKalyan Thota .blendstage_base = { /* offsets relative to mixer base */ 4217bdc0c4bSKalyan Thota 0x20, 0x38, 0x50, 0x68, 0x80, 0x98, 0xb0 4227bdc0c4bSKalyan Thota }, 4237bdc0c4bSKalyan Thota }; 4247bdc0c4bSKalyan Thota 4257bdc0c4bSKalyan Thota static const struct dpu_lm_cfg sc7180_lm[] = { 4267bdc0c4bSKalyan Thota LM_BLK("lm_0", LM_0, 0x44000, MIXER_SC7180_MASK, 427e47616dfSKalyan Thota &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0), 4287bdc0c4bSKalyan Thota LM_BLK("lm_1", LM_1, 0x45000, MIXER_SC7180_MASK, 429e47616dfSKalyan Thota &sc7180_lm_sblk, PINGPONG_1, LM_0, 0), 43025fdd593SJeykumar Sankaran }; 43125fdd593SJeykumar Sankaran 432386fced3SJonathan Marek /* SM8150 */ 433386fced3SJonathan Marek 434386fced3SJonathan Marek static const struct dpu_lm_cfg sm8150_lm[] = { 435386fced3SJonathan Marek LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 436386fced3SJonathan Marek &sdm845_lm_sblk, PINGPONG_0, LM_1, 0), 437386fced3SJonathan Marek LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, 438386fced3SJonathan Marek &sdm845_lm_sblk, PINGPONG_1, LM_0, 0), 439386fced3SJonathan Marek LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, 440386fced3SJonathan Marek &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), 441386fced3SJonathan Marek LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, 442386fced3SJonathan Marek &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), 443386fced3SJonathan Marek LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, 444386fced3SJonathan Marek &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), 445386fced3SJonathan Marek LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, 446386fced3SJonathan Marek &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), 447386fced3SJonathan Marek }; 448386fced3SJonathan Marek 44925fdd593SJeykumar Sankaran /************************************************************* 450e47616dfSKalyan Thota * DSPP sub blocks config 451e47616dfSKalyan Thota *************************************************************/ 4524259ff7aSKalyan Thota static const struct dpu_dspp_sub_blks sc7180_dspp_sblk = { 4534259ff7aSKalyan Thota .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, 4544259ff7aSKalyan Thota .len = 0x90, .version = 0x10000}, 4554259ff7aSKalyan Thota }; 4564259ff7aSKalyan Thota 457e47616dfSKalyan Thota #define DSPP_BLK(_name, _id, _base) \ 458e47616dfSKalyan Thota {\ 459e47616dfSKalyan Thota .name = _name, .id = _id, \ 460e47616dfSKalyan Thota .base = _base, .len = 0x1800, \ 461e47616dfSKalyan Thota .features = DSPP_SC7180_MASK, \ 4624259ff7aSKalyan Thota .sblk = &sc7180_dspp_sblk \ 463e47616dfSKalyan Thota } 464e47616dfSKalyan Thota 465e47616dfSKalyan Thota static const struct dpu_dspp_cfg sc7180_dspp[] = { 466e47616dfSKalyan Thota DSPP_BLK("dspp_0", DSPP_0, 0x54000), 467e47616dfSKalyan Thota }; 468386fced3SJonathan Marek 469e47616dfSKalyan Thota /************************************************************* 47025fdd593SJeykumar Sankaran * PINGPONG sub blocks config 47125fdd593SJeykumar Sankaran *************************************************************/ 47225fdd593SJeykumar Sankaran static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = { 47325fdd593SJeykumar Sankaran .te2 = {.id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0, 47425fdd593SJeykumar Sankaran .version = 0x1}, 47525fdd593SJeykumar Sankaran .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0, 47625fdd593SJeykumar Sankaran .len = 0x20, .version = 0x10000}, 47725fdd593SJeykumar Sankaran }; 47825fdd593SJeykumar Sankaran 47925fdd593SJeykumar Sankaran static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = { 48025fdd593SJeykumar Sankaran .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0, 48125fdd593SJeykumar Sankaran .len = 0x20, .version = 0x10000}, 48225fdd593SJeykumar Sankaran }; 48325fdd593SJeykumar Sankaran 48425fdd593SJeykumar Sankaran #define PP_BLK_TE(_name, _id, _base) \ 48525fdd593SJeykumar Sankaran {\ 48625fdd593SJeykumar Sankaran .name = _name, .id = _id, \ 48725fdd593SJeykumar Sankaran .base = _base, .len = 0xd4, \ 48825fdd593SJeykumar Sankaran .features = PINGPONG_SDM845_SPLIT_MASK, \ 48925fdd593SJeykumar Sankaran .sblk = &sdm845_pp_sblk_te \ 49025fdd593SJeykumar Sankaran } 49125fdd593SJeykumar Sankaran #define PP_BLK(_name, _id, _base) \ 49225fdd593SJeykumar Sankaran {\ 49325fdd593SJeykumar Sankaran .name = _name, .id = _id, \ 49425fdd593SJeykumar Sankaran .base = _base, .len = 0xd4, \ 49525fdd593SJeykumar Sankaran .features = PINGPONG_SDM845_MASK, \ 49625fdd593SJeykumar Sankaran .sblk = &sdm845_pp_sblk \ 49725fdd593SJeykumar Sankaran } 49825fdd593SJeykumar Sankaran 499abda0d92SStephen Boyd static const struct dpu_pingpong_cfg sdm845_pp[] = { 50025fdd593SJeykumar Sankaran PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000), 50125fdd593SJeykumar Sankaran PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800), 50225fdd593SJeykumar Sankaran PP_BLK("pingpong_2", PINGPONG_2, 0x71000), 50325fdd593SJeykumar Sankaran PP_BLK("pingpong_3", PINGPONG_3, 0x71800), 50425fdd593SJeykumar Sankaran }; 50525fdd593SJeykumar Sankaran 5067bdc0c4bSKalyan Thota static struct dpu_pingpong_cfg sc7180_pp[] = { 5077bdc0c4bSKalyan Thota PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000), 5087bdc0c4bSKalyan Thota PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800), 5097bdc0c4bSKalyan Thota }; 5107bdc0c4bSKalyan Thota 511386fced3SJonathan Marek static const struct dpu_pingpong_cfg sm8150_pp[] = { 512386fced3SJonathan Marek PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000), 513386fced3SJonathan Marek PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800), 514386fced3SJonathan Marek PP_BLK("pingpong_2", PINGPONG_2, 0x71000), 515386fced3SJonathan Marek PP_BLK("pingpong_3", PINGPONG_3, 0x71800), 516386fced3SJonathan Marek PP_BLK("pingpong_4", PINGPONG_4, 0x72000), 517386fced3SJonathan Marek PP_BLK("pingpong_5", PINGPONG_5, 0x72800), 518386fced3SJonathan Marek }; 519386fced3SJonathan Marek 52025fdd593SJeykumar Sankaran /************************************************************* 52125fdd593SJeykumar Sankaran * INTF sub blocks config 52225fdd593SJeykumar Sankaran *************************************************************/ 523cace3ac4SJonathan Marek #define INTF_BLK(_name, _id, _base, _type, _ctrl_id, _features) \ 52425fdd593SJeykumar Sankaran {\ 52525fdd593SJeykumar Sankaran .name = _name, .id = _id, \ 52625fdd593SJeykumar Sankaran .base = _base, .len = 0x280, \ 527cace3ac4SJonathan Marek .features = _features, \ 52825fdd593SJeykumar Sankaran .type = _type, \ 52925fdd593SJeykumar Sankaran .controller_id = _ctrl_id, \ 53025fdd593SJeykumar Sankaran .prog_fetch_lines_worst_case = 24 \ 53125fdd593SJeykumar Sankaran } 53225fdd593SJeykumar Sankaran 533abda0d92SStephen Boyd static const struct dpu_intf_cfg sdm845_intf[] = { 534cace3ac4SJonathan Marek INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, INTF_SDM845_MASK), 535cace3ac4SJonathan Marek INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, INTF_SDM845_MASK), 536cace3ac4SJonathan Marek INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, INTF_SDM845_MASK), 537cace3ac4SJonathan Marek INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, INTF_SDM845_MASK), 53825fdd593SJeykumar Sankaran }; 53925fdd593SJeykumar Sankaran 5407bdc0c4bSKalyan Thota static const struct dpu_intf_cfg sc7180_intf[] = { 541cace3ac4SJonathan Marek INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, INTF_SC7180_MASK), 542cace3ac4SJonathan Marek INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, INTF_SC7180_MASK), 5437bdc0c4bSKalyan Thota }; 5447bdc0c4bSKalyan Thota 545386fced3SJonathan Marek static const struct dpu_intf_cfg sm8150_intf[] = { 546386fced3SJonathan Marek INTF_BLK("intf_0", INTF_0, 0x6A000, INTF_DP, 0, INTF_SC7180_MASK), 547386fced3SJonathan Marek INTF_BLK("intf_1", INTF_1, 0x6A800, INTF_DSI, 0, INTF_SC7180_MASK), 548386fced3SJonathan Marek INTF_BLK("intf_2", INTF_2, 0x6B000, INTF_DSI, 1, INTF_SC7180_MASK), 549386fced3SJonathan Marek INTF_BLK("intf_3", INTF_3, 0x6B800, INTF_DP, 1, INTF_SC7180_MASK), 550386fced3SJonathan Marek }; 551386fced3SJonathan Marek 55225fdd593SJeykumar Sankaran /************************************************************* 55325fdd593SJeykumar Sankaran * VBIF sub blocks config 55425fdd593SJeykumar Sankaran *************************************************************/ 55525fdd593SJeykumar Sankaran /* VBIF QOS remap */ 556abda0d92SStephen Boyd static const u32 sdm845_rt_pri_lvl[] = {3, 3, 4, 4, 5, 5, 6, 6}; 557abda0d92SStephen Boyd static const u32 sdm845_nrt_pri_lvl[] = {3, 3, 3, 3, 3, 3, 3, 3}; 55825fdd593SJeykumar Sankaran 559abda0d92SStephen Boyd static const struct dpu_vbif_cfg sdm845_vbif[] = { 56025fdd593SJeykumar Sankaran { 56125fdd593SJeykumar Sankaran .name = "vbif_0", .id = VBIF_0, 56225fdd593SJeykumar Sankaran .base = 0, .len = 0x1040, 56325fdd593SJeykumar Sankaran .features = BIT(DPU_VBIF_QOS_REMAP), 56425fdd593SJeykumar Sankaran .xin_halt_timeout = 0x4000, 56525fdd593SJeykumar Sankaran .qos_rt_tbl = { 56625fdd593SJeykumar Sankaran .npriority_lvl = ARRAY_SIZE(sdm845_rt_pri_lvl), 56725fdd593SJeykumar Sankaran .priority_lvl = sdm845_rt_pri_lvl, 56825fdd593SJeykumar Sankaran }, 56925fdd593SJeykumar Sankaran .qos_nrt_tbl = { 57025fdd593SJeykumar Sankaran .npriority_lvl = ARRAY_SIZE(sdm845_nrt_pri_lvl), 57125fdd593SJeykumar Sankaran .priority_lvl = sdm845_nrt_pri_lvl, 57225fdd593SJeykumar Sankaran }, 57325fdd593SJeykumar Sankaran .memtype_count = 14, 57425fdd593SJeykumar Sankaran .memtype = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3}, 57525fdd593SJeykumar Sankaran }, 57625fdd593SJeykumar Sankaran }; 57725fdd593SJeykumar Sankaran 578abda0d92SStephen Boyd static const struct dpu_reg_dma_cfg sdm845_regdma = { 57925fdd593SJeykumar Sankaran .base = 0x0, .version = 0x1, .trigger_sel_off = 0x119c 58025fdd593SJeykumar Sankaran }; 58125fdd593SJeykumar Sankaran 582386fced3SJonathan Marek static const struct dpu_reg_dma_cfg sm8150_regdma = { 583386fced3SJonathan Marek .base = 0x0, .version = 0x00010001, .trigger_sel_off = 0x119c 584386fced3SJonathan Marek }; 585386fced3SJonathan Marek 586af776a3eSJonathan Marek static const struct dpu_reg_dma_cfg sm8250_regdma = { 587af776a3eSJonathan Marek .base = 0x0, 588af776a3eSJonathan Marek .version = 0x00010002, 589af776a3eSJonathan Marek .trigger_sel_off = 0x119c, 590af776a3eSJonathan Marek .xin_id = 7, 591af776a3eSJonathan Marek .clk_ctrl = DPU_CLK_CTRL_REG_DMA, 592af776a3eSJonathan Marek }; 593af776a3eSJonathan Marek 59425fdd593SJeykumar Sankaran /************************************************************* 59525fdd593SJeykumar Sankaran * PERF data config 59625fdd593SJeykumar Sankaran *************************************************************/ 59725fdd593SJeykumar Sankaran 59825fdd593SJeykumar Sankaran /* SSPP QOS LUTs */ 599abda0d92SStephen Boyd static const struct dpu_qos_lut_entry sdm845_qos_linear[] = { 60025fdd593SJeykumar Sankaran {.fl = 4, .lut = 0x357}, 60125fdd593SJeykumar Sankaran {.fl = 5, .lut = 0x3357}, 60225fdd593SJeykumar Sankaran {.fl = 6, .lut = 0x23357}, 60325fdd593SJeykumar Sankaran {.fl = 7, .lut = 0x223357}, 60425fdd593SJeykumar Sankaran {.fl = 8, .lut = 0x2223357}, 60525fdd593SJeykumar Sankaran {.fl = 9, .lut = 0x22223357}, 60625fdd593SJeykumar Sankaran {.fl = 10, .lut = 0x222223357}, 60725fdd593SJeykumar Sankaran {.fl = 11, .lut = 0x2222223357}, 60825fdd593SJeykumar Sankaran {.fl = 12, .lut = 0x22222223357}, 60925fdd593SJeykumar Sankaran {.fl = 13, .lut = 0x222222223357}, 61025fdd593SJeykumar Sankaran {.fl = 14, .lut = 0x1222222223357}, 61125fdd593SJeykumar Sankaran {.fl = 0, .lut = 0x11222222223357} 61225fdd593SJeykumar Sankaran }; 61325fdd593SJeykumar Sankaran 6147bdc0c4bSKalyan Thota static const struct dpu_qos_lut_entry sc7180_qos_linear[] = { 6157bdc0c4bSKalyan Thota {.fl = 0, .lut = 0x0011222222335777}, 6167bdc0c4bSKalyan Thota }; 6177bdc0c4bSKalyan Thota 618386fced3SJonathan Marek static const struct dpu_qos_lut_entry sm8150_qos_linear[] = { 619386fced3SJonathan Marek {.fl = 0, .lut = 0x0011222222223357 }, 620386fced3SJonathan Marek }; 621386fced3SJonathan Marek 622abda0d92SStephen Boyd static const struct dpu_qos_lut_entry sdm845_qos_macrotile[] = { 62325fdd593SJeykumar Sankaran {.fl = 10, .lut = 0x344556677}, 62425fdd593SJeykumar Sankaran {.fl = 11, .lut = 0x3344556677}, 62525fdd593SJeykumar Sankaran {.fl = 12, .lut = 0x23344556677}, 62625fdd593SJeykumar Sankaran {.fl = 13, .lut = 0x223344556677}, 62725fdd593SJeykumar Sankaran {.fl = 14, .lut = 0x1223344556677}, 62825fdd593SJeykumar Sankaran {.fl = 0, .lut = 0x112233344556677}, 62925fdd593SJeykumar Sankaran }; 63025fdd593SJeykumar Sankaran 6317bdc0c4bSKalyan Thota static const struct dpu_qos_lut_entry sc7180_qos_macrotile[] = { 6327bdc0c4bSKalyan Thota {.fl = 0, .lut = 0x0011223344556677}, 6337bdc0c4bSKalyan Thota }; 6347bdc0c4bSKalyan Thota 635abda0d92SStephen Boyd static const struct dpu_qos_lut_entry sdm845_qos_nrt[] = { 63625fdd593SJeykumar Sankaran {.fl = 0, .lut = 0x0}, 63725fdd593SJeykumar Sankaran }; 63825fdd593SJeykumar Sankaran 6397bdc0c4bSKalyan Thota static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { 6407bdc0c4bSKalyan Thota {.fl = 0, .lut = 0x0}, 6417bdc0c4bSKalyan Thota }; 6427bdc0c4bSKalyan Thota 643abda0d92SStephen Boyd static const struct dpu_perf_cfg sdm845_perf_data = { 64425fdd593SJeykumar Sankaran .max_bw_low = 6800000, 64525fdd593SJeykumar Sankaran .max_bw_high = 6800000, 64625fdd593SJeykumar Sankaran .min_core_ib = 2400000, 64725fdd593SJeykumar Sankaran .min_llcc_ib = 800000, 64825fdd593SJeykumar Sankaran .min_dram_ib = 800000, 64925fdd593SJeykumar Sankaran .core_ib_ff = "6.0", 65025fdd593SJeykumar Sankaran .core_clk_ff = "1.0", 65125fdd593SJeykumar Sankaran .comp_ratio_rt = 65225fdd593SJeykumar Sankaran "NV12/5/1/1.23 AB24/5/1/1.23 XB24/5/1/1.23", 65325fdd593SJeykumar Sankaran .comp_ratio_nrt = 65425fdd593SJeykumar Sankaran "NV12/5/1/1.25 AB24/5/1/1.25 XB24/5/1/1.25", 65525fdd593SJeykumar Sankaran .undersized_prefill_lines = 2, 65625fdd593SJeykumar Sankaran .xtra_prefill_lines = 2, 65725fdd593SJeykumar Sankaran .dest_scale_prefill_lines = 3, 65825fdd593SJeykumar Sankaran .macrotile_prefill_lines = 4, 65925fdd593SJeykumar Sankaran .yuv_nv12_prefill_lines = 8, 66025fdd593SJeykumar Sankaran .linear_prefill_lines = 1, 66125fdd593SJeykumar Sankaran .downscaling_prefill_lines = 1, 66225fdd593SJeykumar Sankaran .amortizable_threshold = 25, 66325fdd593SJeykumar Sankaran .min_prefill_lines = 24, 66425fdd593SJeykumar Sankaran .danger_lut_tbl = {0xf, 0xffff, 0x0}, 66525fdd593SJeykumar Sankaran .qos_lut_tbl = { 66625fdd593SJeykumar Sankaran {.nentry = ARRAY_SIZE(sdm845_qos_linear), 66725fdd593SJeykumar Sankaran .entries = sdm845_qos_linear 66825fdd593SJeykumar Sankaran }, 66925fdd593SJeykumar Sankaran {.nentry = ARRAY_SIZE(sdm845_qos_macrotile), 67025fdd593SJeykumar Sankaran .entries = sdm845_qos_macrotile 67125fdd593SJeykumar Sankaran }, 67225fdd593SJeykumar Sankaran {.nentry = ARRAY_SIZE(sdm845_qos_nrt), 67325fdd593SJeykumar Sankaran .entries = sdm845_qos_nrt 67425fdd593SJeykumar Sankaran }, 67525fdd593SJeykumar Sankaran }, 67625fdd593SJeykumar Sankaran .cdp_cfg = { 67725fdd593SJeykumar Sankaran {.rd_enable = 1, .wr_enable = 1}, 67825fdd593SJeykumar Sankaran {.rd_enable = 1, .wr_enable = 0} 67925fdd593SJeykumar Sankaran }, 68025fdd593SJeykumar Sankaran }; 68125fdd593SJeykumar Sankaran 6827bdc0c4bSKalyan Thota static const struct dpu_perf_cfg sc7180_perf_data = { 68371dc6c08SKrishna Manikandan .max_bw_low = 6800000, 68471dc6c08SKrishna Manikandan .max_bw_high = 6800000, 6857bdc0c4bSKalyan Thota .min_core_ib = 2400000, 6867bdc0c4bSKalyan Thota .min_llcc_ib = 800000, 6871cb2c4a2SRob Clark .min_dram_ib = 800000, 6887bdc0c4bSKalyan Thota .danger_lut_tbl = {0xff, 0xffff, 0x0}, 6897bdc0c4bSKalyan Thota .qos_lut_tbl = { 6907bdc0c4bSKalyan Thota {.nentry = ARRAY_SIZE(sc7180_qos_linear), 6917bdc0c4bSKalyan Thota .entries = sc7180_qos_linear 6927bdc0c4bSKalyan Thota }, 6937bdc0c4bSKalyan Thota {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 6947bdc0c4bSKalyan Thota .entries = sc7180_qos_macrotile 6957bdc0c4bSKalyan Thota }, 6967bdc0c4bSKalyan Thota {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 6977bdc0c4bSKalyan Thota .entries = sc7180_qos_nrt 6987bdc0c4bSKalyan Thota }, 6997bdc0c4bSKalyan Thota }, 7007bdc0c4bSKalyan Thota .cdp_cfg = { 7017bdc0c4bSKalyan Thota {.rd_enable = 1, .wr_enable = 1}, 7027bdc0c4bSKalyan Thota {.rd_enable = 1, .wr_enable = 0} 7037bdc0c4bSKalyan Thota }, 7047bdc0c4bSKalyan Thota }; 7057bdc0c4bSKalyan Thota 706386fced3SJonathan Marek static const struct dpu_perf_cfg sm8150_perf_data = { 707386fced3SJonathan Marek .max_bw_low = 12800000, 708386fced3SJonathan Marek .max_bw_high = 12800000, 709386fced3SJonathan Marek .min_core_ib = 2400000, 710386fced3SJonathan Marek .min_llcc_ib = 800000, 711386fced3SJonathan Marek .min_dram_ib = 800000, 712386fced3SJonathan Marek .danger_lut_tbl = {0xf, 0xffff, 0x0}, 713386fced3SJonathan Marek .qos_lut_tbl = { 714386fced3SJonathan Marek {.nentry = ARRAY_SIZE(sm8150_qos_linear), 715386fced3SJonathan Marek .entries = sm8150_qos_linear 716386fced3SJonathan Marek }, 717386fced3SJonathan Marek {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 718386fced3SJonathan Marek .entries = sc7180_qos_macrotile 719386fced3SJonathan Marek }, 720386fced3SJonathan Marek {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 721386fced3SJonathan Marek .entries = sc7180_qos_nrt 722386fced3SJonathan Marek }, 723386fced3SJonathan Marek /* TODO: macrotile-qseed is different from macrotile */ 724386fced3SJonathan Marek }, 725386fced3SJonathan Marek .cdp_cfg = { 726386fced3SJonathan Marek {.rd_enable = 1, .wr_enable = 1}, 727386fced3SJonathan Marek {.rd_enable = 1, .wr_enable = 0} 728386fced3SJonathan Marek }, 729386fced3SJonathan Marek }; 730386fced3SJonathan Marek 731af776a3eSJonathan Marek static const struct dpu_perf_cfg sm8250_perf_data = { 732af776a3eSJonathan Marek .max_bw_low = 13700000, 733af776a3eSJonathan Marek .max_bw_high = 16600000, 734af776a3eSJonathan Marek .min_core_ib = 4800000, 735af776a3eSJonathan Marek .min_llcc_ib = 0, 736af776a3eSJonathan Marek .min_dram_ib = 800000, 737af776a3eSJonathan Marek .danger_lut_tbl = {0xf, 0xffff, 0x0}, 738af776a3eSJonathan Marek .qos_lut_tbl = { 739af776a3eSJonathan Marek {.nentry = ARRAY_SIZE(sc7180_qos_linear), 740af776a3eSJonathan Marek .entries = sc7180_qos_linear 741af776a3eSJonathan Marek }, 742af776a3eSJonathan Marek {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 743af776a3eSJonathan Marek .entries = sc7180_qos_macrotile 744af776a3eSJonathan Marek }, 745af776a3eSJonathan Marek {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 746af776a3eSJonathan Marek .entries = sc7180_qos_nrt 747af776a3eSJonathan Marek }, 748af776a3eSJonathan Marek /* TODO: macrotile-qseed is different from macrotile */ 749af776a3eSJonathan Marek }, 750af776a3eSJonathan Marek .cdp_cfg = { 751af776a3eSJonathan Marek {.rd_enable = 1, .wr_enable = 1}, 752af776a3eSJonathan Marek {.rd_enable = 1, .wr_enable = 0} 753af776a3eSJonathan Marek }, 754af776a3eSJonathan Marek }; 755af776a3eSJonathan Marek 75625fdd593SJeykumar Sankaran /************************************************************* 75725fdd593SJeykumar Sankaran * Hardware catalog init 75825fdd593SJeykumar Sankaran *************************************************************/ 75925fdd593SJeykumar Sankaran 76025fdd593SJeykumar Sankaran /* 76125fdd593SJeykumar Sankaran * sdm845_cfg_init(): populate sdm845 dpu sub-blocks reg offsets 76225fdd593SJeykumar Sankaran * and instance counts. 76325fdd593SJeykumar Sankaran */ 764fba33caeSJordan Crouse static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg) 76525fdd593SJeykumar Sankaran { 76625fdd593SJeykumar Sankaran *dpu_cfg = (struct dpu_mdss_cfg){ 76725fdd593SJeykumar Sankaran .caps = &sdm845_dpu_caps, 76825fdd593SJeykumar Sankaran .mdp_count = ARRAY_SIZE(sdm845_mdp), 76925fdd593SJeykumar Sankaran .mdp = sdm845_mdp, 77025fdd593SJeykumar Sankaran .ctl_count = ARRAY_SIZE(sdm845_ctl), 77125fdd593SJeykumar Sankaran .ctl = sdm845_ctl, 77225fdd593SJeykumar Sankaran .sspp_count = ARRAY_SIZE(sdm845_sspp), 77325fdd593SJeykumar Sankaran .sspp = sdm845_sspp, 77425fdd593SJeykumar Sankaran .mixer_count = ARRAY_SIZE(sdm845_lm), 77525fdd593SJeykumar Sankaran .mixer = sdm845_lm, 77625fdd593SJeykumar Sankaran .pingpong_count = ARRAY_SIZE(sdm845_pp), 77725fdd593SJeykumar Sankaran .pingpong = sdm845_pp, 77825fdd593SJeykumar Sankaran .intf_count = ARRAY_SIZE(sdm845_intf), 77925fdd593SJeykumar Sankaran .intf = sdm845_intf, 78025fdd593SJeykumar Sankaran .vbif_count = ARRAY_SIZE(sdm845_vbif), 78125fdd593SJeykumar Sankaran .vbif = sdm845_vbif, 78225fdd593SJeykumar Sankaran .reg_dma_count = 1, 78325fdd593SJeykumar Sankaran .dma_cfg = sdm845_regdma, 78425fdd593SJeykumar Sankaran .perf = sdm845_perf_data, 7850846cca3SShubhashree Dhar .mdss_irqs = 0x3ff, 78625fdd593SJeykumar Sankaran }; 78725fdd593SJeykumar Sankaran } 78825fdd593SJeykumar Sankaran 7897bdc0c4bSKalyan Thota /* 7907bdc0c4bSKalyan Thota * sc7180_cfg_init(): populate sc7180 dpu sub-blocks reg offsets 7917bdc0c4bSKalyan Thota * and instance counts. 7927bdc0c4bSKalyan Thota */ 7937bdc0c4bSKalyan Thota static void sc7180_cfg_init(struct dpu_mdss_cfg *dpu_cfg) 7947bdc0c4bSKalyan Thota { 7957bdc0c4bSKalyan Thota *dpu_cfg = (struct dpu_mdss_cfg){ 7967bdc0c4bSKalyan Thota .caps = &sc7180_dpu_caps, 7977bdc0c4bSKalyan Thota .mdp_count = ARRAY_SIZE(sc7180_mdp), 7987bdc0c4bSKalyan Thota .mdp = sc7180_mdp, 7997bdc0c4bSKalyan Thota .ctl_count = ARRAY_SIZE(sc7180_ctl), 8007bdc0c4bSKalyan Thota .ctl = sc7180_ctl, 8017bdc0c4bSKalyan Thota .sspp_count = ARRAY_SIZE(sc7180_sspp), 8027bdc0c4bSKalyan Thota .sspp = sc7180_sspp, 8037bdc0c4bSKalyan Thota .mixer_count = ARRAY_SIZE(sc7180_lm), 8047bdc0c4bSKalyan Thota .mixer = sc7180_lm, 805e47616dfSKalyan Thota .dspp_count = ARRAY_SIZE(sc7180_dspp), 806e47616dfSKalyan Thota .dspp = sc7180_dspp, 8077bdc0c4bSKalyan Thota .pingpong_count = ARRAY_SIZE(sc7180_pp), 8087bdc0c4bSKalyan Thota .pingpong = sc7180_pp, 8097bdc0c4bSKalyan Thota .intf_count = ARRAY_SIZE(sc7180_intf), 8107bdc0c4bSKalyan Thota .intf = sc7180_intf, 8117bdc0c4bSKalyan Thota .vbif_count = ARRAY_SIZE(sdm845_vbif), 8127bdc0c4bSKalyan Thota .vbif = sdm845_vbif, 8137bdc0c4bSKalyan Thota .reg_dma_count = 1, 8147bdc0c4bSKalyan Thota .dma_cfg = sdm845_regdma, 8157bdc0c4bSKalyan Thota .perf = sc7180_perf_data, 8167bdc0c4bSKalyan Thota .mdss_irqs = 0x3f, 8177bdc0c4bSKalyan Thota }; 8187bdc0c4bSKalyan Thota } 8197bdc0c4bSKalyan Thota 820386fced3SJonathan Marek /* 821386fced3SJonathan Marek * sm8150_cfg_init(): populate sm8150 dpu sub-blocks reg offsets 822386fced3SJonathan Marek * and instance counts. 823386fced3SJonathan Marek */ 824386fced3SJonathan Marek static void sm8150_cfg_init(struct dpu_mdss_cfg *dpu_cfg) 825386fced3SJonathan Marek { 826386fced3SJonathan Marek *dpu_cfg = (struct dpu_mdss_cfg){ 827386fced3SJonathan Marek .caps = &sm8150_dpu_caps, 828386fced3SJonathan Marek .mdp_count = ARRAY_SIZE(sdm845_mdp), 829386fced3SJonathan Marek .mdp = sdm845_mdp, 830386fced3SJonathan Marek .ctl_count = ARRAY_SIZE(sm8150_ctl), 831386fced3SJonathan Marek .ctl = sm8150_ctl, 832386fced3SJonathan Marek .sspp_count = ARRAY_SIZE(sdm845_sspp), 833386fced3SJonathan Marek .sspp = sdm845_sspp, 834386fced3SJonathan Marek .mixer_count = ARRAY_SIZE(sm8150_lm), 835386fced3SJonathan Marek .mixer = sm8150_lm, 836386fced3SJonathan Marek .pingpong_count = ARRAY_SIZE(sm8150_pp), 837386fced3SJonathan Marek .pingpong = sm8150_pp, 838386fced3SJonathan Marek .intf_count = ARRAY_SIZE(sm8150_intf), 839386fced3SJonathan Marek .intf = sm8150_intf, 840386fced3SJonathan Marek .vbif_count = ARRAY_SIZE(sdm845_vbif), 841386fced3SJonathan Marek .vbif = sdm845_vbif, 842386fced3SJonathan Marek .reg_dma_count = 1, 843386fced3SJonathan Marek .dma_cfg = sm8150_regdma, 844386fced3SJonathan Marek .perf = sm8150_perf_data, 845386fced3SJonathan Marek .mdss_irqs = 0x3ff, 846386fced3SJonathan Marek }; 847386fced3SJonathan Marek } 848386fced3SJonathan Marek 849af776a3eSJonathan Marek /* 850af776a3eSJonathan Marek * sm8250_cfg_init(): populate sm8250 dpu sub-blocks reg offsets 851af776a3eSJonathan Marek * and instance counts. 852af776a3eSJonathan Marek */ 853af776a3eSJonathan Marek static void sm8250_cfg_init(struct dpu_mdss_cfg *dpu_cfg) 854af776a3eSJonathan Marek { 855af776a3eSJonathan Marek *dpu_cfg = (struct dpu_mdss_cfg){ 856af776a3eSJonathan Marek .caps = &sm8250_dpu_caps, 857af776a3eSJonathan Marek .mdp_count = ARRAY_SIZE(sm8250_mdp), 858af776a3eSJonathan Marek .mdp = sm8250_mdp, 859af776a3eSJonathan Marek .ctl_count = ARRAY_SIZE(sm8150_ctl), 860af776a3eSJonathan Marek .ctl = sm8150_ctl, 861af776a3eSJonathan Marek /* TODO: sspp qseed version differs from 845 */ 862af776a3eSJonathan Marek .sspp_count = ARRAY_SIZE(sdm845_sspp), 863af776a3eSJonathan Marek .sspp = sdm845_sspp, 864af776a3eSJonathan Marek .mixer_count = ARRAY_SIZE(sm8150_lm), 865af776a3eSJonathan Marek .mixer = sm8150_lm, 866af776a3eSJonathan Marek .pingpong_count = ARRAY_SIZE(sm8150_pp), 867af776a3eSJonathan Marek .pingpong = sm8150_pp, 868af776a3eSJonathan Marek .intf_count = ARRAY_SIZE(sm8150_intf), 869af776a3eSJonathan Marek .intf = sm8150_intf, 870af776a3eSJonathan Marek .vbif_count = ARRAY_SIZE(sdm845_vbif), 871af776a3eSJonathan Marek .vbif = sdm845_vbif, 872af776a3eSJonathan Marek .reg_dma_count = 1, 873af776a3eSJonathan Marek .dma_cfg = sm8250_regdma, 874af776a3eSJonathan Marek .perf = sm8250_perf_data, 875af776a3eSJonathan Marek .mdss_irqs = 0xff, 876af776a3eSJonathan Marek }; 877af776a3eSJonathan Marek } 878af776a3eSJonathan Marek 879abda0d92SStephen Boyd static const struct dpu_mdss_hw_cfg_handler cfg_handler[] = { 88025fdd593SJeykumar Sankaran { .hw_rev = DPU_HW_VER_400, .cfg_init = sdm845_cfg_init}, 88125fdd593SJeykumar Sankaran { .hw_rev = DPU_HW_VER_401, .cfg_init = sdm845_cfg_init}, 882386fced3SJonathan Marek { .hw_rev = DPU_HW_VER_500, .cfg_init = sm8150_cfg_init}, 883386fced3SJonathan Marek { .hw_rev = DPU_HW_VER_501, .cfg_init = sm8150_cfg_init}, 884af776a3eSJonathan Marek { .hw_rev = DPU_HW_VER_600, .cfg_init = sm8250_cfg_init}, 8857bdc0c4bSKalyan Thota { .hw_rev = DPU_HW_VER_620, .cfg_init = sc7180_cfg_init}, 88625fdd593SJeykumar Sankaran }; 88725fdd593SJeykumar Sankaran 88825fdd593SJeykumar Sankaran void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg) 88925fdd593SJeykumar Sankaran { 89025fdd593SJeykumar Sankaran kfree(dpu_cfg); 89125fdd593SJeykumar Sankaran } 89225fdd593SJeykumar Sankaran 89325fdd593SJeykumar Sankaran struct dpu_mdss_cfg *dpu_hw_catalog_init(u32 hw_rev) 89425fdd593SJeykumar Sankaran { 89525fdd593SJeykumar Sankaran int i; 89625fdd593SJeykumar Sankaran struct dpu_mdss_cfg *dpu_cfg; 89725fdd593SJeykumar Sankaran 89825fdd593SJeykumar Sankaran dpu_cfg = kzalloc(sizeof(*dpu_cfg), GFP_KERNEL); 89925fdd593SJeykumar Sankaran if (!dpu_cfg) 90025fdd593SJeykumar Sankaran return ERR_PTR(-ENOMEM); 90125fdd593SJeykumar Sankaran 90225fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(cfg_handler); i++) { 90325fdd593SJeykumar Sankaran if (cfg_handler[i].hw_rev == hw_rev) { 90425fdd593SJeykumar Sankaran cfg_handler[i].cfg_init(dpu_cfg); 90525fdd593SJeykumar Sankaran dpu_cfg->hwversion = hw_rev; 90625fdd593SJeykumar Sankaran return dpu_cfg; 90725fdd593SJeykumar Sankaran } 90825fdd593SJeykumar Sankaran } 90925fdd593SJeykumar Sankaran 91025fdd593SJeykumar Sankaran DPU_ERROR("unsupported chipset id:%X\n", hw_rev); 91125fdd593SJeykumar Sankaran dpu_hw_catalog_deinit(dpu_cfg); 91225fdd593SJeykumar Sankaran return ERR_PTR(-ENODEV); 91325fdd593SJeykumar Sankaran } 91425fdd593SJeykumar Sankaran 915