1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved. 3 */ 4 5 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 6 #include "dpu_encoder_phys.h" 7 #include "dpu_hw_interrupts.h" 8 #include "dpu_hw_merge3d.h" 9 #include "dpu_core_irq.h" 10 #include "dpu_formats.h" 11 #include "dpu_trace.h" 12 #include "disp/msm_disp_snapshot.h" 13 14 #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \ 15 (e) && (e)->parent ? \ 16 (e)->parent->base.id : -1, \ 17 (e) && (e)->hw_intf ? \ 18 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__) 19 20 #define DPU_ERROR_VIDENC(e, fmt, ...) DPU_ERROR("enc%d intf%d " fmt, \ 21 (e) && (e)->parent ? \ 22 (e)->parent->base.id : -1, \ 23 (e) && (e)->hw_intf ? \ 24 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__) 25 26 #define to_dpu_encoder_phys_vid(x) \ 27 container_of(x, struct dpu_encoder_phys_vid, base) 28 29 static bool dpu_encoder_phys_vid_is_master( 30 struct dpu_encoder_phys *phys_enc) 31 { 32 bool ret = false; 33 34 if (phys_enc->split_role != ENC_ROLE_SLAVE) 35 ret = true; 36 37 return ret; 38 } 39 40 static void drm_mode_to_intf_timing_params( 41 const struct dpu_encoder_phys *phys_enc, 42 const struct drm_display_mode *mode, 43 struct intf_timing_params *timing) 44 { 45 memset(timing, 0, sizeof(*timing)); 46 47 if ((mode->htotal < mode->hsync_end) 48 || (mode->hsync_start < mode->hdisplay) 49 || (mode->vtotal < mode->vsync_end) 50 || (mode->vsync_start < mode->vdisplay) 51 || (mode->hsync_end < mode->hsync_start) 52 || (mode->vsync_end < mode->vsync_start)) { 53 DPU_ERROR( 54 "invalid params - hstart:%d,hend:%d,htot:%d,hdisplay:%d\n", 55 mode->hsync_start, mode->hsync_end, 56 mode->htotal, mode->hdisplay); 57 DPU_ERROR("vstart:%d,vend:%d,vtot:%d,vdisplay:%d\n", 58 mode->vsync_start, mode->vsync_end, 59 mode->vtotal, mode->vdisplay); 60 return; 61 } 62 63 /* 64 * https://www.kernel.org/doc/htmldocs/drm/ch02s05.html 65 * Active Region Front Porch Sync Back Porch 66 * <-----------------><------------><-----><-----------> 67 * <- [hv]display ---> 68 * <--------- [hv]sync_start ------> 69 * <----------------- [hv]sync_end -------> 70 * <---------------------------- [hv]total -------------> 71 */ 72 timing->width = mode->hdisplay; /* active width */ 73 timing->height = mode->vdisplay; /* active height */ 74 timing->xres = timing->width; 75 timing->yres = timing->height; 76 timing->h_back_porch = mode->htotal - mode->hsync_end; 77 timing->h_front_porch = mode->hsync_start - mode->hdisplay; 78 timing->v_back_porch = mode->vtotal - mode->vsync_end; 79 timing->v_front_porch = mode->vsync_start - mode->vdisplay; 80 timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start; 81 timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start; 82 timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0; 83 timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0; 84 timing->border_clr = 0; 85 timing->underflow_clr = 0xff; 86 timing->hsync_skew = mode->hskew; 87 88 /* DSI controller cannot handle active-low sync signals. */ 89 if (phys_enc->hw_intf->cap->type == INTF_DSI) { 90 timing->hsync_polarity = 0; 91 timing->vsync_polarity = 0; 92 } 93 94 /* 95 * For edp only: 96 * DISPLAY_V_START = (VBP * HCYCLE) + HBP 97 * DISPLAY_V_END = (VBP + VACTIVE) * HCYCLE - 1 - HFP 98 */ 99 /* 100 * if (vid_enc->hw->cap->type == INTF_EDP) { 101 * display_v_start += mode->htotal - mode->hsync_start; 102 * display_v_end -= mode->hsync_start - mode->hdisplay; 103 * } 104 */ 105 /* for DP/EDP, Shift timings to align it to bottom right */ 106 if ((phys_enc->hw_intf->cap->type == INTF_DP) || 107 (phys_enc->hw_intf->cap->type == INTF_EDP)) { 108 timing->h_back_porch += timing->h_front_porch; 109 timing->h_front_porch = 0; 110 timing->v_back_porch += timing->v_front_porch; 111 timing->v_front_porch = 0; 112 } 113 } 114 115 static u32 get_horizontal_total(const struct intf_timing_params *timing) 116 { 117 u32 active = timing->xres; 118 u32 inactive = 119 timing->h_back_porch + timing->h_front_porch + 120 timing->hsync_pulse_width; 121 return active + inactive; 122 } 123 124 static u32 get_vertical_total(const struct intf_timing_params *timing) 125 { 126 u32 active = timing->yres; 127 u32 inactive = 128 timing->v_back_porch + timing->v_front_porch + 129 timing->vsync_pulse_width; 130 return active + inactive; 131 } 132 133 /* 134 * programmable_fetch_get_num_lines: 135 * Number of fetch lines in vertical front porch 136 * @timing: Pointer to the intf timing information for the requested mode 137 * 138 * Returns the number of fetch lines in vertical front porch at which mdp 139 * can start fetching the next frame. 140 * 141 * Number of needed prefetch lines is anything that cannot be absorbed in the 142 * start of frame time (back porch + vsync pulse width). 143 * 144 * Some panels have very large VFP, however we only need a total number of 145 * lines based on the chip worst case latencies. 146 */ 147 static u32 programmable_fetch_get_num_lines( 148 struct dpu_encoder_phys *phys_enc, 149 const struct intf_timing_params *timing) 150 { 151 u32 worst_case_needed_lines = 152 phys_enc->hw_intf->cap->prog_fetch_lines_worst_case; 153 u32 start_of_frame_lines = 154 timing->v_back_porch + timing->vsync_pulse_width; 155 u32 needed_vfp_lines = worst_case_needed_lines - start_of_frame_lines; 156 u32 actual_vfp_lines = 0; 157 158 /* Fetch must be outside active lines, otherwise undefined. */ 159 if (start_of_frame_lines >= worst_case_needed_lines) { 160 DPU_DEBUG_VIDENC(phys_enc, 161 "prog fetch is not needed, large vbp+vsw\n"); 162 actual_vfp_lines = 0; 163 } else if (timing->v_front_porch < needed_vfp_lines) { 164 /* Warn fetch needed, but not enough porch in panel config */ 165 pr_warn_once 166 ("low vbp+vfp may lead to perf issues in some cases\n"); 167 DPU_DEBUG_VIDENC(phys_enc, 168 "less vfp than fetch req, using entire vfp\n"); 169 actual_vfp_lines = timing->v_front_porch; 170 } else { 171 DPU_DEBUG_VIDENC(phys_enc, "room in vfp for needed prefetch\n"); 172 actual_vfp_lines = needed_vfp_lines; 173 } 174 175 DPU_DEBUG_VIDENC(phys_enc, 176 "v_front_porch %u v_back_porch %u vsync_pulse_width %u\n", 177 timing->v_front_porch, timing->v_back_porch, 178 timing->vsync_pulse_width); 179 DPU_DEBUG_VIDENC(phys_enc, 180 "wc_lines %u needed_vfp_lines %u actual_vfp_lines %u\n", 181 worst_case_needed_lines, needed_vfp_lines, actual_vfp_lines); 182 183 return actual_vfp_lines; 184 } 185 186 /* 187 * programmable_fetch_config: Programs HW to prefetch lines by offsetting 188 * the start of fetch into the vertical front porch for cases where the 189 * vsync pulse width and vertical back porch time is insufficient 190 * 191 * Gets # of lines to pre-fetch, then calculate VSYNC counter value. 192 * HW layer requires VSYNC counter of first pixel of tgt VFP line. 193 * 194 * @timing: Pointer to the intf timing information for the requested mode 195 */ 196 static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc, 197 const struct intf_timing_params *timing) 198 { 199 struct intf_prog_fetch f = { 0 }; 200 u32 vfp_fetch_lines = 0; 201 u32 horiz_total = 0; 202 u32 vert_total = 0; 203 u32 vfp_fetch_start_vsync_counter = 0; 204 unsigned long lock_flags; 205 206 if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch)) 207 return; 208 209 vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing); 210 if (vfp_fetch_lines) { 211 vert_total = get_vertical_total(timing); 212 horiz_total = get_horizontal_total(timing); 213 vfp_fetch_start_vsync_counter = 214 (vert_total - vfp_fetch_lines) * horiz_total + 1; 215 f.enable = 1; 216 f.fetch_start = vfp_fetch_start_vsync_counter; 217 } 218 219 DPU_DEBUG_VIDENC(phys_enc, 220 "vfp_fetch_lines %u vfp_fetch_start_vsync_counter %u\n", 221 vfp_fetch_lines, vfp_fetch_start_vsync_counter); 222 223 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); 224 phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f); 225 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); 226 } 227 228 static bool dpu_encoder_phys_vid_mode_fixup( 229 struct dpu_encoder_phys *phys_enc, 230 const struct drm_display_mode *mode, 231 struct drm_display_mode *adj_mode) 232 { 233 DPU_DEBUG_VIDENC(phys_enc, "\n"); 234 235 /* 236 * Modifying mode has consequences when the mode comes back to us 237 */ 238 return true; 239 } 240 241 static void dpu_encoder_phys_vid_setup_timing_engine( 242 struct dpu_encoder_phys *phys_enc) 243 { 244 struct drm_display_mode mode; 245 struct intf_timing_params timing_params = { 0 }; 246 const struct dpu_format *fmt = NULL; 247 u32 fmt_fourcc = DRM_FORMAT_RGB888; 248 unsigned long lock_flags; 249 struct dpu_hw_intf_cfg intf_cfg = { 0 }; 250 251 if (!phys_enc->hw_ctl->ops.setup_intf_cfg) { 252 DPU_ERROR("invalid encoder %d\n", phys_enc != NULL); 253 return; 254 } 255 256 mode = phys_enc->cached_mode; 257 if (!phys_enc->hw_intf->ops.setup_timing_gen) { 258 DPU_ERROR("timing engine setup is not supported\n"); 259 return; 260 } 261 262 DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n"); 263 drm_mode_debug_printmodeline(&mode); 264 265 if (phys_enc->split_role != ENC_ROLE_SOLO) { 266 mode.hdisplay >>= 1; 267 mode.htotal >>= 1; 268 mode.hsync_start >>= 1; 269 mode.hsync_end >>= 1; 270 271 DPU_DEBUG_VIDENC(phys_enc, 272 "split_role %d, halve horizontal %d %d %d %d\n", 273 phys_enc->split_role, 274 mode.hdisplay, mode.htotal, 275 mode.hsync_start, mode.hsync_end); 276 } 277 278 drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params); 279 280 fmt = dpu_get_dpu_format(fmt_fourcc); 281 DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc); 282 283 intf_cfg.intf = phys_enc->hw_intf->idx; 284 intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID; 285 intf_cfg.stream_sel = 0; /* Don't care value for video mode */ 286 intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); 287 if (phys_enc->hw_pp->merge_3d) 288 intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; 289 290 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); 291 phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf, 292 &timing_params, fmt); 293 phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); 294 295 /* setup which pp blk will connect to this intf */ 296 if (phys_enc->hw_intf->ops.bind_pingpong_blk) 297 phys_enc->hw_intf->ops.bind_pingpong_blk( 298 phys_enc->hw_intf, 299 true, 300 phys_enc->hw_pp->idx); 301 302 if (phys_enc->hw_pp->merge_3d) 303 phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d); 304 305 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); 306 307 programmable_fetch_config(phys_enc, &timing_params); 308 } 309 310 static void dpu_encoder_phys_vid_vblank_irq(void *arg, int irq_idx) 311 { 312 struct dpu_encoder_phys *phys_enc = arg; 313 struct dpu_hw_ctl *hw_ctl; 314 unsigned long lock_flags; 315 u32 flush_register = 0; 316 317 hw_ctl = phys_enc->hw_ctl; 318 319 DPU_ATRACE_BEGIN("vblank_irq"); 320 321 if (phys_enc->parent_ops->handle_vblank_virt) 322 phys_enc->parent_ops->handle_vblank_virt(phys_enc->parent, 323 phys_enc); 324 325 atomic_read(&phys_enc->pending_kickoff_cnt); 326 327 /* 328 * only decrement the pending flush count if we've actually flushed 329 * hardware. due to sw irq latency, vblank may have already happened 330 * so we need to double-check with hw that it accepted the flush bits 331 */ 332 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); 333 if (hw_ctl->ops.get_flush_register) 334 flush_register = hw_ctl->ops.get_flush_register(hw_ctl); 335 336 if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl))) 337 atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0); 338 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); 339 340 /* Signal any waiting atomic commit thread */ 341 wake_up_all(&phys_enc->pending_kickoff_wq); 342 343 phys_enc->parent_ops->handle_frame_done(phys_enc->parent, phys_enc, 344 DPU_ENCODER_FRAME_EVENT_DONE); 345 346 DPU_ATRACE_END("vblank_irq"); 347 } 348 349 static void dpu_encoder_phys_vid_underrun_irq(void *arg, int irq_idx) 350 { 351 struct dpu_encoder_phys *phys_enc = arg; 352 353 if (phys_enc->parent_ops->handle_underrun_virt) 354 phys_enc->parent_ops->handle_underrun_virt(phys_enc->parent, 355 phys_enc); 356 } 357 358 static bool dpu_encoder_phys_vid_needs_single_flush( 359 struct dpu_encoder_phys *phys_enc) 360 { 361 return phys_enc->split_role != ENC_ROLE_SOLO; 362 } 363 364 static void dpu_encoder_phys_vid_mode_set( 365 struct dpu_encoder_phys *phys_enc, 366 struct drm_display_mode *mode, 367 struct drm_display_mode *adj_mode) 368 { 369 struct dpu_encoder_irq *irq; 370 371 if (adj_mode) { 372 phys_enc->cached_mode = *adj_mode; 373 drm_mode_debug_printmodeline(adj_mode); 374 DPU_DEBUG_VIDENC(phys_enc, "caching mode:\n"); 375 } 376 377 irq = &phys_enc->irq[INTR_IDX_VSYNC]; 378 irq->irq_idx = phys_enc->hw_intf->cap->intr_vsync; 379 380 irq = &phys_enc->irq[INTR_IDX_UNDERRUN]; 381 irq->irq_idx = phys_enc->hw_intf->cap->intr_underrun; 382 } 383 384 static int dpu_encoder_phys_vid_control_vblank_irq( 385 struct dpu_encoder_phys *phys_enc, 386 bool enable) 387 { 388 int ret = 0; 389 int refcount; 390 391 refcount = atomic_read(&phys_enc->vblank_refcount); 392 393 /* Slave encoders don't report vblank */ 394 if (!dpu_encoder_phys_vid_is_master(phys_enc)) 395 goto end; 396 397 /* protect against negative */ 398 if (!enable && refcount == 0) { 399 ret = -EINVAL; 400 goto end; 401 } 402 403 DRM_DEBUG_VBL("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable, 404 atomic_read(&phys_enc->vblank_refcount)); 405 406 if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1) 407 ret = dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_VSYNC); 408 else if (!enable && atomic_dec_return(&phys_enc->vblank_refcount) == 0) 409 ret = dpu_encoder_helper_unregister_irq(phys_enc, 410 INTR_IDX_VSYNC); 411 412 end: 413 if (ret) { 414 DRM_ERROR("failed: id:%u intf:%d ret:%d enable:%d refcnt:%d\n", 415 DRMID(phys_enc->parent), 416 phys_enc->hw_intf->idx - INTF_0, ret, enable, 417 refcount); 418 } 419 return ret; 420 } 421 422 static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) 423 { 424 struct dpu_hw_ctl *ctl; 425 426 ctl = phys_enc->hw_ctl; 427 428 DPU_DEBUG_VIDENC(phys_enc, "\n"); 429 430 if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing)) 431 return; 432 433 dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx); 434 435 dpu_encoder_phys_vid_setup_timing_engine(phys_enc); 436 437 /* 438 * For single flush cases (dual-ctl or pp-split), skip setting the 439 * flush bit for the slave intf, since both intfs use same ctl 440 * and HW will only flush the master. 441 */ 442 if (dpu_encoder_phys_vid_needs_single_flush(phys_enc) && 443 !dpu_encoder_phys_vid_is_master(phys_enc)) 444 goto skip_flush; 445 446 ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx); 447 if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d) 448 ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx); 449 450 skip_flush: 451 DPU_DEBUG_VIDENC(phys_enc, 452 "update pending flush ctl %d intf %d\n", 453 ctl->idx - CTL_0, phys_enc->hw_intf->idx); 454 455 atomic_set(&phys_enc->underrun_cnt, 0); 456 457 /* ctl_flush & timing engine enable will be triggered by framework */ 458 if (phys_enc->enable_state == DPU_ENC_DISABLED) 459 phys_enc->enable_state = DPU_ENC_ENABLING; 460 } 461 462 static void dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys *phys_enc) 463 { 464 DPU_DEBUG_VIDENC(phys_enc, "\n"); 465 kfree(phys_enc); 466 } 467 468 static void dpu_encoder_phys_vid_get_hw_resources( 469 struct dpu_encoder_phys *phys_enc, 470 struct dpu_encoder_hw_resources *hw_res) 471 { 472 hw_res->intfs[phys_enc->intf_idx - INTF_0] = INTF_MODE_VIDEO; 473 } 474 475 static int dpu_encoder_phys_vid_wait_for_vblank( 476 struct dpu_encoder_phys *phys_enc) 477 { 478 struct dpu_encoder_wait_info wait_info; 479 int ret; 480 481 wait_info.wq = &phys_enc->pending_kickoff_wq; 482 wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt; 483 wait_info.timeout_ms = KICKOFF_TIMEOUT_MS; 484 485 if (!dpu_encoder_phys_vid_is_master(phys_enc)) { 486 return 0; 487 } 488 489 /* Wait for kickoff to complete */ 490 ret = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_VSYNC, 491 &wait_info); 492 493 if (ret == -ETIMEDOUT) { 494 dpu_encoder_helper_report_irq_timeout(phys_enc, INTR_IDX_VSYNC); 495 } 496 497 return ret; 498 } 499 500 static int dpu_encoder_phys_vid_wait_for_commit_done( 501 struct dpu_encoder_phys *phys_enc) 502 { 503 struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl; 504 int ret; 505 506 if (!hw_ctl) 507 return 0; 508 509 ret = wait_event_timeout(phys_enc->pending_kickoff_wq, 510 (hw_ctl->ops.get_flush_register(hw_ctl) == 0), 511 msecs_to_jiffies(50)); 512 if (ret <= 0) { 513 DPU_ERROR("vblank timeout\n"); 514 return -ETIMEDOUT; 515 } 516 517 return 0; 518 } 519 520 static void dpu_encoder_phys_vid_prepare_for_kickoff( 521 struct dpu_encoder_phys *phys_enc) 522 { 523 struct dpu_hw_ctl *ctl; 524 int rc; 525 struct drm_encoder *drm_enc; 526 527 drm_enc = phys_enc->parent; 528 529 ctl = phys_enc->hw_ctl; 530 if (!ctl->ops.wait_reset_status) 531 return; 532 533 /* 534 * hw supports hardware initiated ctl reset, so before we kickoff a new 535 * frame, need to check and wait for hw initiated ctl reset completion 536 */ 537 rc = ctl->ops.wait_reset_status(ctl); 538 if (rc) { 539 DPU_ERROR_VIDENC(phys_enc, "ctl %d reset failure: %d\n", 540 ctl->idx, rc); 541 msm_disp_snapshot_state(drm_enc->dev); 542 dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_VSYNC); 543 } 544 } 545 546 static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc) 547 { 548 unsigned long lock_flags; 549 int ret; 550 551 if (!phys_enc->parent || !phys_enc->parent->dev) { 552 DPU_ERROR("invalid encoder/device\n"); 553 return; 554 } 555 556 if (!phys_enc->hw_intf) { 557 DPU_ERROR("invalid hw_intf %d hw_ctl %d\n", 558 phys_enc->hw_intf != NULL, phys_enc->hw_ctl != NULL); 559 return; 560 } 561 562 if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing)) 563 return; 564 565 if (phys_enc->enable_state == DPU_ENC_DISABLED) { 566 DPU_ERROR("already disabled\n"); 567 return; 568 } 569 570 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); 571 phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0); 572 if (dpu_encoder_phys_vid_is_master(phys_enc)) 573 dpu_encoder_phys_inc_pending(phys_enc); 574 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); 575 576 /* 577 * Wait for a vsync so we know the ENABLE=0 latched before 578 * the (connector) source of the vsync's gets disabled, 579 * otherwise we end up in a funny state if we re-enable 580 * before the disable latches, which results that some of 581 * the settings changes for the new modeset (like new 582 * scanout buffer) don't latch properly.. 583 */ 584 if (dpu_encoder_phys_vid_is_master(phys_enc)) { 585 ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc); 586 if (ret) { 587 atomic_set(&phys_enc->pending_kickoff_cnt, 0); 588 DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n", 589 DRMID(phys_enc->parent), 590 phys_enc->hw_intf->idx - INTF_0, ret); 591 } 592 } 593 594 phys_enc->enable_state = DPU_ENC_DISABLED; 595 } 596 597 static void dpu_encoder_phys_vid_handle_post_kickoff( 598 struct dpu_encoder_phys *phys_enc) 599 { 600 unsigned long lock_flags; 601 602 /* 603 * Video mode must flush CTL before enabling timing engine 604 * Video encoders need to turn on their interfaces now 605 */ 606 if (phys_enc->enable_state == DPU_ENC_ENABLING) { 607 trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent), 608 phys_enc->hw_intf->idx - INTF_0); 609 spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); 610 phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 1); 611 spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); 612 phys_enc->enable_state = DPU_ENC_ENABLED; 613 } 614 } 615 616 static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc, 617 bool enable) 618 { 619 int ret; 620 621 trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent), 622 phys_enc->hw_intf->idx - INTF_0, 623 enable, 624 atomic_read(&phys_enc->vblank_refcount)); 625 626 if (enable) { 627 ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true); 628 if (WARN_ON(ret)) 629 return; 630 631 dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN); 632 } else { 633 dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false); 634 dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_UNDERRUN); 635 } 636 } 637 638 static int dpu_encoder_phys_vid_get_line_count( 639 struct dpu_encoder_phys *phys_enc) 640 { 641 if (!dpu_encoder_phys_vid_is_master(phys_enc)) 642 return -EINVAL; 643 644 if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count) 645 return -EINVAL; 646 647 return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf); 648 } 649 650 static int dpu_encoder_phys_vid_get_frame_count( 651 struct dpu_encoder_phys *phys_enc) 652 { 653 struct intf_status s = {0}; 654 u32 fetch_start = 0; 655 struct drm_display_mode mode = phys_enc->cached_mode; 656 657 if (!dpu_encoder_phys_vid_is_master(phys_enc)) 658 return -EINVAL; 659 660 if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_status) 661 return -EINVAL; 662 663 phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf, &s); 664 665 if (s.is_prog_fetch_en && s.is_en) { 666 fetch_start = mode.vtotal - (mode.vsync_start - mode.vdisplay); 667 if ((s.line_count > fetch_start) && 668 (s.line_count <= mode.vtotal)) 669 return s.frame_count + 1; 670 } 671 672 return s.frame_count; 673 } 674 675 static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) 676 { 677 ops->is_master = dpu_encoder_phys_vid_is_master; 678 ops->mode_set = dpu_encoder_phys_vid_mode_set; 679 ops->mode_fixup = dpu_encoder_phys_vid_mode_fixup; 680 ops->enable = dpu_encoder_phys_vid_enable; 681 ops->disable = dpu_encoder_phys_vid_disable; 682 ops->destroy = dpu_encoder_phys_vid_destroy; 683 ops->get_hw_resources = dpu_encoder_phys_vid_get_hw_resources; 684 ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq; 685 ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done; 686 ops->wait_for_vblank = dpu_encoder_phys_vid_wait_for_vblank; 687 ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_vblank; 688 ops->irq_control = dpu_encoder_phys_vid_irq_control; 689 ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff; 690 ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff; 691 ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush; 692 ops->get_line_count = dpu_encoder_phys_vid_get_line_count; 693 ops->get_frame_count = dpu_encoder_phys_vid_get_frame_count; 694 } 695 696 struct dpu_encoder_phys *dpu_encoder_phys_vid_init( 697 struct dpu_enc_phys_init_params *p) 698 { 699 struct dpu_encoder_phys *phys_enc = NULL; 700 struct dpu_encoder_irq *irq; 701 int i, ret = 0; 702 703 if (!p) { 704 ret = -EINVAL; 705 goto fail; 706 } 707 708 phys_enc = kzalloc(sizeof(*phys_enc), GFP_KERNEL); 709 if (!phys_enc) { 710 ret = -ENOMEM; 711 goto fail; 712 } 713 714 phys_enc->hw_mdptop = p->dpu_kms->hw_mdp; 715 phys_enc->intf_idx = p->intf_idx; 716 717 DPU_DEBUG_VIDENC(phys_enc, "\n"); 718 719 dpu_encoder_phys_vid_init_ops(&phys_enc->ops); 720 phys_enc->parent = p->parent; 721 phys_enc->parent_ops = p->parent_ops; 722 phys_enc->dpu_kms = p->dpu_kms; 723 phys_enc->split_role = p->split_role; 724 phys_enc->intf_mode = INTF_MODE_VIDEO; 725 phys_enc->enc_spinlock = p->enc_spinlock; 726 for (i = 0; i < INTR_IDX_MAX; i++) { 727 irq = &phys_enc->irq[i]; 728 INIT_LIST_HEAD(&irq->cb.list); 729 irq->irq_idx = -EINVAL; 730 irq->cb.arg = phys_enc; 731 } 732 733 irq = &phys_enc->irq[INTR_IDX_VSYNC]; 734 irq->name = "vsync_irq"; 735 irq->intr_idx = INTR_IDX_VSYNC; 736 irq->cb.func = dpu_encoder_phys_vid_vblank_irq; 737 738 irq = &phys_enc->irq[INTR_IDX_UNDERRUN]; 739 irq->name = "underrun"; 740 irq->intr_idx = INTR_IDX_UNDERRUN; 741 irq->cb.func = dpu_encoder_phys_vid_underrun_irq; 742 743 atomic_set(&phys_enc->vblank_refcount, 0); 744 atomic_set(&phys_enc->pending_kickoff_cnt, 0); 745 init_waitqueue_head(&phys_enc->pending_kickoff_wq); 746 phys_enc->enable_state = DPU_ENC_DISABLED; 747 748 DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->intf_idx); 749 750 return phys_enc; 751 752 fail: 753 DPU_ERROR("failed to create encoder\n"); 754 if (phys_enc) 755 dpu_encoder_phys_vid_destroy(phys_enc); 756 757 return ERR_PTR(ret); 758 } 759