197fb5e8dSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 22ec5b3dcSAbhinav Kumar /* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved. 325fdd593SJeykumar Sankaran */ 425fdd593SJeykumar Sankaran 525fdd593SJeykumar Sankaran #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 625fdd593SJeykumar Sankaran #include "dpu_encoder_phys.h" 725fdd593SJeykumar Sankaran #include "dpu_hw_interrupts.h" 83e79527aSDmitry Baryshkov #include "dpu_hw_merge3d.h" 925fdd593SJeykumar Sankaran #include "dpu_core_irq.h" 1025fdd593SJeykumar Sankaran #include "dpu_formats.h" 1125fdd593SJeykumar Sankaran #include "dpu_trace.h" 122ec5b3dcSAbhinav Kumar #include "disp/msm_disp_snapshot.h" 1325fdd593SJeykumar Sankaran 1425fdd593SJeykumar Sankaran #define DPU_DEBUG_VIDENC(e, fmt, ...) DPU_DEBUG("enc%d intf%d " fmt, \ 15b6057cdaSJeykumar Sankaran (e) && (e)->parent ? \ 16b6057cdaSJeykumar Sankaran (e)->parent->base.id : -1, \ 1725fdd593SJeykumar Sankaran (e) && (e)->hw_intf ? \ 1825fdd593SJeykumar Sankaran (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__) 1925fdd593SJeykumar Sankaran 2025fdd593SJeykumar Sankaran #define DPU_ERROR_VIDENC(e, fmt, ...) DPU_ERROR("enc%d intf%d " fmt, \ 21b6057cdaSJeykumar Sankaran (e) && (e)->parent ? \ 22b6057cdaSJeykumar Sankaran (e)->parent->base.id : -1, \ 2325fdd593SJeykumar Sankaran (e) && (e)->hw_intf ? \ 2425fdd593SJeykumar Sankaran (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__) 2525fdd593SJeykumar Sankaran 2625fdd593SJeykumar Sankaran #define to_dpu_encoder_phys_vid(x) \ 2725fdd593SJeykumar Sankaran container_of(x, struct dpu_encoder_phys_vid, base) 2825fdd593SJeykumar Sankaran 2925fdd593SJeykumar Sankaran static bool dpu_encoder_phys_vid_is_master( 3025fdd593SJeykumar Sankaran struct dpu_encoder_phys *phys_enc) 3125fdd593SJeykumar Sankaran { 3225fdd593SJeykumar Sankaran bool ret = false; 3325fdd593SJeykumar Sankaran 3425fdd593SJeykumar Sankaran if (phys_enc->split_role != ENC_ROLE_SLAVE) 3525fdd593SJeykumar Sankaran ret = true; 3625fdd593SJeykumar Sankaran 3725fdd593SJeykumar Sankaran return ret; 3825fdd593SJeykumar Sankaran } 3925fdd593SJeykumar Sankaran 4025fdd593SJeykumar Sankaran static void drm_mode_to_intf_timing_params( 41b6057cdaSJeykumar Sankaran const struct dpu_encoder_phys *phys_enc, 4225fdd593SJeykumar Sankaran const struct drm_display_mode *mode, 4325fdd593SJeykumar Sankaran struct intf_timing_params *timing) 4425fdd593SJeykumar Sankaran { 4525fdd593SJeykumar Sankaran memset(timing, 0, sizeof(*timing)); 4625fdd593SJeykumar Sankaran 4725fdd593SJeykumar Sankaran if ((mode->htotal < mode->hsync_end) 4825fdd593SJeykumar Sankaran || (mode->hsync_start < mode->hdisplay) 4925fdd593SJeykumar Sankaran || (mode->vtotal < mode->vsync_end) 5025fdd593SJeykumar Sankaran || (mode->vsync_start < mode->vdisplay) 5125fdd593SJeykumar Sankaran || (mode->hsync_end < mode->hsync_start) 5225fdd593SJeykumar Sankaran || (mode->vsync_end < mode->vsync_start)) { 5325fdd593SJeykumar Sankaran DPU_ERROR( 5425fdd593SJeykumar Sankaran "invalid params - hstart:%d,hend:%d,htot:%d,hdisplay:%d\n", 5525fdd593SJeykumar Sankaran mode->hsync_start, mode->hsync_end, 5625fdd593SJeykumar Sankaran mode->htotal, mode->hdisplay); 5725fdd593SJeykumar Sankaran DPU_ERROR("vstart:%d,vend:%d,vtot:%d,vdisplay:%d\n", 5825fdd593SJeykumar Sankaran mode->vsync_start, mode->vsync_end, 5925fdd593SJeykumar Sankaran mode->vtotal, mode->vdisplay); 6025fdd593SJeykumar Sankaran return; 6125fdd593SJeykumar Sankaran } 6225fdd593SJeykumar Sankaran 6325fdd593SJeykumar Sankaran /* 6425fdd593SJeykumar Sankaran * https://www.kernel.org/doc/htmldocs/drm/ch02s05.html 6525fdd593SJeykumar Sankaran * Active Region Front Porch Sync Back Porch 6625fdd593SJeykumar Sankaran * <-----------------><------------><-----><-----------> 6725fdd593SJeykumar Sankaran * <- [hv]display ---> 6825fdd593SJeykumar Sankaran * <--------- [hv]sync_start ------> 6925fdd593SJeykumar Sankaran * <----------------- [hv]sync_end -------> 7025fdd593SJeykumar Sankaran * <---------------------------- [hv]total -------------> 7125fdd593SJeykumar Sankaran */ 7225fdd593SJeykumar Sankaran timing->width = mode->hdisplay; /* active width */ 7325fdd593SJeykumar Sankaran timing->height = mode->vdisplay; /* active height */ 7425fdd593SJeykumar Sankaran timing->xres = timing->width; 7525fdd593SJeykumar Sankaran timing->yres = timing->height; 7625fdd593SJeykumar Sankaran timing->h_back_porch = mode->htotal - mode->hsync_end; 7725fdd593SJeykumar Sankaran timing->h_front_porch = mode->hsync_start - mode->hdisplay; 7825fdd593SJeykumar Sankaran timing->v_back_porch = mode->vtotal - mode->vsync_end; 7925fdd593SJeykumar Sankaran timing->v_front_porch = mode->vsync_start - mode->vdisplay; 8025fdd593SJeykumar Sankaran timing->hsync_pulse_width = mode->hsync_end - mode->hsync_start; 8125fdd593SJeykumar Sankaran timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start; 8225fdd593SJeykumar Sankaran timing->hsync_polarity = (mode->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0; 8325fdd593SJeykumar Sankaran timing->vsync_polarity = (mode->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0; 8425fdd593SJeykumar Sankaran timing->border_clr = 0; 8525fdd593SJeykumar Sankaran timing->underflow_clr = 0xff; 8625fdd593SJeykumar Sankaran timing->hsync_skew = mode->hskew; 8725fdd593SJeykumar Sankaran 8825fdd593SJeykumar Sankaran /* DSI controller cannot handle active-low sync signals. */ 89b6057cdaSJeykumar Sankaran if (phys_enc->hw_intf->cap->type == INTF_DSI) { 9025fdd593SJeykumar Sankaran timing->hsync_polarity = 0; 9125fdd593SJeykumar Sankaran timing->vsync_polarity = 0; 9225fdd593SJeykumar Sankaran } 9325fdd593SJeykumar Sankaran 94c943b494SChandan Uddaraju /* for DP/EDP, Shift timings to align it to bottom right */ 951c7b8ed7SDmitry Baryshkov if (phys_enc->hw_intf->cap->type == INTF_DP) { 96c943b494SChandan Uddaraju timing->h_back_porch += timing->h_front_porch; 97c943b494SChandan Uddaraju timing->h_front_porch = 0; 98c943b494SChandan Uddaraju timing->v_back_porch += timing->v_front_porch; 99c943b494SChandan Uddaraju timing->v_front_porch = 0; 100c943b494SChandan Uddaraju } 1013309a756SKuogee Hsieh 1023309a756SKuogee Hsieh timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent); 1033309a756SKuogee Hsieh 1043309a756SKuogee Hsieh /* 1053309a756SKuogee Hsieh * for DP, divide the horizonal parameters by 2 when 1063309a756SKuogee Hsieh * widebus is enabled 1073309a756SKuogee Hsieh */ 1083309a756SKuogee Hsieh if (phys_enc->hw_intf->cap->type == INTF_DP && timing->wide_bus_en) { 1093309a756SKuogee Hsieh timing->width = timing->width >> 1; 1103309a756SKuogee Hsieh timing->xres = timing->xres >> 1; 1113309a756SKuogee Hsieh timing->h_back_porch = timing->h_back_porch >> 1; 1123309a756SKuogee Hsieh timing->h_front_porch = timing->h_front_porch >> 1; 1133309a756SKuogee Hsieh timing->hsync_pulse_width = timing->hsync_pulse_width >> 1; 1143309a756SKuogee Hsieh } 11525fdd593SJeykumar Sankaran } 11625fdd593SJeykumar Sankaran 11758fba464SSean Paul static u32 get_horizontal_total(const struct intf_timing_params *timing) 11825fdd593SJeykumar Sankaran { 11925fdd593SJeykumar Sankaran u32 active = timing->xres; 12025fdd593SJeykumar Sankaran u32 inactive = 12125fdd593SJeykumar Sankaran timing->h_back_porch + timing->h_front_porch + 12225fdd593SJeykumar Sankaran timing->hsync_pulse_width; 12325fdd593SJeykumar Sankaran return active + inactive; 12425fdd593SJeykumar Sankaran } 12525fdd593SJeykumar Sankaran 12658fba464SSean Paul static u32 get_vertical_total(const struct intf_timing_params *timing) 12725fdd593SJeykumar Sankaran { 12825fdd593SJeykumar Sankaran u32 active = timing->yres; 12925fdd593SJeykumar Sankaran u32 inactive = 13025fdd593SJeykumar Sankaran timing->v_back_porch + timing->v_front_porch + 13125fdd593SJeykumar Sankaran timing->vsync_pulse_width; 13225fdd593SJeykumar Sankaran return active + inactive; 13325fdd593SJeykumar Sankaran } 13425fdd593SJeykumar Sankaran 13525fdd593SJeykumar Sankaran /* 13625fdd593SJeykumar Sankaran * programmable_fetch_get_num_lines: 13725fdd593SJeykumar Sankaran * Number of fetch lines in vertical front porch 13825fdd593SJeykumar Sankaran * @timing: Pointer to the intf timing information for the requested mode 13925fdd593SJeykumar Sankaran * 14025fdd593SJeykumar Sankaran * Returns the number of fetch lines in vertical front porch at which mdp 14125fdd593SJeykumar Sankaran * can start fetching the next frame. 14225fdd593SJeykumar Sankaran * 14325fdd593SJeykumar Sankaran * Number of needed prefetch lines is anything that cannot be absorbed in the 14425fdd593SJeykumar Sankaran * start of frame time (back porch + vsync pulse width). 14525fdd593SJeykumar Sankaran * 14625fdd593SJeykumar Sankaran * Some panels have very large VFP, however we only need a total number of 14725fdd593SJeykumar Sankaran * lines based on the chip worst case latencies. 14825fdd593SJeykumar Sankaran */ 14925fdd593SJeykumar Sankaran static u32 programmable_fetch_get_num_lines( 150b6057cdaSJeykumar Sankaran struct dpu_encoder_phys *phys_enc, 15125fdd593SJeykumar Sankaran const struct intf_timing_params *timing) 15225fdd593SJeykumar Sankaran { 15325fdd593SJeykumar Sankaran u32 worst_case_needed_lines = 154b6057cdaSJeykumar Sankaran phys_enc->hw_intf->cap->prog_fetch_lines_worst_case; 15525fdd593SJeykumar Sankaran u32 start_of_frame_lines = 15625fdd593SJeykumar Sankaran timing->v_back_porch + timing->vsync_pulse_width; 15725fdd593SJeykumar Sankaran u32 needed_vfp_lines = worst_case_needed_lines - start_of_frame_lines; 15825fdd593SJeykumar Sankaran u32 actual_vfp_lines = 0; 15925fdd593SJeykumar Sankaran 16025fdd593SJeykumar Sankaran /* Fetch must be outside active lines, otherwise undefined. */ 16125fdd593SJeykumar Sankaran if (start_of_frame_lines >= worst_case_needed_lines) { 162b6057cdaSJeykumar Sankaran DPU_DEBUG_VIDENC(phys_enc, 16325fdd593SJeykumar Sankaran "prog fetch is not needed, large vbp+vsw\n"); 16425fdd593SJeykumar Sankaran actual_vfp_lines = 0; 16525fdd593SJeykumar Sankaran } else if (timing->v_front_porch < needed_vfp_lines) { 16625fdd593SJeykumar Sankaran /* Warn fetch needed, but not enough porch in panel config */ 16725fdd593SJeykumar Sankaran pr_warn_once 16825fdd593SJeykumar Sankaran ("low vbp+vfp may lead to perf issues in some cases\n"); 169b6057cdaSJeykumar Sankaran DPU_DEBUG_VIDENC(phys_enc, 17025fdd593SJeykumar Sankaran "less vfp than fetch req, using entire vfp\n"); 17125fdd593SJeykumar Sankaran actual_vfp_lines = timing->v_front_porch; 17225fdd593SJeykumar Sankaran } else { 173b6057cdaSJeykumar Sankaran DPU_DEBUG_VIDENC(phys_enc, "room in vfp for needed prefetch\n"); 17425fdd593SJeykumar Sankaran actual_vfp_lines = needed_vfp_lines; 17525fdd593SJeykumar Sankaran } 17625fdd593SJeykumar Sankaran 177b6057cdaSJeykumar Sankaran DPU_DEBUG_VIDENC(phys_enc, 17825fdd593SJeykumar Sankaran "v_front_porch %u v_back_porch %u vsync_pulse_width %u\n", 17925fdd593SJeykumar Sankaran timing->v_front_porch, timing->v_back_porch, 18025fdd593SJeykumar Sankaran timing->vsync_pulse_width); 181b6057cdaSJeykumar Sankaran DPU_DEBUG_VIDENC(phys_enc, 18225fdd593SJeykumar Sankaran "wc_lines %u needed_vfp_lines %u actual_vfp_lines %u\n", 18325fdd593SJeykumar Sankaran worst_case_needed_lines, needed_vfp_lines, actual_vfp_lines); 18425fdd593SJeykumar Sankaran 18525fdd593SJeykumar Sankaran return actual_vfp_lines; 18625fdd593SJeykumar Sankaran } 18725fdd593SJeykumar Sankaran 18825fdd593SJeykumar Sankaran /* 18925fdd593SJeykumar Sankaran * programmable_fetch_config: Programs HW to prefetch lines by offsetting 19025fdd593SJeykumar Sankaran * the start of fetch into the vertical front porch for cases where the 19125fdd593SJeykumar Sankaran * vsync pulse width and vertical back porch time is insufficient 19225fdd593SJeykumar Sankaran * 19325fdd593SJeykumar Sankaran * Gets # of lines to pre-fetch, then calculate VSYNC counter value. 19425fdd593SJeykumar Sankaran * HW layer requires VSYNC counter of first pixel of tgt VFP line. 19525fdd593SJeykumar Sankaran * 19625fdd593SJeykumar Sankaran * @timing: Pointer to the intf timing information for the requested mode 19725fdd593SJeykumar Sankaran */ 19825fdd593SJeykumar Sankaran static void programmable_fetch_config(struct dpu_encoder_phys *phys_enc, 19925fdd593SJeykumar Sankaran const struct intf_timing_params *timing) 20025fdd593SJeykumar Sankaran { 20125fdd593SJeykumar Sankaran struct intf_prog_fetch f = { 0 }; 20225fdd593SJeykumar Sankaran u32 vfp_fetch_lines = 0; 20325fdd593SJeykumar Sankaran u32 horiz_total = 0; 20425fdd593SJeykumar Sankaran u32 vert_total = 0; 20525fdd593SJeykumar Sankaran u32 vfp_fetch_start_vsync_counter = 0; 20625fdd593SJeykumar Sankaran unsigned long lock_flags; 20725fdd593SJeykumar Sankaran 208b6057cdaSJeykumar Sankaran if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch)) 20925fdd593SJeykumar Sankaran return; 21025fdd593SJeykumar Sankaran 211b6057cdaSJeykumar Sankaran vfp_fetch_lines = programmable_fetch_get_num_lines(phys_enc, timing); 21225fdd593SJeykumar Sankaran if (vfp_fetch_lines) { 21325fdd593SJeykumar Sankaran vert_total = get_vertical_total(timing); 21425fdd593SJeykumar Sankaran horiz_total = get_horizontal_total(timing); 21525fdd593SJeykumar Sankaran vfp_fetch_start_vsync_counter = 21625fdd593SJeykumar Sankaran (vert_total - vfp_fetch_lines) * horiz_total + 1; 21725fdd593SJeykumar Sankaran f.enable = 1; 21825fdd593SJeykumar Sankaran f.fetch_start = vfp_fetch_start_vsync_counter; 21925fdd593SJeykumar Sankaran } 22025fdd593SJeykumar Sankaran 221b6057cdaSJeykumar Sankaran DPU_DEBUG_VIDENC(phys_enc, 22225fdd593SJeykumar Sankaran "vfp_fetch_lines %u vfp_fetch_start_vsync_counter %u\n", 22325fdd593SJeykumar Sankaran vfp_fetch_lines, vfp_fetch_start_vsync_counter); 22425fdd593SJeykumar Sankaran 22525fdd593SJeykumar Sankaran spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); 226b6057cdaSJeykumar Sankaran phys_enc->hw_intf->ops.setup_prg_fetch(phys_enc->hw_intf, &f); 22725fdd593SJeykumar Sankaran spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); 22825fdd593SJeykumar Sankaran } 22925fdd593SJeykumar Sankaran 23025fdd593SJeykumar Sankaran static void dpu_encoder_phys_vid_setup_timing_engine( 23125fdd593SJeykumar Sankaran struct dpu_encoder_phys *phys_enc) 23225fdd593SJeykumar Sankaran { 23325fdd593SJeykumar Sankaran struct drm_display_mode mode; 23425fdd593SJeykumar Sankaran struct intf_timing_params timing_params = { 0 }; 23525fdd593SJeykumar Sankaran const struct dpu_format *fmt = NULL; 23625fdd593SJeykumar Sankaran u32 fmt_fourcc = DRM_FORMAT_RGB888; 23725fdd593SJeykumar Sankaran unsigned long lock_flags; 23825fdd593SJeykumar Sankaran struct dpu_hw_intf_cfg intf_cfg = { 0 }; 23925fdd593SJeykumar Sankaran 240*17309a47SVille Syrjälä drm_mode_init(&mode, &phys_enc->cached_mode); 241*17309a47SVille Syrjälä 2425e7d4a84SDrew Davenport if (!phys_enc->hw_ctl->ops.setup_intf_cfg) { 24330801221SZheng Bin DPU_ERROR("invalid encoder %d\n", phys_enc != NULL); 24425fdd593SJeykumar Sankaran return; 24525fdd593SJeykumar Sankaran } 24625fdd593SJeykumar Sankaran 247b6057cdaSJeykumar Sankaran if (!phys_enc->hw_intf->ops.setup_timing_gen) { 24825fdd593SJeykumar Sankaran DPU_ERROR("timing engine setup is not supported\n"); 24925fdd593SJeykumar Sankaran return; 25025fdd593SJeykumar Sankaran } 25125fdd593SJeykumar Sankaran 252b6057cdaSJeykumar Sankaran DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n"); 25325fdd593SJeykumar Sankaran drm_mode_debug_printmodeline(&mode); 25425fdd593SJeykumar Sankaran 25525fdd593SJeykumar Sankaran if (phys_enc->split_role != ENC_ROLE_SOLO) { 25625fdd593SJeykumar Sankaran mode.hdisplay >>= 1; 25725fdd593SJeykumar Sankaran mode.htotal >>= 1; 25825fdd593SJeykumar Sankaran mode.hsync_start >>= 1; 25925fdd593SJeykumar Sankaran mode.hsync_end >>= 1; 26025fdd593SJeykumar Sankaran 261b6057cdaSJeykumar Sankaran DPU_DEBUG_VIDENC(phys_enc, 26225fdd593SJeykumar Sankaran "split_role %d, halve horizontal %d %d %d %d\n", 26325fdd593SJeykumar Sankaran phys_enc->split_role, 26425fdd593SJeykumar Sankaran mode.hdisplay, mode.htotal, 26525fdd593SJeykumar Sankaran mode.hsync_start, mode.hsync_end); 26625fdd593SJeykumar Sankaran } 26725fdd593SJeykumar Sankaran 268b6057cdaSJeykumar Sankaran drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params); 26925fdd593SJeykumar Sankaran 27025fdd593SJeykumar Sankaran fmt = dpu_get_dpu_format(fmt_fourcc); 271b6057cdaSJeykumar Sankaran DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc); 27225fdd593SJeykumar Sankaran 273b6057cdaSJeykumar Sankaran intf_cfg.intf = phys_enc->hw_intf->idx; 27425fdd593SJeykumar Sankaran intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID; 27525fdd593SJeykumar Sankaran intf_cfg.stream_sel = 0; /* Don't care value for video mode */ 27625fdd593SJeykumar Sankaran intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); 2773e79527aSDmitry Baryshkov if (phys_enc->hw_pp->merge_3d) 278dfa35bacSDmitry Baryshkov intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx; 27925fdd593SJeykumar Sankaran 28025fdd593SJeykumar Sankaran spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); 281b6057cdaSJeykumar Sankaran phys_enc->hw_intf->ops.setup_timing_gen(phys_enc->hw_intf, 28225fdd593SJeykumar Sankaran &timing_params, fmt); 28325fdd593SJeykumar Sankaran phys_enc->hw_ctl->ops.setup_intf_cfg(phys_enc->hw_ctl, &intf_cfg); 28473bfb790SKalyan Thota 28573bfb790SKalyan Thota /* setup which pp blk will connect to this intf */ 28673bfb790SKalyan Thota if (phys_enc->hw_intf->ops.bind_pingpong_blk) 28773bfb790SKalyan Thota phys_enc->hw_intf->ops.bind_pingpong_blk( 28873bfb790SKalyan Thota phys_enc->hw_intf, 28973bfb790SKalyan Thota true, 29073bfb790SKalyan Thota phys_enc->hw_pp->idx); 29173bfb790SKalyan Thota 292dfa35bacSDmitry Baryshkov if (phys_enc->hw_pp->merge_3d) 293dfa35bacSDmitry Baryshkov phys_enc->hw_pp->merge_3d->ops.setup_3d_mode(phys_enc->hw_pp->merge_3d, intf_cfg.mode_3d); 2943e79527aSDmitry Baryshkov 29525fdd593SJeykumar Sankaran spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); 29625fdd593SJeykumar Sankaran 29725fdd593SJeykumar Sankaran programmable_fetch_config(phys_enc, &timing_params); 29825fdd593SJeykumar Sankaran } 29925fdd593SJeykumar Sankaran 30025fdd593SJeykumar Sankaran static void dpu_encoder_phys_vid_vblank_irq(void *arg, int irq_idx) 30125fdd593SJeykumar Sankaran { 30225fdd593SJeykumar Sankaran struct dpu_encoder_phys *phys_enc = arg; 30325fdd593SJeykumar Sankaran struct dpu_hw_ctl *hw_ctl; 30425fdd593SJeykumar Sankaran unsigned long lock_flags; 30525fdd593SJeykumar Sankaran u32 flush_register = 0; 30625fdd593SJeykumar Sankaran 30725fdd593SJeykumar Sankaran hw_ctl = phys_enc->hw_ctl; 30825fdd593SJeykumar Sankaran 30925fdd593SJeykumar Sankaran DPU_ATRACE_BEGIN("vblank_irq"); 31025fdd593SJeykumar Sankaran 31125fdd593SJeykumar Sankaran if (phys_enc->parent_ops->handle_vblank_virt) 31225fdd593SJeykumar Sankaran phys_enc->parent_ops->handle_vblank_virt(phys_enc->parent, 31325fdd593SJeykumar Sankaran phys_enc); 31425fdd593SJeykumar Sankaran 3153c0f462dSLuo Jiaxing atomic_read(&phys_enc->pending_kickoff_cnt); 31625fdd593SJeykumar Sankaran 31725fdd593SJeykumar Sankaran /* 31825fdd593SJeykumar Sankaran * only decrement the pending flush count if we've actually flushed 31925fdd593SJeykumar Sankaran * hardware. due to sw irq latency, vblank may have already happened 32025fdd593SJeykumar Sankaran * so we need to double-check with hw that it accepted the flush bits 32125fdd593SJeykumar Sankaran */ 32225fdd593SJeykumar Sankaran spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); 32399beed68SDrew Davenport if (hw_ctl->ops.get_flush_register) 32425fdd593SJeykumar Sankaran flush_register = hw_ctl->ops.get_flush_register(hw_ctl); 32525fdd593SJeykumar Sankaran 3265f79e03bSSean Paul if (!(flush_register & hw_ctl->ops.get_pending_flush(hw_ctl))) 3273c0f462dSLuo Jiaxing atomic_add_unless(&phys_enc->pending_kickoff_cnt, -1, 0); 32825fdd593SJeykumar Sankaran spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); 32925fdd593SJeykumar Sankaran 33025fdd593SJeykumar Sankaran /* Signal any waiting atomic commit thread */ 33125fdd593SJeykumar Sankaran wake_up_all(&phys_enc->pending_kickoff_wq); 33241a52059SRob Clark 33341a52059SRob Clark phys_enc->parent_ops->handle_frame_done(phys_enc->parent, phys_enc, 33441a52059SRob Clark DPU_ENCODER_FRAME_EVENT_DONE); 33541a52059SRob Clark 33625fdd593SJeykumar Sankaran DPU_ATRACE_END("vblank_irq"); 33725fdd593SJeykumar Sankaran } 33825fdd593SJeykumar Sankaran 33925fdd593SJeykumar Sankaran static void dpu_encoder_phys_vid_underrun_irq(void *arg, int irq_idx) 34025fdd593SJeykumar Sankaran { 34125fdd593SJeykumar Sankaran struct dpu_encoder_phys *phys_enc = arg; 34225fdd593SJeykumar Sankaran 34325fdd593SJeykumar Sankaran if (phys_enc->parent_ops->handle_underrun_virt) 34425fdd593SJeykumar Sankaran phys_enc->parent_ops->handle_underrun_virt(phys_enc->parent, 34525fdd593SJeykumar Sankaran phys_enc); 34625fdd593SJeykumar Sankaran } 34725fdd593SJeykumar Sankaran 34825fdd593SJeykumar Sankaran static bool dpu_encoder_phys_vid_needs_single_flush( 34925fdd593SJeykumar Sankaran struct dpu_encoder_phys *phys_enc) 35025fdd593SJeykumar Sankaran { 3514e998517SJeykumar Sankaran return phys_enc->split_role != ENC_ROLE_SOLO; 35225fdd593SJeykumar Sankaran } 35325fdd593SJeykumar Sankaran 354764332bfSDmitry Baryshkov static void dpu_encoder_phys_vid_atomic_mode_set( 35525fdd593SJeykumar Sankaran struct dpu_encoder_phys *phys_enc, 356764332bfSDmitry Baryshkov struct drm_crtc_state *crtc_state, 357764332bfSDmitry Baryshkov struct drm_connector_state *conn_state) 35825fdd593SJeykumar Sankaran { 359b8c149e2SDmitry Baryshkov phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync; 360667e9985SDmitry Baryshkov 361b8c149e2SDmitry Baryshkov phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun; 36225fdd593SJeykumar Sankaran } 36325fdd593SJeykumar Sankaran 36425fdd593SJeykumar Sankaran static int dpu_encoder_phys_vid_control_vblank_irq( 36525fdd593SJeykumar Sankaran struct dpu_encoder_phys *phys_enc, 36625fdd593SJeykumar Sankaran bool enable) 36725fdd593SJeykumar Sankaran { 36825fdd593SJeykumar Sankaran int ret = 0; 36925fdd593SJeykumar Sankaran int refcount; 37025fdd593SJeykumar Sankaran 37125fdd593SJeykumar Sankaran refcount = atomic_read(&phys_enc->vblank_refcount); 37225fdd593SJeykumar Sankaran 37325fdd593SJeykumar Sankaran /* Slave encoders don't report vblank */ 37425fdd593SJeykumar Sankaran if (!dpu_encoder_phys_vid_is_master(phys_enc)) 37525fdd593SJeykumar Sankaran goto end; 37625fdd593SJeykumar Sankaran 37725fdd593SJeykumar Sankaran /* protect against negative */ 37825fdd593SJeykumar Sankaran if (!enable && refcount == 0) { 37925fdd593SJeykumar Sankaran ret = -EINVAL; 38025fdd593SJeykumar Sankaran goto end; 38125fdd593SJeykumar Sankaran } 38225fdd593SJeykumar Sankaran 383721c6e0cSStephen Boyd DRM_DEBUG_VBL("id:%u enable=%d/%d\n", DRMID(phys_enc->parent), enable, 38425fdd593SJeykumar Sankaran atomic_read(&phys_enc->vblank_refcount)); 38525fdd593SJeykumar Sankaran 38625fdd593SJeykumar Sankaran if (enable && atomic_inc_return(&phys_enc->vblank_refcount) == 1) 3876ee11c41SDmitry Baryshkov ret = dpu_core_irq_register_callback(phys_enc->dpu_kms, 388b8c149e2SDmitry Baryshkov phys_enc->irq[INTR_IDX_VSYNC], 389b8c149e2SDmitry Baryshkov dpu_encoder_phys_vid_vblank_irq, 390b8c149e2SDmitry Baryshkov phys_enc); 39125fdd593SJeykumar Sankaran else if (!enable && atomic_dec_return(&phys_enc->vblank_refcount) == 0) 3926ee11c41SDmitry Baryshkov ret = dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 393b8c149e2SDmitry Baryshkov phys_enc->irq[INTR_IDX_VSYNC]); 39425fdd593SJeykumar Sankaran 39525fdd593SJeykumar Sankaran end: 39625fdd593SJeykumar Sankaran if (ret) { 39725fdd593SJeykumar Sankaran DRM_ERROR("failed: id:%u intf:%d ret:%d enable:%d refcnt:%d\n", 39825fdd593SJeykumar Sankaran DRMID(phys_enc->parent), 399b6057cdaSJeykumar Sankaran phys_enc->hw_intf->idx - INTF_0, ret, enable, 40025fdd593SJeykumar Sankaran refcount); 40125fdd593SJeykumar Sankaran } 40225fdd593SJeykumar Sankaran return ret; 40325fdd593SJeykumar Sankaran } 40425fdd593SJeykumar Sankaran 40525fdd593SJeykumar Sankaran static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) 40625fdd593SJeykumar Sankaran { 40725fdd593SJeykumar Sankaran struct dpu_hw_ctl *ctl; 40825fdd593SJeykumar Sankaran 40925fdd593SJeykumar Sankaran ctl = phys_enc->hw_ctl; 410906216baSJeykumar Sankaran 411b6057cdaSJeykumar Sankaran DPU_DEBUG_VIDENC(phys_enc, "\n"); 41225fdd593SJeykumar Sankaran 413b6057cdaSJeykumar Sankaran if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing)) 41425fdd593SJeykumar Sankaran return; 41525fdd593SJeykumar Sankaran 416b6057cdaSJeykumar Sankaran dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx); 41725fdd593SJeykumar Sankaran 41825fdd593SJeykumar Sankaran dpu_encoder_phys_vid_setup_timing_engine(phys_enc); 41925fdd593SJeykumar Sankaran 42025fdd593SJeykumar Sankaran /* 42125fdd593SJeykumar Sankaran * For single flush cases (dual-ctl or pp-split), skip setting the 42225fdd593SJeykumar Sankaran * flush bit for the slave intf, since both intfs use same ctl 42325fdd593SJeykumar Sankaran * and HW will only flush the master. 42425fdd593SJeykumar Sankaran */ 42525fdd593SJeykumar Sankaran if (dpu_encoder_phys_vid_needs_single_flush(phys_enc) && 42625fdd593SJeykumar Sankaran !dpu_encoder_phys_vid_is_master(phys_enc)) 42725fdd593SJeykumar Sankaran goto skip_flush; 42825fdd593SJeykumar Sankaran 429d8199c85SDmitry Baryshkov ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx); 4303e79527aSDmitry Baryshkov if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d) 431dfa35bacSDmitry Baryshkov ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx); 43273bfb790SKalyan Thota 43325fdd593SJeykumar Sankaran skip_flush: 434b6057cdaSJeykumar Sankaran DPU_DEBUG_VIDENC(phys_enc, 435d8199c85SDmitry Baryshkov "update pending flush ctl %d intf %d\n", 436d8199c85SDmitry Baryshkov ctl->idx - CTL_0, phys_enc->hw_intf->idx); 43773bfb790SKalyan Thota 4382ec5b3dcSAbhinav Kumar atomic_set(&phys_enc->underrun_cnt, 0); 43925fdd593SJeykumar Sankaran 44025fdd593SJeykumar Sankaran /* ctl_flush & timing engine enable will be triggered by framework */ 44125fdd593SJeykumar Sankaran if (phys_enc->enable_state == DPU_ENC_DISABLED) 44225fdd593SJeykumar Sankaran phys_enc->enable_state = DPU_ENC_ENABLING; 44325fdd593SJeykumar Sankaran } 44425fdd593SJeykumar Sankaran 44525fdd593SJeykumar Sankaran static void dpu_encoder_phys_vid_destroy(struct dpu_encoder_phys *phys_enc) 44625fdd593SJeykumar Sankaran { 447b6057cdaSJeykumar Sankaran DPU_DEBUG_VIDENC(phys_enc, "\n"); 448366334a3SJeykumar Sankaran kfree(phys_enc); 44925fdd593SJeykumar Sankaran } 45025fdd593SJeykumar Sankaran 45141a52059SRob Clark static int dpu_encoder_phys_vid_wait_for_vblank( 45241a52059SRob Clark struct dpu_encoder_phys *phys_enc) 45325fdd593SJeykumar Sankaran { 45425fdd593SJeykumar Sankaran struct dpu_encoder_wait_info wait_info; 45525fdd593SJeykumar Sankaran int ret; 45625fdd593SJeykumar Sankaran 45725fdd593SJeykumar Sankaran wait_info.wq = &phys_enc->pending_kickoff_wq; 45825fdd593SJeykumar Sankaran wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt; 45925fdd593SJeykumar Sankaran wait_info.timeout_ms = KICKOFF_TIMEOUT_MS; 46025fdd593SJeykumar Sankaran 46125fdd593SJeykumar Sankaran if (!dpu_encoder_phys_vid_is_master(phys_enc)) { 46225fdd593SJeykumar Sankaran return 0; 46325fdd593SJeykumar Sankaran } 46425fdd593SJeykumar Sankaran 46525fdd593SJeykumar Sankaran /* Wait for kickoff to complete */ 4661e7ac595SDmitry Baryshkov ret = dpu_encoder_helper_wait_for_irq(phys_enc, 4671e7ac595SDmitry Baryshkov phys_enc->irq[INTR_IDX_VSYNC], 468b8c149e2SDmitry Baryshkov dpu_encoder_phys_vid_vblank_irq, 46925fdd593SJeykumar Sankaran &wait_info); 47025fdd593SJeykumar Sankaran 47125fdd593SJeykumar Sankaran if (ret == -ETIMEDOUT) { 47225fdd593SJeykumar Sankaran dpu_encoder_helper_report_irq_timeout(phys_enc, INTR_IDX_VSYNC); 47325fdd593SJeykumar Sankaran } 47425fdd593SJeykumar Sankaran 47541a52059SRob Clark return ret; 47625fdd593SJeykumar Sankaran } 47725fdd593SJeykumar Sankaran 478fe9df3f5SRob Clark static int dpu_encoder_phys_vid_wait_for_commit_done( 479fe9df3f5SRob Clark struct dpu_encoder_phys *phys_enc) 480fe9df3f5SRob Clark { 481fe9df3f5SRob Clark struct dpu_hw_ctl *hw_ctl = phys_enc->hw_ctl; 482fe9df3f5SRob Clark int ret; 483fe9df3f5SRob Clark 484fe9df3f5SRob Clark if (!hw_ctl) 485fe9df3f5SRob Clark return 0; 486fe9df3f5SRob Clark 487fe9df3f5SRob Clark ret = wait_event_timeout(phys_enc->pending_kickoff_wq, 488fe9df3f5SRob Clark (hw_ctl->ops.get_flush_register(hw_ctl) == 0), 489fe9df3f5SRob Clark msecs_to_jiffies(50)); 490fe9df3f5SRob Clark if (ret <= 0) { 491fe9df3f5SRob Clark DPU_ERROR("vblank timeout\n"); 492fe9df3f5SRob Clark return -ETIMEDOUT; 493fe9df3f5SRob Clark } 494fe9df3f5SRob Clark 495fe9df3f5SRob Clark return 0; 496fe9df3f5SRob Clark } 497fe9df3f5SRob Clark 49825fdd593SJeykumar Sankaran static void dpu_encoder_phys_vid_prepare_for_kickoff( 499d3db61caSBruce Wang struct dpu_encoder_phys *phys_enc) 50025fdd593SJeykumar Sankaran { 50125fdd593SJeykumar Sankaran struct dpu_hw_ctl *ctl; 50225fdd593SJeykumar Sankaran int rc; 5032ec5b3dcSAbhinav Kumar struct drm_encoder *drm_enc; 5042ec5b3dcSAbhinav Kumar 5052ec5b3dcSAbhinav Kumar drm_enc = phys_enc->parent; 50625fdd593SJeykumar Sankaran 50725fdd593SJeykumar Sankaran ctl = phys_enc->hw_ctl; 50899beed68SDrew Davenport if (!ctl->ops.wait_reset_status) 50925fdd593SJeykumar Sankaran return; 51025fdd593SJeykumar Sankaran 51125fdd593SJeykumar Sankaran /* 51225fdd593SJeykumar Sankaran * hw supports hardware initiated ctl reset, so before we kickoff a new 51325fdd593SJeykumar Sankaran * frame, need to check and wait for hw initiated ctl reset completion 51425fdd593SJeykumar Sankaran */ 51525fdd593SJeykumar Sankaran rc = ctl->ops.wait_reset_status(ctl); 51625fdd593SJeykumar Sankaran if (rc) { 517b6057cdaSJeykumar Sankaran DPU_ERROR_VIDENC(phys_enc, "ctl %d reset failure: %d\n", 51825fdd593SJeykumar Sankaran ctl->idx, rc); 5192ec5b3dcSAbhinav Kumar msm_disp_snapshot_state(drm_enc->dev); 5206ee11c41SDmitry Baryshkov dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 521b8c149e2SDmitry Baryshkov phys_enc->irq[INTR_IDX_VSYNC]); 52225fdd593SJeykumar Sankaran } 52325fdd593SJeykumar Sankaran } 52425fdd593SJeykumar Sankaran 52525fdd593SJeykumar Sankaran static void dpu_encoder_phys_vid_disable(struct dpu_encoder_phys *phys_enc) 52625fdd593SJeykumar Sankaran { 52725fdd593SJeykumar Sankaran unsigned long lock_flags; 52825fdd593SJeykumar Sankaran int ret; 52925fdd593SJeykumar Sankaran 5305e7d4a84SDrew Davenport if (!phys_enc->parent || !phys_enc->parent->dev) { 53125fdd593SJeykumar Sankaran DPU_ERROR("invalid encoder/device\n"); 53225fdd593SJeykumar Sankaran return; 53325fdd593SJeykumar Sankaran } 53425fdd593SJeykumar Sankaran 53599beed68SDrew Davenport if (!phys_enc->hw_intf) { 53625fdd593SJeykumar Sankaran DPU_ERROR("invalid hw_intf %d hw_ctl %d\n", 53730801221SZheng Bin phys_enc->hw_intf != NULL, phys_enc->hw_ctl != NULL); 53825fdd593SJeykumar Sankaran return; 53925fdd593SJeykumar Sankaran } 54025fdd593SJeykumar Sankaran 541b6057cdaSJeykumar Sankaran if (WARN_ON(!phys_enc->hw_intf->ops.enable_timing)) 54225fdd593SJeykumar Sankaran return; 54325fdd593SJeykumar Sankaran 54425fdd593SJeykumar Sankaran if (phys_enc->enable_state == DPU_ENC_DISABLED) { 54525fdd593SJeykumar Sankaran DPU_ERROR("already disabled\n"); 54625fdd593SJeykumar Sankaran return; 54725fdd593SJeykumar Sankaran } 54825fdd593SJeykumar Sankaran 54925fdd593SJeykumar Sankaran spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); 550b6057cdaSJeykumar Sankaran phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 0); 55125fdd593SJeykumar Sankaran if (dpu_encoder_phys_vid_is_master(phys_enc)) 55225fdd593SJeykumar Sankaran dpu_encoder_phys_inc_pending(phys_enc); 55325fdd593SJeykumar Sankaran spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); 55425fdd593SJeykumar Sankaran 55525fdd593SJeykumar Sankaran /* 55625fdd593SJeykumar Sankaran * Wait for a vsync so we know the ENABLE=0 latched before 55725fdd593SJeykumar Sankaran * the (connector) source of the vsync's gets disabled, 55825fdd593SJeykumar Sankaran * otherwise we end up in a funny state if we re-enable 55925fdd593SJeykumar Sankaran * before the disable latches, which results that some of 56025fdd593SJeykumar Sankaran * the settings changes for the new modeset (like new 56125fdd593SJeykumar Sankaran * scanout buffer) don't latch properly.. 56225fdd593SJeykumar Sankaran */ 56325fdd593SJeykumar Sankaran if (dpu_encoder_phys_vid_is_master(phys_enc)) { 56441a52059SRob Clark ret = dpu_encoder_phys_vid_wait_for_vblank(phys_enc); 56525fdd593SJeykumar Sankaran if (ret) { 56625fdd593SJeykumar Sankaran atomic_set(&phys_enc->pending_kickoff_cnt, 0); 56725fdd593SJeykumar Sankaran DRM_ERROR("wait disable failed: id:%u intf:%d ret:%d\n", 56825fdd593SJeykumar Sankaran DRMID(phys_enc->parent), 569b6057cdaSJeykumar Sankaran phys_enc->hw_intf->idx - INTF_0, ret); 57025fdd593SJeykumar Sankaran } 57125fdd593SJeykumar Sankaran } 57225fdd593SJeykumar Sankaran 57325fdd593SJeykumar Sankaran phys_enc->enable_state = DPU_ENC_DISABLED; 57425fdd593SJeykumar Sankaran } 57525fdd593SJeykumar Sankaran 57625fdd593SJeykumar Sankaran static void dpu_encoder_phys_vid_handle_post_kickoff( 57725fdd593SJeykumar Sankaran struct dpu_encoder_phys *phys_enc) 57825fdd593SJeykumar Sankaran { 57925fdd593SJeykumar Sankaran unsigned long lock_flags; 58025fdd593SJeykumar Sankaran 58125fdd593SJeykumar Sankaran /* 58225fdd593SJeykumar Sankaran * Video mode must flush CTL before enabling timing engine 58325fdd593SJeykumar Sankaran * Video encoders need to turn on their interfaces now 58425fdd593SJeykumar Sankaran */ 58525fdd593SJeykumar Sankaran if (phys_enc->enable_state == DPU_ENC_ENABLING) { 58625fdd593SJeykumar Sankaran trace_dpu_enc_phys_vid_post_kickoff(DRMID(phys_enc->parent), 587b6057cdaSJeykumar Sankaran phys_enc->hw_intf->idx - INTF_0); 58825fdd593SJeykumar Sankaran spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); 589b6057cdaSJeykumar Sankaran phys_enc->hw_intf->ops.enable_timing(phys_enc->hw_intf, 1); 59025fdd593SJeykumar Sankaran spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); 59125fdd593SJeykumar Sankaran phys_enc->enable_state = DPU_ENC_ENABLED; 59225fdd593SJeykumar Sankaran } 59325fdd593SJeykumar Sankaran } 59425fdd593SJeykumar Sankaran 59525fdd593SJeykumar Sankaran static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc, 59625fdd593SJeykumar Sankaran bool enable) 59725fdd593SJeykumar Sankaran { 59825fdd593SJeykumar Sankaran int ret; 59925fdd593SJeykumar Sankaran 60025fdd593SJeykumar Sankaran trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent), 601b6057cdaSJeykumar Sankaran phys_enc->hw_intf->idx - INTF_0, 60225fdd593SJeykumar Sankaran enable, 60325fdd593SJeykumar Sankaran atomic_read(&phys_enc->vblank_refcount)); 60425fdd593SJeykumar Sankaran 60525fdd593SJeykumar Sankaran if (enable) { 60625fdd593SJeykumar Sankaran ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true); 607667e9985SDmitry Baryshkov if (WARN_ON(ret)) 60825fdd593SJeykumar Sankaran return; 60925fdd593SJeykumar Sankaran 6106ee11c41SDmitry Baryshkov dpu_core_irq_register_callback(phys_enc->dpu_kms, 611b8c149e2SDmitry Baryshkov phys_enc->irq[INTR_IDX_UNDERRUN], 612b8c149e2SDmitry Baryshkov dpu_encoder_phys_vid_underrun_irq, 613b8c149e2SDmitry Baryshkov phys_enc); 61425fdd593SJeykumar Sankaran } else { 61525fdd593SJeykumar Sankaran dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false); 6166ee11c41SDmitry Baryshkov dpu_core_irq_unregister_callback(phys_enc->dpu_kms, 617b8c149e2SDmitry Baryshkov phys_enc->irq[INTR_IDX_UNDERRUN]); 61825fdd593SJeykumar Sankaran } 61925fdd593SJeykumar Sankaran } 62025fdd593SJeykumar Sankaran 62125fdd593SJeykumar Sankaran static int dpu_encoder_phys_vid_get_line_count( 62225fdd593SJeykumar Sankaran struct dpu_encoder_phys *phys_enc) 62325fdd593SJeykumar Sankaran { 62425fdd593SJeykumar Sankaran if (!dpu_encoder_phys_vid_is_master(phys_enc)) 62525fdd593SJeykumar Sankaran return -EINVAL; 62625fdd593SJeykumar Sankaran 627b6057cdaSJeykumar Sankaran if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_line_count) 62825fdd593SJeykumar Sankaran return -EINVAL; 62925fdd593SJeykumar Sankaran 630b6057cdaSJeykumar Sankaran return phys_enc->hw_intf->ops.get_line_count(phys_enc->hw_intf); 63125fdd593SJeykumar Sankaran } 63225fdd593SJeykumar Sankaran 63373743e72SKalyan Thota static int dpu_encoder_phys_vid_get_frame_count( 63473743e72SKalyan Thota struct dpu_encoder_phys *phys_enc) 63573743e72SKalyan Thota { 63673743e72SKalyan Thota struct intf_status s = {0}; 63773743e72SKalyan Thota u32 fetch_start = 0; 638*17309a47SVille Syrjälä struct drm_display_mode mode; 639*17309a47SVille Syrjälä 640*17309a47SVille Syrjälä drm_mode_init(&mode, &phys_enc->cached_mode); 64173743e72SKalyan Thota 64273743e72SKalyan Thota if (!dpu_encoder_phys_vid_is_master(phys_enc)) 64373743e72SKalyan Thota return -EINVAL; 64473743e72SKalyan Thota 64573743e72SKalyan Thota if (!phys_enc->hw_intf || !phys_enc->hw_intf->ops.get_status) 64673743e72SKalyan Thota return -EINVAL; 64773743e72SKalyan Thota 64873743e72SKalyan Thota phys_enc->hw_intf->ops.get_status(phys_enc->hw_intf, &s); 64973743e72SKalyan Thota 65073743e72SKalyan Thota if (s.is_prog_fetch_en && s.is_en) { 65173743e72SKalyan Thota fetch_start = mode.vtotal - (mode.vsync_start - mode.vdisplay); 65273743e72SKalyan Thota if ((s.line_count > fetch_start) && 65373743e72SKalyan Thota (s.line_count <= mode.vtotal)) 65473743e72SKalyan Thota return s.frame_count + 1; 65573743e72SKalyan Thota } 65673743e72SKalyan Thota 65773743e72SKalyan Thota return s.frame_count; 65873743e72SKalyan Thota } 65973743e72SKalyan Thota 66025fdd593SJeykumar Sankaran static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) 66125fdd593SJeykumar Sankaran { 66225fdd593SJeykumar Sankaran ops->is_master = dpu_encoder_phys_vid_is_master; 663764332bfSDmitry Baryshkov ops->atomic_mode_set = dpu_encoder_phys_vid_atomic_mode_set; 66425fdd593SJeykumar Sankaran ops->enable = dpu_encoder_phys_vid_enable; 66525fdd593SJeykumar Sankaran ops->disable = dpu_encoder_phys_vid_disable; 66625fdd593SJeykumar Sankaran ops->destroy = dpu_encoder_phys_vid_destroy; 66725fdd593SJeykumar Sankaran ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq; 668fe9df3f5SRob Clark ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done; 66925fdd593SJeykumar Sankaran ops->wait_for_vblank = dpu_encoder_phys_vid_wait_for_vblank; 67025fdd593SJeykumar Sankaran ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_vblank; 67125fdd593SJeykumar Sankaran ops->irq_control = dpu_encoder_phys_vid_irq_control; 67225fdd593SJeykumar Sankaran ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff; 67325fdd593SJeykumar Sankaran ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff; 67425fdd593SJeykumar Sankaran ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush; 67525fdd593SJeykumar Sankaran ops->get_line_count = dpu_encoder_phys_vid_get_line_count; 67673743e72SKalyan Thota ops->get_frame_count = dpu_encoder_phys_vid_get_frame_count; 67725fdd593SJeykumar Sankaran } 67825fdd593SJeykumar Sankaran 67925fdd593SJeykumar Sankaran struct dpu_encoder_phys *dpu_encoder_phys_vid_init( 68025fdd593SJeykumar Sankaran struct dpu_enc_phys_init_params *p) 68125fdd593SJeykumar Sankaran { 68225fdd593SJeykumar Sankaran struct dpu_encoder_phys *phys_enc = NULL; 683542a5db2SAmeer Hamza int i; 68425fdd593SJeykumar Sankaran 68525fdd593SJeykumar Sankaran if (!p) { 686542a5db2SAmeer Hamza DPU_ERROR("failed to create encoder due to invalid parameter\n"); 687542a5db2SAmeer Hamza return ERR_PTR(-EINVAL); 68825fdd593SJeykumar Sankaran } 68925fdd593SJeykumar Sankaran 690366334a3SJeykumar Sankaran phys_enc = kzalloc(sizeof(*phys_enc), GFP_KERNEL); 691366334a3SJeykumar Sankaran if (!phys_enc) { 692542a5db2SAmeer Hamza DPU_ERROR("failed to create encoder due to memory allocation error\n"); 693542a5db2SAmeer Hamza return ERR_PTR(-ENOMEM); 69425fdd593SJeykumar Sankaran } 69525fdd593SJeykumar Sankaran 69657250ca5SJeykumar Sankaran phys_enc->hw_mdptop = p->dpu_kms->hw_mdp; 69725fdd593SJeykumar Sankaran phys_enc->intf_idx = p->intf_idx; 69825fdd593SJeykumar Sankaran 699b6057cdaSJeykumar Sankaran DPU_DEBUG_VIDENC(phys_enc, "\n"); 70025fdd593SJeykumar Sankaran 70125fdd593SJeykumar Sankaran dpu_encoder_phys_vid_init_ops(&phys_enc->ops); 70225fdd593SJeykumar Sankaran phys_enc->parent = p->parent; 70325fdd593SJeykumar Sankaran phys_enc->parent_ops = p->parent_ops; 70425fdd593SJeykumar Sankaran phys_enc->dpu_kms = p->dpu_kms; 70525fdd593SJeykumar Sankaran phys_enc->split_role = p->split_role; 70625fdd593SJeykumar Sankaran phys_enc->intf_mode = INTF_MODE_VIDEO; 70725fdd593SJeykumar Sankaran phys_enc->enc_spinlock = p->enc_spinlock; 708b8c149e2SDmitry Baryshkov for (i = 0; i < ARRAY_SIZE(phys_enc->irq); i++) 709b8c149e2SDmitry Baryshkov phys_enc->irq[i] = -EINVAL; 71025fdd593SJeykumar Sankaran 71125fdd593SJeykumar Sankaran atomic_set(&phys_enc->vblank_refcount, 0); 71225fdd593SJeykumar Sankaran atomic_set(&phys_enc->pending_kickoff_cnt, 0); 71325fdd593SJeykumar Sankaran init_waitqueue_head(&phys_enc->pending_kickoff_wq); 71425fdd593SJeykumar Sankaran phys_enc->enable_state = DPU_ENC_DISABLED; 71525fdd593SJeykumar Sankaran 716b6057cdaSJeykumar Sankaran DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->intf_idx); 71725fdd593SJeykumar Sankaran 71825fdd593SJeykumar Sankaran return phys_enc; 71925fdd593SJeykumar Sankaran } 720