1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef __DPU_ENCODER_PHYS_H__ 8 #define __DPU_ENCODER_PHYS_H__ 9 10 #include <drm/drm_writeback.h> 11 #include <linux/jiffies.h> 12 13 #include "dpu_kms.h" 14 #include "dpu_hw_intf.h" 15 #include "dpu_hw_wb.h" 16 #include "dpu_hw_pingpong.h" 17 #include "dpu_hw_ctl.h" 18 #include "dpu_hw_top.h" 19 #include "dpu_encoder.h" 20 #include "dpu_crtc.h" 21 22 #define DPU_ENCODER_NAME_MAX 16 23 24 /* wait for at most 2 vsync for lowest refresh rate (24hz) */ 25 #define KICKOFF_TIMEOUT_MS 84 26 #define KICKOFF_TIMEOUT_JIFFIES msecs_to_jiffies(KICKOFF_TIMEOUT_MS) 27 28 /** 29 * enum dpu_enc_split_role - Role this physical encoder will play in a 30 * split-panel configuration, where one panel is master, and others slaves. 31 * Masters have extra responsibilities, like managing the VBLANK IRQ. 32 * @ENC_ROLE_SOLO: This is the one and only panel. This encoder is master. 33 * @ENC_ROLE_MASTER: This encoder is the master of a split panel config. 34 * @ENC_ROLE_SLAVE: This encoder is not the master of a split panel config. 35 */ 36 enum dpu_enc_split_role { 37 ENC_ROLE_SOLO, 38 ENC_ROLE_MASTER, 39 ENC_ROLE_SLAVE, 40 }; 41 42 /** 43 * enum dpu_enc_enable_state - current enabled state of the physical encoder 44 * @DPU_ENC_DISABLING: Encoder transitioning to disable state 45 * Events bounding transition are encoder type specific 46 * @DPU_ENC_DISABLED: Encoder is disabled 47 * @DPU_ENC_ENABLING: Encoder transitioning to enabled 48 * Events bounding transition are encoder type specific 49 * @DPU_ENC_ENABLED: Encoder is enabled 50 * @DPU_ENC_ERR_NEEDS_HW_RESET: Encoder is enabled, but requires a hw_reset 51 * to recover from a previous error 52 */ 53 enum dpu_enc_enable_state { 54 DPU_ENC_DISABLING, 55 DPU_ENC_DISABLED, 56 DPU_ENC_ENABLING, 57 DPU_ENC_ENABLED, 58 DPU_ENC_ERR_NEEDS_HW_RESET 59 }; 60 61 struct dpu_encoder_phys; 62 63 /** 64 * struct dpu_encoder_phys_ops - Interface the physical encoders provide to 65 * the containing virtual encoder. 66 * @late_register: DRM Call. Add Userspace interfaces, debugfs. 67 * @prepare_commit: MSM Atomic Call, start of atomic commit sequence 68 * @is_master: Whether this phys_enc is the current master 69 * encoder. Can be switched at enable time. Based 70 * on split_role and current mode (CMD/VID). 71 * @atomic_mode_set: DRM Call. Set a DRM mode. 72 * This likely caches the mode, for use at enable. 73 * @enable: DRM Call. Enable a DRM mode. 74 * @disable: DRM Call. Disable mode. 75 * @atomic_check: DRM Call. Atomic check new DRM state. 76 * @destroy: DRM Call. Destroy and release resources. 77 * @control_vblank_irq Register/Deregister for VBLANK IRQ 78 * @wait_for_commit_done: Wait for hardware to have flushed the 79 * current pending frames to hardware 80 * @wait_for_tx_complete: Wait for hardware to transfer the pixels 81 * to the panel 82 * @wait_for_vblank: Wait for VBLANK, for sub-driver internal use 83 * @prepare_for_kickoff: Do any work necessary prior to a kickoff 84 * For CMD encoder, may wait for previous tx done 85 * @handle_post_kickoff: Do any work necessary post-kickoff work 86 * @trigger_start: Process start event on physical encoder 87 * @needs_single_flush: Whether encoder slaves need to be flushed 88 * @irq_control: Handler to enable/disable all the encoder IRQs 89 * @prepare_idle_pc: phys encoder can update the vsync_enable status 90 * on idle power collapse prepare 91 * @restore: Restore all the encoder configs. 92 * @get_line_count: Obtain current vertical line count 93 */ 94 95 struct dpu_encoder_phys_ops { 96 int (*late_register)(struct dpu_encoder_phys *encoder, 97 struct dentry *debugfs_root); 98 void (*prepare_commit)(struct dpu_encoder_phys *encoder); 99 bool (*is_master)(struct dpu_encoder_phys *encoder); 100 void (*atomic_mode_set)(struct dpu_encoder_phys *encoder, 101 struct drm_crtc_state *crtc_state, 102 struct drm_connector_state *conn_state); 103 void (*enable)(struct dpu_encoder_phys *encoder); 104 void (*disable)(struct dpu_encoder_phys *encoder); 105 int (*atomic_check)(struct dpu_encoder_phys *encoder, 106 struct drm_crtc_state *crtc_state, 107 struct drm_connector_state *conn_state); 108 void (*destroy)(struct dpu_encoder_phys *encoder); 109 int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable); 110 int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc); 111 int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc); 112 int (*wait_for_vblank)(struct dpu_encoder_phys *phys_enc); 113 void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc); 114 void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc); 115 void (*trigger_start)(struct dpu_encoder_phys *phys_enc); 116 bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc); 117 void (*irq_control)(struct dpu_encoder_phys *phys, bool enable); 118 void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc); 119 void (*restore)(struct dpu_encoder_phys *phys); 120 int (*get_line_count)(struct dpu_encoder_phys *phys); 121 int (*get_frame_count)(struct dpu_encoder_phys *phys); 122 void (*prepare_wb_job)(struct dpu_encoder_phys *phys_enc, 123 struct drm_writeback_job *job); 124 void (*cleanup_wb_job)(struct dpu_encoder_phys *phys_enc, 125 struct drm_writeback_job *job); 126 bool (*is_valid_for_commit)(struct dpu_encoder_phys *phys_enc); 127 }; 128 129 /** 130 * enum dpu_intr_idx - dpu encoder interrupt index 131 * @INTR_IDX_VSYNC: Vsync interrupt for video mode panel 132 * @INTR_IDX_PINGPONG: Pingpong done unterrupt for cmd mode panel 133 * @INTR_IDX_UNDERRUN: Underrun unterrupt for video and cmd mode panel 134 * @INTR_IDX_RDPTR: Readpointer done unterrupt for cmd mode panel 135 * @INTR_IDX_WB_DONE: Writeback fone interrupt for virtual connector 136 */ 137 enum dpu_intr_idx { 138 INTR_IDX_VSYNC, 139 INTR_IDX_PINGPONG, 140 INTR_IDX_UNDERRUN, 141 INTR_IDX_CTL_START, 142 INTR_IDX_RDPTR, 143 INTR_IDX_WB_DONE, 144 INTR_IDX_MAX, 145 }; 146 147 /** 148 * struct dpu_encoder_phys - physical encoder that drives a single INTF block 149 * tied to a specific panel / sub-panel. Abstract type, sub-classed by 150 * phys_vid or phys_cmd for video mode or command mode encs respectively. 151 * @parent: Pointer to the containing virtual encoder 152 * @ops: Operations exposed to the virtual encoder 153 * @parent_ops: Callbacks exposed by the parent to the phys_enc 154 * @hw_mdptop: Hardware interface to the top registers 155 * @hw_ctl: Hardware interface to the ctl registers 156 * @hw_pp: Hardware interface to the ping pong registers 157 * @hw_intf: Hardware interface to the intf registers 158 * @hw_wb: Hardware interface to the wb registers 159 * @dpu_kms: Pointer to the dpu_kms top level 160 * @cached_mode: DRM mode cached at mode_set time, acted on in enable 161 * @enabled: Whether the encoder has enabled and running a mode 162 * @split_role: Role to play in a split-panel configuration 163 * @intf_mode: Interface mode 164 * @intf_idx: Interface index on dpu hardware 165 * @wb_idx: Writeback index on dpu hardware 166 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes 167 * @enable_state: Enable state tracking 168 * @vblank_refcount: Reference count of vblank request 169 * @vsync_cnt: Vsync count for the physical encoder 170 * @underrun_cnt: Underrun count for the physical encoder 171 * @pending_kickoff_cnt: Atomic counter tracking the number of kickoffs 172 * vs. the number of done/vblank irqs. Should hover 173 * between 0-2 Incremented when a new kickoff is 174 * scheduled. Decremented in irq handler 175 * @pending_ctlstart_cnt: Atomic counter tracking the number of ctl start 176 * pending. 177 * @pending_kickoff_wq: Wait queue for blocking until kickoff completes 178 * @irq: IRQ indices 179 */ 180 struct dpu_encoder_phys { 181 struct drm_encoder *parent; 182 struct dpu_encoder_phys_ops ops; 183 struct dpu_hw_mdp *hw_mdptop; 184 struct dpu_hw_ctl *hw_ctl; 185 struct dpu_hw_pingpong *hw_pp; 186 struct dpu_hw_intf *hw_intf; 187 struct dpu_hw_wb *hw_wb; 188 struct dpu_kms *dpu_kms; 189 struct drm_display_mode cached_mode; 190 enum dpu_enc_split_role split_role; 191 enum dpu_intf_mode intf_mode; 192 enum dpu_intf intf_idx; 193 enum dpu_wb wb_idx; 194 spinlock_t *enc_spinlock; 195 enum dpu_enc_enable_state enable_state; 196 atomic_t vblank_refcount; 197 atomic_t vsync_cnt; 198 atomic_t underrun_cnt; 199 atomic_t pending_ctlstart_cnt; 200 atomic_t pending_kickoff_cnt; 201 wait_queue_head_t pending_kickoff_wq; 202 int irq[INTR_IDX_MAX]; 203 }; 204 205 static inline int dpu_encoder_phys_inc_pending(struct dpu_encoder_phys *phys) 206 { 207 atomic_inc_return(&phys->pending_ctlstart_cnt); 208 return atomic_inc_return(&phys->pending_kickoff_cnt); 209 } 210 211 /** 212 * struct dpu_encoder_phys_wb - sub-class of dpu_encoder_phys to handle command 213 * mode specific operations 214 * @base: Baseclass physical encoder structure 215 * @wbirq_refcount: Reference count of writeback interrupt 216 * @wb_done_timeout_cnt: number of wb done irq timeout errors 217 * @wb_cfg: writeback block config to store fb related details 218 * @wb_conn: backpointer to writeback connector 219 * @wb_job: backpointer to current writeback job 220 * @dest: dpu buffer layout for current writeback output buffer 221 */ 222 struct dpu_encoder_phys_wb { 223 struct dpu_encoder_phys base; 224 atomic_t wbirq_refcount; 225 int wb_done_timeout_cnt; 226 struct dpu_hw_wb_cfg wb_cfg; 227 struct drm_writeback_connector *wb_conn; 228 struct drm_writeback_job *wb_job; 229 struct dpu_hw_fmt_layout dest; 230 }; 231 232 /** 233 * struct dpu_encoder_phys_cmd - sub-class of dpu_encoder_phys to handle command 234 * mode specific operations 235 * @base: Baseclass physical encoder structure 236 * @intf_idx: Intf Block index used by this phys encoder 237 * @stream_sel: Stream selection for multi-stream interfaces 238 * @serialize_wait4pp: serialize wait4pp feature waits for pp_done interrupt 239 * after ctl_start instead of before next frame kickoff 240 * @pp_timeout_report_cnt: number of pingpong done irq timeout errors 241 * @pending_vblank_cnt: Atomic counter tracking pending wait for VBLANK 242 * @pending_vblank_wq: Wait queue for blocking until VBLANK received 243 */ 244 struct dpu_encoder_phys_cmd { 245 struct dpu_encoder_phys base; 246 int stream_sel; 247 bool serialize_wait4pp; 248 int pp_timeout_report_cnt; 249 atomic_t pending_vblank_cnt; 250 wait_queue_head_t pending_vblank_wq; 251 }; 252 253 /** 254 * struct dpu_enc_phys_init_params - initialization parameters for phys encs 255 * @dpu_kms: Pointer to the dpu_kms top level 256 * @parent: Pointer to the containing virtual encoder 257 * @parent_ops: Callbacks exposed by the parent to the phys_enc 258 * @split_role: Role to play in a split-panel configuration 259 * @intf_idx: Interface index this phys_enc will control 260 * @wb_idx: Writeback index this phys_enc will control 261 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes 262 */ 263 struct dpu_enc_phys_init_params { 264 struct dpu_kms *dpu_kms; 265 struct drm_encoder *parent; 266 enum dpu_enc_split_role split_role; 267 enum dpu_intf intf_idx; 268 enum dpu_wb wb_idx; 269 spinlock_t *enc_spinlock; 270 }; 271 272 /** 273 * dpu_encoder_wait_info - container for passing arguments to irq wait functions 274 * @wq: wait queue structure 275 * @atomic_cnt: wait until atomic_cnt equals zero 276 * @timeout_ms: timeout value in milliseconds 277 */ 278 struct dpu_encoder_wait_info { 279 wait_queue_head_t *wq; 280 atomic_t *atomic_cnt; 281 s64 timeout_ms; 282 }; 283 284 /** 285 * dpu_encoder_phys_vid_init - Construct a new video mode physical encoder 286 * @p: Pointer to init params structure 287 * Return: Error code or newly allocated encoder 288 */ 289 struct dpu_encoder_phys *dpu_encoder_phys_vid_init( 290 struct dpu_enc_phys_init_params *p); 291 292 /** 293 * dpu_encoder_phys_cmd_init - Construct a new command mode physical encoder 294 * @p: Pointer to init params structure 295 * Return: Error code or newly allocated encoder 296 */ 297 struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( 298 struct dpu_enc_phys_init_params *p); 299 300 /** 301 * dpu_encoder_phys_wb_init - initialize writeback encoder 302 * @init: Pointer to init info structure with initialization params 303 */ 304 struct dpu_encoder_phys *dpu_encoder_phys_wb_init( 305 struct dpu_enc_phys_init_params *p); 306 307 /** 308 * dpu_encoder_helper_trigger_start - control start helper function 309 * This helper function may be optionally specified by physical 310 * encoders if they require ctl_start triggering. 311 * @phys_enc: Pointer to physical encoder structure 312 */ 313 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc); 314 315 static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( 316 struct dpu_encoder_phys *phys_enc) 317 { 318 struct dpu_crtc_state *dpu_cstate; 319 320 if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING) 321 return BLEND_3D_NONE; 322 323 dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state); 324 325 /* Use merge_3d unless DSC MERGE topology is used */ 326 if (phys_enc->split_role == ENC_ROLE_SOLO && 327 dpu_cstate->num_mixers == CRTC_DUAL_MIXERS && 328 !dpu_encoder_use_dsc_merge(phys_enc->parent)) 329 return BLEND_3D_H_ROW_INT; 330 331 return BLEND_3D_NONE; 332 } 333 334 /** 335 * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder 336 * This helper function is used by physical encoder to get DSC blocks mask 337 * used for this encoder. 338 * @phys_enc: Pointer to physical encoder structure 339 */ 340 unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc); 341 342 /** 343 * dpu_encoder_helper_split_config - split display configuration helper function 344 * This helper function may be used by physical encoders to configure 345 * the split display related registers. 346 * @phys_enc: Pointer to physical encoder structure 347 * @interface: enum dpu_intf setting 348 */ 349 void dpu_encoder_helper_split_config( 350 struct dpu_encoder_phys *phys_enc, 351 enum dpu_intf interface); 352 353 /** 354 * dpu_encoder_helper_report_irq_timeout - utility to report error that irq has 355 * timed out, including reporting frame error event to crtc and debug dump 356 * @phys_enc: Pointer to physical encoder structure 357 * @intr_idx: Failing interrupt index 358 */ 359 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 360 enum dpu_intr_idx intr_idx); 361 362 /** 363 * dpu_encoder_helper_wait_for_irq - utility to wait on an irq. 364 * note: will call dpu_encoder_helper_wait_for_irq on timeout 365 * @phys_enc: Pointer to physical encoder structure 366 * @irq: IRQ index 367 * @func: IRQ callback to be called in case of timeout 368 * @wait_info: wait info struct 369 * @Return: 0 or -ERROR 370 */ 371 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, 372 int irq, 373 void (*func)(void *arg, int irq_idx), 374 struct dpu_encoder_wait_info *wait_info); 375 376 /** 377 * dpu_encoder_helper_phys_cleanup - helper to cleanup dpu pipeline 378 * @phys_enc: Pointer to physical encoder structure 379 */ 380 void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc); 381 382 /** 383 * dpu_encoder_vblank_callback - Notify virtual encoder of vblank IRQ reception 384 * @drm_enc: Pointer to drm encoder structure 385 * @phys_enc: Pointer to physical encoder 386 * Note: This is called from IRQ handler context. 387 */ 388 void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc, 389 struct dpu_encoder_phys *phy_enc); 390 391 /** dpu_encoder_underrun_callback - Notify virtual encoder of underrun IRQ reception 392 * @drm_enc: Pointer to drm encoder structure 393 * @phys_enc: Pointer to physical encoder 394 * Note: This is called from IRQ handler context. 395 */ 396 void dpu_encoder_underrun_callback(struct drm_encoder *drm_enc, 397 struct dpu_encoder_phys *phy_enc); 398 399 /** dpu_encoder_frame_done_callback -- Notify virtual encoder that this phys encoder completes last request frame 400 * @drm_enc: Pointer to drm encoder structure 401 * @phys_enc: Pointer to physical encoder 402 * @event: Event to process 403 */ 404 void dpu_encoder_frame_done_callback( 405 struct drm_encoder *drm_enc, 406 struct dpu_encoder_phys *ready_phys, u32 event); 407 408 #endif /* __dpu_encoder_phys_H__ */ 409