1 /* 2 * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #ifndef __DPU_ENCODER_PHYS_H__ 16 #define __DPU_ENCODER_PHYS_H__ 17 18 #include <linux/jiffies.h> 19 20 #include "dpu_kms.h" 21 #include "dpu_hw_intf.h" 22 #include "dpu_hw_pingpong.h" 23 #include "dpu_hw_ctl.h" 24 #include "dpu_hw_top.h" 25 #include "dpu_encoder.h" 26 #include "dpu_crtc.h" 27 28 #define DPU_ENCODER_NAME_MAX 16 29 30 /* wait for at most 2 vsync for lowest refresh rate (24hz) */ 31 #define KICKOFF_TIMEOUT_MS 84 32 #define KICKOFF_TIMEOUT_JIFFIES msecs_to_jiffies(KICKOFF_TIMEOUT_MS) 33 34 /** 35 * enum dpu_enc_split_role - Role this physical encoder will play in a 36 * split-panel configuration, where one panel is master, and others slaves. 37 * Masters have extra responsibilities, like managing the VBLANK IRQ. 38 * @ENC_ROLE_SOLO: This is the one and only panel. This encoder is master. 39 * @ENC_ROLE_MASTER: This encoder is the master of a split panel config. 40 * @ENC_ROLE_SLAVE: This encoder is not the master of a split panel config. 41 */ 42 enum dpu_enc_split_role { 43 ENC_ROLE_SOLO, 44 ENC_ROLE_MASTER, 45 ENC_ROLE_SLAVE, 46 }; 47 48 /** 49 * enum dpu_enc_enable_state - current enabled state of the physical encoder 50 * @DPU_ENC_DISABLING: Encoder transitioning to disable state 51 * Events bounding transition are encoder type specific 52 * @DPU_ENC_DISABLED: Encoder is disabled 53 * @DPU_ENC_ENABLING: Encoder transitioning to enabled 54 * Events bounding transition are encoder type specific 55 * @DPU_ENC_ENABLED: Encoder is enabled 56 * @DPU_ENC_ERR_NEEDS_HW_RESET: Encoder is enabled, but requires a hw_reset 57 * to recover from a previous error 58 */ 59 enum dpu_enc_enable_state { 60 DPU_ENC_DISABLING, 61 DPU_ENC_DISABLED, 62 DPU_ENC_ENABLING, 63 DPU_ENC_ENABLED, 64 DPU_ENC_ERR_NEEDS_HW_RESET 65 }; 66 67 struct dpu_encoder_phys; 68 69 /** 70 * struct dpu_encoder_virt_ops - Interface the containing virtual encoder 71 * provides for the physical encoders to use to callback. 72 * @handle_vblank_virt: Notify virtual encoder of vblank IRQ reception 73 * Note: This is called from IRQ handler context. 74 * @handle_underrun_virt: Notify virtual encoder of underrun IRQ reception 75 * Note: This is called from IRQ handler context. 76 * @handle_frame_done: Notify virtual encoder that this phys encoder 77 * completes last request frame. 78 */ 79 struct dpu_encoder_virt_ops { 80 void (*handle_vblank_virt)(struct drm_encoder *, 81 struct dpu_encoder_phys *phys); 82 void (*handle_underrun_virt)(struct drm_encoder *, 83 struct dpu_encoder_phys *phys); 84 void (*handle_frame_done)(struct drm_encoder *, 85 struct dpu_encoder_phys *phys, u32 event); 86 }; 87 88 /** 89 * struct dpu_encoder_phys_ops - Interface the physical encoders provide to 90 * the containing virtual encoder. 91 * @late_register: DRM Call. Add Userspace interfaces, debugfs. 92 * @prepare_commit: MSM Atomic Call, start of atomic commit sequence 93 * @is_master: Whether this phys_enc is the current master 94 * encoder. Can be switched at enable time. Based 95 * on split_role and current mode (CMD/VID). 96 * @mode_fixup: DRM Call. Fixup a DRM mode. 97 * @mode_set: DRM Call. Set a DRM mode. 98 * This likely caches the mode, for use at enable. 99 * @enable: DRM Call. Enable a DRM mode. 100 * @disable: DRM Call. Disable mode. 101 * @atomic_check: DRM Call. Atomic check new DRM state. 102 * @destroy: DRM Call. Destroy and release resources. 103 * @get_hw_resources: Populate the structure with the hardware 104 * resources that this phys_enc is using. 105 * Expect no overlap between phys_encs. 106 * @control_vblank_irq Register/Deregister for VBLANK IRQ 107 * @wait_for_commit_done: Wait for hardware to have flushed the 108 * current pending frames to hardware 109 * @wait_for_tx_complete: Wait for hardware to transfer the pixels 110 * to the panel 111 * @wait_for_vblank: Wait for VBLANK, for sub-driver internal use 112 * @prepare_for_kickoff: Do any work necessary prior to a kickoff 113 * For CMD encoder, may wait for previous tx done 114 * @handle_post_kickoff: Do any work necessary post-kickoff work 115 * @trigger_start: Process start event on physical encoder 116 * @needs_single_flush: Whether encoder slaves need to be flushed 117 * @irq_control: Handler to enable/disable all the encoder IRQs 118 * @prepare_idle_pc: phys encoder can update the vsync_enable status 119 * on idle power collapse prepare 120 * @restore: Restore all the encoder configs. 121 * @get_line_count: Obtain current vertical line count 122 */ 123 124 struct dpu_encoder_phys_ops { 125 int (*late_register)(struct dpu_encoder_phys *encoder, 126 struct dentry *debugfs_root); 127 void (*prepare_commit)(struct dpu_encoder_phys *encoder); 128 bool (*is_master)(struct dpu_encoder_phys *encoder); 129 bool (*mode_fixup)(struct dpu_encoder_phys *encoder, 130 const struct drm_display_mode *mode, 131 struct drm_display_mode *adjusted_mode); 132 void (*mode_set)(struct dpu_encoder_phys *encoder, 133 struct drm_display_mode *mode, 134 struct drm_display_mode *adjusted_mode); 135 void (*enable)(struct dpu_encoder_phys *encoder); 136 void (*disable)(struct dpu_encoder_phys *encoder); 137 int (*atomic_check)(struct dpu_encoder_phys *encoder, 138 struct drm_crtc_state *crtc_state, 139 struct drm_connector_state *conn_state); 140 void (*destroy)(struct dpu_encoder_phys *encoder); 141 void (*get_hw_resources)(struct dpu_encoder_phys *encoder, 142 struct dpu_encoder_hw_resources *hw_res); 143 int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable); 144 int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc); 145 int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc); 146 int (*wait_for_vblank)(struct dpu_encoder_phys *phys_enc); 147 void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc); 148 void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc); 149 void (*trigger_start)(struct dpu_encoder_phys *phys_enc); 150 bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc); 151 void (*irq_control)(struct dpu_encoder_phys *phys, bool enable); 152 void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc); 153 void (*restore)(struct dpu_encoder_phys *phys); 154 int (*get_line_count)(struct dpu_encoder_phys *phys); 155 }; 156 157 /** 158 * enum dpu_intr_idx - dpu encoder interrupt index 159 * @INTR_IDX_VSYNC: Vsync interrupt for video mode panel 160 * @INTR_IDX_PINGPONG: Pingpong done unterrupt for cmd mode panel 161 * @INTR_IDX_UNDERRUN: Underrun unterrupt for video and cmd mode panel 162 * @INTR_IDX_RDPTR: Readpointer done unterrupt for cmd mode panel 163 */ 164 enum dpu_intr_idx { 165 INTR_IDX_VSYNC, 166 INTR_IDX_PINGPONG, 167 INTR_IDX_UNDERRUN, 168 INTR_IDX_CTL_START, 169 INTR_IDX_RDPTR, 170 INTR_IDX_MAX, 171 }; 172 173 /** 174 * dpu_encoder_irq - tracking structure for interrupts 175 * @name: string name of interrupt 176 * @intr_type: Encoder interrupt type 177 * @intr_idx: Encoder interrupt enumeration 178 * @hw_idx: HW Block ID 179 * @irq_idx: IRQ interface lookup index from DPU IRQ framework 180 * will be -EINVAL if IRQ is not registered 181 * @irq_cb: interrupt callback 182 */ 183 struct dpu_encoder_irq { 184 const char *name; 185 enum dpu_intr_type intr_type; 186 enum dpu_intr_idx intr_idx; 187 int hw_idx; 188 int irq_idx; 189 struct dpu_irq_callback cb; 190 }; 191 192 /** 193 * struct dpu_encoder_phys - physical encoder that drives a single INTF block 194 * tied to a specific panel / sub-panel. Abstract type, sub-classed by 195 * phys_vid or phys_cmd for video mode or command mode encs respectively. 196 * @parent: Pointer to the containing virtual encoder 197 * @connector: If a mode is set, cached pointer to the active connector 198 * @ops: Operations exposed to the virtual encoder 199 * @parent_ops: Callbacks exposed by the parent to the phys_enc 200 * @hw_mdptop: Hardware interface to the top registers 201 * @hw_ctl: Hardware interface to the ctl registers 202 * @hw_pp: Hardware interface to the ping pong registers 203 * @hw_intf: Hardware interface to the intf registers 204 * @dpu_kms: Pointer to the dpu_kms top level 205 * @cached_mode: DRM mode cached at mode_set time, acted on in enable 206 * @enabled: Whether the encoder has enabled and running a mode 207 * @split_role: Role to play in a split-panel configuration 208 * @intf_mode: Interface mode 209 * @intf_idx: Interface index on dpu hardware 210 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes 211 * @enable_state: Enable state tracking 212 * @vblank_refcount: Reference count of vblank request 213 * @vsync_cnt: Vsync count for the physical encoder 214 * @underrun_cnt: Underrun count for the physical encoder 215 * @pending_kickoff_cnt: Atomic counter tracking the number of kickoffs 216 * vs. the number of done/vblank irqs. Should hover 217 * between 0-2 Incremented when a new kickoff is 218 * scheduled. Decremented in irq handler 219 * @pending_ctlstart_cnt: Atomic counter tracking the number of ctl start 220 * pending. 221 * @pending_kickoff_wq: Wait queue for blocking until kickoff completes 222 * @irq: IRQ tracking structures 223 */ 224 struct dpu_encoder_phys { 225 struct drm_encoder *parent; 226 struct drm_connector *connector; 227 struct dpu_encoder_phys_ops ops; 228 const struct dpu_encoder_virt_ops *parent_ops; 229 struct dpu_hw_mdp *hw_mdptop; 230 struct dpu_hw_ctl *hw_ctl; 231 struct dpu_hw_pingpong *hw_pp; 232 struct dpu_hw_intf *hw_intf; 233 struct dpu_kms *dpu_kms; 234 struct drm_display_mode cached_mode; 235 enum dpu_enc_split_role split_role; 236 enum dpu_intf_mode intf_mode; 237 enum dpu_intf intf_idx; 238 spinlock_t *enc_spinlock; 239 enum dpu_enc_enable_state enable_state; 240 atomic_t vblank_refcount; 241 atomic_t vsync_cnt; 242 atomic_t underrun_cnt; 243 atomic_t pending_ctlstart_cnt; 244 atomic_t pending_kickoff_cnt; 245 wait_queue_head_t pending_kickoff_wq; 246 struct dpu_encoder_irq irq[INTR_IDX_MAX]; 247 }; 248 249 static inline int dpu_encoder_phys_inc_pending(struct dpu_encoder_phys *phys) 250 { 251 atomic_inc_return(&phys->pending_ctlstart_cnt); 252 return atomic_inc_return(&phys->pending_kickoff_cnt); 253 } 254 255 /** 256 * struct dpu_encoder_phys_cmd - sub-class of dpu_encoder_phys to handle command 257 * mode specific operations 258 * @base: Baseclass physical encoder structure 259 * @intf_idx: Intf Block index used by this phys encoder 260 * @stream_sel: Stream selection for multi-stream interfaces 261 * @serialize_wait4pp: serialize wait4pp feature waits for pp_done interrupt 262 * after ctl_start instead of before next frame kickoff 263 * @pp_timeout_report_cnt: number of pingpong done irq timeout errors 264 * @pending_vblank_cnt: Atomic counter tracking pending wait for VBLANK 265 * @pending_vblank_wq: Wait queue for blocking until VBLANK received 266 */ 267 struct dpu_encoder_phys_cmd { 268 struct dpu_encoder_phys base; 269 int stream_sel; 270 bool serialize_wait4pp; 271 int pp_timeout_report_cnt; 272 atomic_t pending_vblank_cnt; 273 wait_queue_head_t pending_vblank_wq; 274 }; 275 276 /** 277 * struct dpu_enc_phys_init_params - initialization parameters for phys encs 278 * @dpu_kms: Pointer to the dpu_kms top level 279 * @parent: Pointer to the containing virtual encoder 280 * @parent_ops: Callbacks exposed by the parent to the phys_enc 281 * @split_role: Role to play in a split-panel configuration 282 * @intf_idx: Interface index this phys_enc will control 283 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes 284 */ 285 struct dpu_enc_phys_init_params { 286 struct dpu_kms *dpu_kms; 287 struct drm_encoder *parent; 288 const struct dpu_encoder_virt_ops *parent_ops; 289 enum dpu_enc_split_role split_role; 290 enum dpu_intf intf_idx; 291 spinlock_t *enc_spinlock; 292 }; 293 294 /** 295 * dpu_encoder_wait_info - container for passing arguments to irq wait functions 296 * @wq: wait queue structure 297 * @atomic_cnt: wait until atomic_cnt equals zero 298 * @timeout_ms: timeout value in milliseconds 299 */ 300 struct dpu_encoder_wait_info { 301 wait_queue_head_t *wq; 302 atomic_t *atomic_cnt; 303 s64 timeout_ms; 304 }; 305 306 /** 307 * dpu_encoder_phys_vid_init - Construct a new video mode physical encoder 308 * @p: Pointer to init params structure 309 * Return: Error code or newly allocated encoder 310 */ 311 struct dpu_encoder_phys *dpu_encoder_phys_vid_init( 312 struct dpu_enc_phys_init_params *p); 313 314 /** 315 * dpu_encoder_phys_cmd_init - Construct a new command mode physical encoder 316 * @p: Pointer to init params structure 317 * Return: Error code or newly allocated encoder 318 */ 319 struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( 320 struct dpu_enc_phys_init_params *p); 321 322 /** 323 * dpu_encoder_helper_trigger_start - control start helper function 324 * This helper function may be optionally specified by physical 325 * encoders if they require ctl_start triggering. 326 * @phys_enc: Pointer to physical encoder structure 327 */ 328 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc); 329 330 static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( 331 struct dpu_encoder_phys *phys_enc) 332 { 333 struct dpu_crtc_state *dpu_cstate; 334 335 if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING) 336 return BLEND_3D_NONE; 337 338 dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state); 339 340 if (phys_enc->split_role == ENC_ROLE_SOLO && 341 dpu_cstate->num_mixers == CRTC_DUAL_MIXERS) 342 return BLEND_3D_H_ROW_INT; 343 344 return BLEND_3D_NONE; 345 } 346 347 /** 348 * dpu_encoder_helper_split_config - split display configuration helper function 349 * This helper function may be used by physical encoders to configure 350 * the split display related registers. 351 * @phys_enc: Pointer to physical encoder structure 352 * @interface: enum dpu_intf setting 353 */ 354 void dpu_encoder_helper_split_config( 355 struct dpu_encoder_phys *phys_enc, 356 enum dpu_intf interface); 357 358 /** 359 * dpu_encoder_helper_report_irq_timeout - utility to report error that irq has 360 * timed out, including reporting frame error event to crtc and debug dump 361 * @phys_enc: Pointer to physical encoder structure 362 * @intr_idx: Failing interrupt index 363 */ 364 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 365 enum dpu_intr_idx intr_idx); 366 367 /** 368 * dpu_encoder_helper_wait_for_irq - utility to wait on an irq. 369 * note: will call dpu_encoder_helper_wait_for_irq on timeout 370 * @phys_enc: Pointer to physical encoder structure 371 * @intr_idx: encoder interrupt index 372 * @wait_info: wait info struct 373 * @Return: 0 or -ERROR 374 */ 375 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, 376 enum dpu_intr_idx intr_idx, 377 struct dpu_encoder_wait_info *wait_info); 378 379 /** 380 * dpu_encoder_helper_register_irq - register and enable an irq 381 * @phys_enc: Pointer to physical encoder structure 382 * @intr_idx: encoder interrupt index 383 * @Return: 0 or -ERROR 384 */ 385 int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc, 386 enum dpu_intr_idx intr_idx); 387 388 /** 389 * dpu_encoder_helper_unregister_irq - unregister and disable an irq 390 * @phys_enc: Pointer to physical encoder structure 391 * @intr_idx: encoder interrupt index 392 * @Return: 0 or -ERROR 393 */ 394 int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc, 395 enum dpu_intr_idx intr_idx); 396 397 #endif /* __dpu_encoder_phys_H__ */ 398