1 /* 2 * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #ifndef __DPU_ENCODER_PHYS_H__ 16 #define __DPU_ENCODER_PHYS_H__ 17 18 #include <linux/jiffies.h> 19 20 #include "dpu_kms.h" 21 #include "dpu_hw_intf.h" 22 #include "dpu_hw_pingpong.h" 23 #include "dpu_hw_ctl.h" 24 #include "dpu_hw_top.h" 25 #include "dpu_encoder.h" 26 #include "dpu_crtc.h" 27 28 #define DPU_ENCODER_NAME_MAX 16 29 30 /* wait for at most 2 vsync for lowest refresh rate (24hz) */ 31 #define KICKOFF_TIMEOUT_MS 84 32 #define KICKOFF_TIMEOUT_JIFFIES msecs_to_jiffies(KICKOFF_TIMEOUT_MS) 33 34 /** 35 * enum dpu_enc_split_role - Role this physical encoder will play in a 36 * split-panel configuration, where one panel is master, and others slaves. 37 * Masters have extra responsibilities, like managing the VBLANK IRQ. 38 * @ENC_ROLE_SOLO: This is the one and only panel. This encoder is master. 39 * @ENC_ROLE_MASTER: This encoder is the master of a split panel config. 40 * @ENC_ROLE_SLAVE: This encoder is not the master of a split panel config. 41 */ 42 enum dpu_enc_split_role { 43 ENC_ROLE_SOLO, 44 ENC_ROLE_MASTER, 45 ENC_ROLE_SLAVE, 46 }; 47 48 /** 49 * enum dpu_enc_enable_state - current enabled state of the physical encoder 50 * @DPU_ENC_DISABLING: Encoder transitioning to disable state 51 * Events bounding transition are encoder type specific 52 * @DPU_ENC_DISABLED: Encoder is disabled 53 * @DPU_ENC_ENABLING: Encoder transitioning to enabled 54 * Events bounding transition are encoder type specific 55 * @DPU_ENC_ENABLED: Encoder is enabled 56 * @DPU_ENC_ERR_NEEDS_HW_RESET: Encoder is enabled, but requires a hw_reset 57 * to recover from a previous error 58 */ 59 enum dpu_enc_enable_state { 60 DPU_ENC_DISABLING, 61 DPU_ENC_DISABLED, 62 DPU_ENC_ENABLING, 63 DPU_ENC_ENABLED, 64 DPU_ENC_ERR_NEEDS_HW_RESET 65 }; 66 67 struct dpu_encoder_phys; 68 69 /** 70 * struct dpu_encoder_virt_ops - Interface the containing virtual encoder 71 * provides for the physical encoders to use to callback. 72 * @handle_vblank_virt: Notify virtual encoder of vblank IRQ reception 73 * Note: This is called from IRQ handler context. 74 * @handle_underrun_virt: Notify virtual encoder of underrun IRQ reception 75 * Note: This is called from IRQ handler context. 76 * @handle_frame_done: Notify virtual encoder that this phys encoder 77 * completes last request frame. 78 */ 79 struct dpu_encoder_virt_ops { 80 void (*handle_vblank_virt)(struct drm_encoder *, 81 struct dpu_encoder_phys *phys); 82 void (*handle_underrun_virt)(struct drm_encoder *, 83 struct dpu_encoder_phys *phys); 84 void (*handle_frame_done)(struct drm_encoder *, 85 struct dpu_encoder_phys *phys, u32 event); 86 }; 87 88 /** 89 * struct dpu_encoder_phys_ops - Interface the physical encoders provide to 90 * the containing virtual encoder. 91 * @late_register: DRM Call. Add Userspace interfaces, debugfs. 92 * @prepare_commit: MSM Atomic Call, start of atomic commit sequence 93 * @is_master: Whether this phys_enc is the current master 94 * encoder. Can be switched at enable time. Based 95 * on split_role and current mode (CMD/VID). 96 * @mode_fixup: DRM Call. Fixup a DRM mode. 97 * @mode_set: DRM Call. Set a DRM mode. 98 * This likely caches the mode, for use at enable. 99 * @enable: DRM Call. Enable a DRM mode. 100 * @disable: DRM Call. Disable mode. 101 * @atomic_check: DRM Call. Atomic check new DRM state. 102 * @destroy: DRM Call. Destroy and release resources. 103 * @get_hw_resources: Populate the structure with the hardware 104 * resources that this phys_enc is using. 105 * Expect no overlap between phys_encs. 106 * @control_vblank_irq Register/Deregister for VBLANK IRQ 107 * @wait_for_commit_done: Wait for hardware to have flushed the 108 * current pending frames to hardware 109 * @wait_for_tx_complete: Wait for hardware to transfer the pixels 110 * to the panel 111 * @wait_for_vblank: Wait for VBLANK, for sub-driver internal use 112 * @prepare_for_kickoff: Do any work necessary prior to a kickoff 113 * For CMD encoder, may wait for previous tx done 114 * @handle_post_kickoff: Do any work necessary post-kickoff work 115 * @trigger_start: Process start event on physical encoder 116 * @needs_single_flush: Whether encoder slaves need to be flushed 117 * @hw_reset: Issue HW recovery such as CTL reset and clear 118 * DPU_ENC_ERR_NEEDS_HW_RESET state 119 * @irq_control: Handler to enable/disable all the encoder IRQs 120 * @prepare_idle_pc: phys encoder can update the vsync_enable status 121 * on idle power collapse prepare 122 * @restore: Restore all the encoder configs. 123 * @get_line_count: Obtain current vertical line count 124 */ 125 126 struct dpu_encoder_phys_ops { 127 int (*late_register)(struct dpu_encoder_phys *encoder, 128 struct dentry *debugfs_root); 129 void (*prepare_commit)(struct dpu_encoder_phys *encoder); 130 bool (*is_master)(struct dpu_encoder_phys *encoder); 131 bool (*mode_fixup)(struct dpu_encoder_phys *encoder, 132 const struct drm_display_mode *mode, 133 struct drm_display_mode *adjusted_mode); 134 void (*mode_set)(struct dpu_encoder_phys *encoder, 135 struct drm_display_mode *mode, 136 struct drm_display_mode *adjusted_mode); 137 void (*enable)(struct dpu_encoder_phys *encoder); 138 void (*disable)(struct dpu_encoder_phys *encoder); 139 int (*atomic_check)(struct dpu_encoder_phys *encoder, 140 struct drm_crtc_state *crtc_state, 141 struct drm_connector_state *conn_state); 142 void (*destroy)(struct dpu_encoder_phys *encoder); 143 void (*get_hw_resources)(struct dpu_encoder_phys *encoder, 144 struct dpu_encoder_hw_resources *hw_res); 145 int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable); 146 int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc); 147 int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc); 148 int (*wait_for_vblank)(struct dpu_encoder_phys *phys_enc); 149 void (*prepare_for_kickoff)(struct dpu_encoder_phys *phys_enc, 150 struct dpu_encoder_kickoff_params *params); 151 void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc); 152 void (*trigger_start)(struct dpu_encoder_phys *phys_enc); 153 bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc); 154 void (*hw_reset)(struct dpu_encoder_phys *phys_enc); 155 void (*irq_control)(struct dpu_encoder_phys *phys, bool enable); 156 void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc); 157 void (*restore)(struct dpu_encoder_phys *phys); 158 int (*get_line_count)(struct dpu_encoder_phys *phys); 159 }; 160 161 /** 162 * enum dpu_intr_idx - dpu encoder interrupt index 163 * @INTR_IDX_VSYNC: Vsync interrupt for video mode panel 164 * @INTR_IDX_PINGPONG: Pingpong done unterrupt for cmd mode panel 165 * @INTR_IDX_UNDERRUN: Underrun unterrupt for video and cmd mode panel 166 * @INTR_IDX_RDPTR: Readpointer done unterrupt for cmd mode panel 167 */ 168 enum dpu_intr_idx { 169 INTR_IDX_VSYNC, 170 INTR_IDX_PINGPONG, 171 INTR_IDX_UNDERRUN, 172 INTR_IDX_CTL_START, 173 INTR_IDX_RDPTR, 174 INTR_IDX_MAX, 175 }; 176 177 /** 178 * dpu_encoder_irq - tracking structure for interrupts 179 * @name: string name of interrupt 180 * @intr_type: Encoder interrupt type 181 * @intr_idx: Encoder interrupt enumeration 182 * @hw_idx: HW Block ID 183 * @irq_idx: IRQ interface lookup index from DPU IRQ framework 184 * will be -EINVAL if IRQ is not registered 185 * @irq_cb: interrupt callback 186 */ 187 struct dpu_encoder_irq { 188 const char *name; 189 enum dpu_intr_type intr_type; 190 enum dpu_intr_idx intr_idx; 191 int hw_idx; 192 int irq_idx; 193 struct dpu_irq_callback cb; 194 }; 195 196 /** 197 * struct dpu_encoder_phys - physical encoder that drives a single INTF block 198 * tied to a specific panel / sub-panel. Abstract type, sub-classed by 199 * phys_vid or phys_cmd for video mode or command mode encs respectively. 200 * @parent: Pointer to the containing virtual encoder 201 * @connector: If a mode is set, cached pointer to the active connector 202 * @ops: Operations exposed to the virtual encoder 203 * @parent_ops: Callbacks exposed by the parent to the phys_enc 204 * @hw_mdptop: Hardware interface to the top registers 205 * @hw_ctl: Hardware interface to the ctl registers 206 * @hw_pp: Hardware interface to the ping pong registers 207 * @dpu_kms: Pointer to the dpu_kms top level 208 * @cached_mode: DRM mode cached at mode_set time, acted on in enable 209 * @enabled: Whether the encoder has enabled and running a mode 210 * @split_role: Role to play in a split-panel configuration 211 * @intf_mode: Interface mode 212 * @intf_idx: Interface index on dpu hardware 213 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes 214 * @enable_state: Enable state tracking 215 * @vblank_refcount: Reference count of vblank request 216 * @vsync_cnt: Vsync count for the physical encoder 217 * @underrun_cnt: Underrun count for the physical encoder 218 * @pending_kickoff_cnt: Atomic counter tracking the number of kickoffs 219 * vs. the number of done/vblank irqs. Should hover 220 * between 0-2 Incremented when a new kickoff is 221 * scheduled. Decremented in irq handler 222 * @pending_ctlstart_cnt: Atomic counter tracking the number of ctl start 223 * pending. 224 * @pending_kickoff_wq: Wait queue for blocking until kickoff completes 225 * @irq: IRQ tracking structures 226 */ 227 struct dpu_encoder_phys { 228 struct drm_encoder *parent; 229 struct drm_connector *connector; 230 struct dpu_encoder_phys_ops ops; 231 const struct dpu_encoder_virt_ops *parent_ops; 232 struct dpu_hw_mdp *hw_mdptop; 233 struct dpu_hw_ctl *hw_ctl; 234 struct dpu_hw_pingpong *hw_pp; 235 struct dpu_kms *dpu_kms; 236 struct drm_display_mode cached_mode; 237 enum dpu_enc_split_role split_role; 238 enum dpu_intf_mode intf_mode; 239 enum dpu_intf intf_idx; 240 spinlock_t *enc_spinlock; 241 enum dpu_enc_enable_state enable_state; 242 atomic_t vblank_refcount; 243 atomic_t vsync_cnt; 244 atomic_t underrun_cnt; 245 atomic_t pending_ctlstart_cnt; 246 atomic_t pending_kickoff_cnt; 247 wait_queue_head_t pending_kickoff_wq; 248 struct dpu_encoder_irq irq[INTR_IDX_MAX]; 249 }; 250 251 static inline int dpu_encoder_phys_inc_pending(struct dpu_encoder_phys *phys) 252 { 253 atomic_inc_return(&phys->pending_ctlstart_cnt); 254 return atomic_inc_return(&phys->pending_kickoff_cnt); 255 } 256 257 /** 258 * struct dpu_encoder_phys_vid - sub-class of dpu_encoder_phys to handle video 259 * mode specific operations 260 * @base: Baseclass physical encoder structure 261 * @hw_intf: Hardware interface to the intf registers 262 * @timing_params: Current timing parameter 263 */ 264 struct dpu_encoder_phys_vid { 265 struct dpu_encoder_phys base; 266 struct dpu_hw_intf *hw_intf; 267 struct intf_timing_params timing_params; 268 }; 269 270 /** 271 * struct dpu_encoder_phys_cmd - sub-class of dpu_encoder_phys to handle command 272 * mode specific operations 273 * @base: Baseclass physical encoder structure 274 * @intf_idx: Intf Block index used by this phys encoder 275 * @stream_sel: Stream selection for multi-stream interfaces 276 * @serialize_wait4pp: serialize wait4pp feature waits for pp_done interrupt 277 * after ctl_start instead of before next frame kickoff 278 * @pp_timeout_report_cnt: number of pingpong done irq timeout errors 279 * @pending_vblank_cnt: Atomic counter tracking pending wait for VBLANK 280 * @pending_vblank_wq: Wait queue for blocking until VBLANK received 281 */ 282 struct dpu_encoder_phys_cmd { 283 struct dpu_encoder_phys base; 284 int stream_sel; 285 bool serialize_wait4pp; 286 int pp_timeout_report_cnt; 287 atomic_t pending_vblank_cnt; 288 wait_queue_head_t pending_vblank_wq; 289 }; 290 291 /** 292 * struct dpu_enc_phys_init_params - initialization parameters for phys encs 293 * @dpu_kms: Pointer to the dpu_kms top level 294 * @parent: Pointer to the containing virtual encoder 295 * @parent_ops: Callbacks exposed by the parent to the phys_enc 296 * @split_role: Role to play in a split-panel configuration 297 * @intf_idx: Interface index this phys_enc will control 298 * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes 299 */ 300 struct dpu_enc_phys_init_params { 301 struct dpu_kms *dpu_kms; 302 struct drm_encoder *parent; 303 const struct dpu_encoder_virt_ops *parent_ops; 304 enum dpu_enc_split_role split_role; 305 enum dpu_intf intf_idx; 306 spinlock_t *enc_spinlock; 307 }; 308 309 /** 310 * dpu_encoder_wait_info - container for passing arguments to irq wait functions 311 * @wq: wait queue structure 312 * @atomic_cnt: wait until atomic_cnt equals zero 313 * @timeout_ms: timeout value in milliseconds 314 */ 315 struct dpu_encoder_wait_info { 316 wait_queue_head_t *wq; 317 atomic_t *atomic_cnt; 318 s64 timeout_ms; 319 }; 320 321 /** 322 * dpu_encoder_phys_vid_init - Construct a new video mode physical encoder 323 * @p: Pointer to init params structure 324 * Return: Error code or newly allocated encoder 325 */ 326 struct dpu_encoder_phys *dpu_encoder_phys_vid_init( 327 struct dpu_enc_phys_init_params *p); 328 329 /** 330 * dpu_encoder_phys_cmd_init - Construct a new command mode physical encoder 331 * @p: Pointer to init params structure 332 * Return: Error code or newly allocated encoder 333 */ 334 struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( 335 struct dpu_enc_phys_init_params *p); 336 337 /** 338 * dpu_encoder_helper_trigger_start - control start helper function 339 * This helper function may be optionally specified by physical 340 * encoders if they require ctl_start triggering. 341 * @phys_enc: Pointer to physical encoder structure 342 */ 343 void dpu_encoder_helper_trigger_start(struct dpu_encoder_phys *phys_enc); 344 345 /** 346 * dpu_encoder_helper_hw_reset - issue ctl hw reset 347 * This helper function may be optionally specified by physical 348 * encoders if they require ctl hw reset. If state is currently 349 * DPU_ENC_ERR_NEEDS_HW_RESET, it is set back to DPU_ENC_ENABLED. 350 * @phys_enc: Pointer to physical encoder structure 351 */ 352 void dpu_encoder_helper_hw_reset(struct dpu_encoder_phys *phys_enc); 353 354 static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( 355 struct dpu_encoder_phys *phys_enc) 356 { 357 struct dpu_crtc_state *dpu_cstate; 358 359 if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING) 360 return BLEND_3D_NONE; 361 362 dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state); 363 364 if (phys_enc->split_role == ENC_ROLE_SOLO && 365 dpu_crtc_state_is_stereo(dpu_cstate)) 366 return BLEND_3D_H_ROW_INT; 367 368 return BLEND_3D_NONE; 369 } 370 371 /** 372 * dpu_encoder_helper_split_config - split display configuration helper function 373 * This helper function may be used by physical encoders to configure 374 * the split display related registers. 375 * @phys_enc: Pointer to physical encoder structure 376 * @interface: enum dpu_intf setting 377 */ 378 void dpu_encoder_helper_split_config( 379 struct dpu_encoder_phys *phys_enc, 380 enum dpu_intf interface); 381 382 /** 383 * dpu_encoder_helper_report_irq_timeout - utility to report error that irq has 384 * timed out, including reporting frame error event to crtc and debug dump 385 * @phys_enc: Pointer to physical encoder structure 386 * @intr_idx: Failing interrupt index 387 */ 388 void dpu_encoder_helper_report_irq_timeout(struct dpu_encoder_phys *phys_enc, 389 enum dpu_intr_idx intr_idx); 390 391 /** 392 * dpu_encoder_helper_wait_for_irq - utility to wait on an irq. 393 * note: will call dpu_encoder_helper_wait_for_irq on timeout 394 * @phys_enc: Pointer to physical encoder structure 395 * @intr_idx: encoder interrupt index 396 * @wait_info: wait info struct 397 * @Return: 0 or -ERROR 398 */ 399 int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, 400 enum dpu_intr_idx intr_idx, 401 struct dpu_encoder_wait_info *wait_info); 402 403 /** 404 * dpu_encoder_helper_register_irq - register and enable an irq 405 * @phys_enc: Pointer to physical encoder structure 406 * @intr_idx: encoder interrupt index 407 * @Return: 0 or -ERROR 408 */ 409 int dpu_encoder_helper_register_irq(struct dpu_encoder_phys *phys_enc, 410 enum dpu_intr_idx intr_idx); 411 412 /** 413 * dpu_encoder_helper_unregister_irq - unregister and disable an irq 414 * @phys_enc: Pointer to physical encoder structure 415 * @intr_idx: encoder interrupt index 416 * @Return: 0 or -ERROR 417 */ 418 int dpu_encoder_helper_unregister_irq(struct dpu_encoder_phys *phys_enc, 419 enum dpu_intr_idx intr_idx); 420 421 #endif /* __dpu_encoder_phys_H__ */ 422