1 /* 2 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef __DPU_ENCODER_H__ 20 #define __DPU_ENCODER_H__ 21 22 #include <drm/drm_crtc.h> 23 #include "dpu_hw_mdss.h" 24 25 #define DPU_ENCODER_FRAME_EVENT_DONE BIT(0) 26 #define DPU_ENCODER_FRAME_EVENT_ERROR BIT(1) 27 #define DPU_ENCODER_FRAME_EVENT_PANEL_DEAD BIT(2) 28 #define DPU_ENCODER_FRAME_EVENT_IDLE BIT(3) 29 30 #define IDLE_TIMEOUT (66 - 16/2) 31 32 /** 33 * Encoder functions and data types 34 * @intfs: Interfaces this encoder is using, INTF_MODE_NONE if unused 35 */ 36 struct dpu_encoder_hw_resources { 37 enum dpu_intf_mode intfs[INTF_MAX]; 38 }; 39 40 /** 41 * dpu_encoder_kickoff_params - info encoder requires at kickoff 42 * @affected_displays: bitmask, bit set means the ROI of the commit lies within 43 * the bounds of the physical display at the bit index 44 */ 45 struct dpu_encoder_kickoff_params { 46 unsigned long affected_displays; 47 }; 48 49 /** 50 * dpu_encoder_get_hw_resources - Populate table of required hardware resources 51 * @encoder: encoder pointer 52 * @hw_res: resource table to populate with encoder required resources 53 */ 54 void dpu_encoder_get_hw_resources(struct drm_encoder *encoder, 55 struct dpu_encoder_hw_resources *hw_res); 56 57 /** 58 * dpu_encoder_register_vblank_callback - provide callback to encoder that 59 * will be called on the next vblank. 60 * @encoder: encoder pointer 61 * @cb: callback pointer, provide NULL to deregister and disable IRQs 62 * @data: user data provided to callback 63 */ 64 void dpu_encoder_register_vblank_callback(struct drm_encoder *encoder, 65 void (*cb)(void *), void *data); 66 67 /** 68 * dpu_encoder_register_frame_event_callback - provide callback to encoder that 69 * will be called after the request is complete, or other events. 70 * @encoder: encoder pointer 71 * @cb: callback pointer, provide NULL to deregister 72 * @data: user data provided to callback 73 */ 74 void dpu_encoder_register_frame_event_callback(struct drm_encoder *encoder, 75 void (*cb)(void *, u32), void *data); 76 77 /** 78 * dpu_encoder_prepare_for_kickoff - schedule double buffer flip of the ctl 79 * path (i.e. ctl flush and start) at next appropriate time. 80 * Immediately: if no previous commit is outstanding. 81 * Delayed: Block until next trigger can be issued. 82 * @encoder: encoder pointer 83 * @params: kickoff time parameters 84 */ 85 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *encoder, 86 struct dpu_encoder_kickoff_params *params); 87 88 /** 89 * dpu_encoder_trigger_kickoff_pending - Clear the flush bits from previous 90 * kickoff and trigger the ctl prepare progress for command mode display. 91 * @encoder: encoder pointer 92 */ 93 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *encoder); 94 95 /** 96 * dpu_encoder_kickoff - trigger a double buffer flip of the ctl path 97 * (i.e. ctl flush and start) immediately. 98 * @encoder: encoder pointer 99 */ 100 void dpu_encoder_kickoff(struct drm_encoder *encoder); 101 102 /** 103 * dpu_encoder_wait_for_event - Waits for encoder events 104 * @encoder: encoder pointer 105 * @event: event to wait for 106 * MSM_ENC_COMMIT_DONE - Wait for hardware to have flushed the current pending 107 * frames to hardware at a vblank or ctl_start 108 * Encoders will map this differently depending on the 109 * panel type. 110 * vid mode -> vsync_irq 111 * cmd mode -> ctl_start 112 * MSM_ENC_TX_COMPLETE - Wait for the hardware to transfer all the pixels to 113 * the panel. Encoders will map this differently 114 * depending on the panel type. 115 * vid mode -> vsync_irq 116 * cmd mode -> pp_done 117 * Returns: 0 on success, -EWOULDBLOCK if already signaled, error otherwise 118 */ 119 int dpu_encoder_wait_for_event(struct drm_encoder *drm_encoder, 120 enum msm_event_wait event); 121 122 /* 123 * dpu_encoder_get_intf_mode - get interface mode of the given encoder 124 * @encoder: Pointer to drm encoder object 125 */ 126 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder); 127 128 /** 129 * dpu_encoder_virt_restore - restore the encoder configs 130 * @encoder: encoder pointer 131 */ 132 void dpu_encoder_virt_restore(struct drm_encoder *encoder); 133 134 /** 135 * dpu_encoder_init - initialize virtual encoder object 136 * @dev: Pointer to drm device structure 137 * @disp_info: Pointer to display information structure 138 * Returns: Pointer to newly created drm encoder 139 */ 140 struct drm_encoder *dpu_encoder_init( 141 struct drm_device *dev, 142 int drm_enc_mode); 143 144 /** 145 * dpu_encoder_setup - setup dpu_encoder for the display probed 146 * @dev: Pointer to drm device structure 147 * @enc: Pointer to the drm_encoder 148 * @disp_info: Pointer to the display info 149 */ 150 int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc, 151 struct msm_display_info *disp_info); 152 153 /** 154 * dpu_encoder_prepare_commit - prepare encoder at the very beginning of an 155 * atomic commit, before any registers are written 156 * @drm_enc: Pointer to previously created drm encoder structure 157 */ 158 void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc); 159 160 /** 161 * dpu_encoder_set_idle_timeout - set the idle timeout for video 162 * and command mode encoders. 163 * @drm_enc: Pointer to previously created drm encoder structure 164 * @idle_timeout: idle timeout duration in milliseconds 165 */ 166 void dpu_encoder_set_idle_timeout(struct drm_encoder *drm_enc, 167 u32 idle_timeout); 168 169 #endif /* __DPU_ENCODER_H__ */ 170