1 /* 2 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef __DPU_ENCODER_H__ 20 #define __DPU_ENCODER_H__ 21 22 #include <drm/drm_crtc.h> 23 #include "dpu_hw_mdss.h" 24 25 #define DPU_ENCODER_FRAME_EVENT_DONE BIT(0) 26 #define DPU_ENCODER_FRAME_EVENT_ERROR BIT(1) 27 #define DPU_ENCODER_FRAME_EVENT_PANEL_DEAD BIT(2) 28 #define DPU_ENCODER_FRAME_EVENT_IDLE BIT(3) 29 30 #define IDLE_TIMEOUT (66 - 16/2) 31 32 /** 33 * Encoder functions and data types 34 * @intfs: Interfaces this encoder is using, INTF_MODE_NONE if unused 35 */ 36 struct dpu_encoder_hw_resources { 37 enum dpu_intf_mode intfs[INTF_MAX]; 38 }; 39 40 /** 41 * dpu_encoder_get_hw_resources - Populate table of required hardware resources 42 * @encoder: encoder pointer 43 * @hw_res: resource table to populate with encoder required resources 44 */ 45 void dpu_encoder_get_hw_resources(struct drm_encoder *encoder, 46 struct dpu_encoder_hw_resources *hw_res); 47 48 /** 49 * dpu_encoder_assign_crtc - Link the encoder to the crtc it's assigned to 50 * @encoder: encoder pointer 51 * @crtc: crtc pointer 52 */ 53 void dpu_encoder_assign_crtc(struct drm_encoder *encoder, 54 struct drm_crtc *crtc); 55 56 /** 57 * dpu_encoder_toggle_vblank_for_crtc - Toggles vblank interrupts on or off if 58 * the encoder is assigned to the given crtc 59 * @encoder: encoder pointer 60 * @crtc: crtc pointer 61 * @enable: true if vblank should be enabled 62 */ 63 void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *encoder, 64 struct drm_crtc *crtc, bool enable); 65 66 /** 67 * dpu_encoder_register_frame_event_callback - provide callback to encoder that 68 * will be called after the request is complete, or other events. 69 * @encoder: encoder pointer 70 * @cb: callback pointer, provide NULL to deregister 71 * @data: user data provided to callback 72 */ 73 void dpu_encoder_register_frame_event_callback(struct drm_encoder *encoder, 74 void (*cb)(void *, u32), void *data); 75 76 /** 77 * dpu_encoder_prepare_for_kickoff - schedule double buffer flip of the ctl 78 * path (i.e. ctl flush and start) at next appropriate time. 79 * Immediately: if no previous commit is outstanding. 80 * Delayed: Block until next trigger can be issued. 81 * @encoder: encoder pointer 82 * @async: true if this is an asynchronous commit 83 */ 84 void dpu_encoder_prepare_for_kickoff(struct drm_encoder *encoder, bool async); 85 86 /** 87 * dpu_encoder_trigger_kickoff_pending - Clear the flush bits from previous 88 * kickoff and trigger the ctl prepare progress for command mode display. 89 * @encoder: encoder pointer 90 */ 91 void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *encoder); 92 93 /** 94 * dpu_encoder_kickoff - trigger a double buffer flip of the ctl path 95 * (i.e. ctl flush and start) immediately. 96 * @encoder: encoder pointer 97 * @async: true if this is an asynchronous commit 98 */ 99 void dpu_encoder_kickoff(struct drm_encoder *encoder, bool async); 100 101 /** 102 * dpu_encoder_wait_for_event - Waits for encoder events 103 * @encoder: encoder pointer 104 * @event: event to wait for 105 * MSM_ENC_COMMIT_DONE - Wait for hardware to have flushed the current pending 106 * frames to hardware at a vblank or ctl_start 107 * Encoders will map this differently depending on the 108 * panel type. 109 * vid mode -> vsync_irq 110 * cmd mode -> ctl_start 111 * MSM_ENC_TX_COMPLETE - Wait for the hardware to transfer all the pixels to 112 * the panel. Encoders will map this differently 113 * depending on the panel type. 114 * vid mode -> vsync_irq 115 * cmd mode -> pp_done 116 * Returns: 0 on success, -EWOULDBLOCK if already signaled, error otherwise 117 */ 118 int dpu_encoder_wait_for_event(struct drm_encoder *drm_encoder, 119 enum msm_event_wait event); 120 121 /* 122 * dpu_encoder_get_intf_mode - get interface mode of the given encoder 123 * @encoder: Pointer to drm encoder object 124 */ 125 enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder); 126 127 /** 128 * dpu_encoder_virt_runtime_resume - pm runtime resume the encoder configs 129 * @encoder: encoder pointer 130 */ 131 void dpu_encoder_virt_runtime_resume(struct drm_encoder *encoder); 132 133 /** 134 * dpu_encoder_init - initialize virtual encoder object 135 * @dev: Pointer to drm device structure 136 * @disp_info: Pointer to display information structure 137 * Returns: Pointer to newly created drm encoder 138 */ 139 struct drm_encoder *dpu_encoder_init( 140 struct drm_device *dev, 141 int drm_enc_mode); 142 143 /** 144 * dpu_encoder_setup - setup dpu_encoder for the display probed 145 * @dev: Pointer to drm device structure 146 * @enc: Pointer to the drm_encoder 147 * @disp_info: Pointer to the display info 148 */ 149 int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc, 150 struct msm_display_info *disp_info); 151 152 /** 153 * dpu_encoder_prepare_commit - prepare encoder at the very beginning of an 154 * atomic commit, before any registers are written 155 * @drm_enc: Pointer to previously created drm encoder structure 156 */ 157 void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc); 158 159 /** 160 * dpu_encoder_set_idle_timeout - set the idle timeout for video 161 * and command mode encoders. 162 * @drm_enc: Pointer to previously created drm encoder structure 163 * @idle_timeout: idle timeout duration in milliseconds 164 */ 165 void dpu_encoder_set_idle_timeout(struct drm_encoder *drm_enc, 166 u32 idle_timeout); 167 168 #endif /* __DPU_ENCODER_H__ */ 169