1 /* 2 * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved. 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef _DPU_CRTC_H_ 20 #define _DPU_CRTC_H_ 21 22 #include <linux/kthread.h> 23 #include <drm/drm_crtc.h> 24 #include "dpu_kms.h" 25 #include "dpu_core_perf.h" 26 #include "dpu_hw_blk.h" 27 28 #define DPU_CRTC_NAME_SIZE 12 29 30 /* define the maximum number of in-flight frame events */ 31 #define DPU_CRTC_FRAME_EVENT_SIZE 4 32 33 /** 34 * enum dpu_crtc_client_type: crtc client type 35 * @RT_CLIENT: RealTime client like video/cmd mode display 36 * voting through apps rsc 37 * @NRT_CLIENT: Non-RealTime client like WB display 38 * voting through apps rsc 39 */ 40 enum dpu_crtc_client_type { 41 RT_CLIENT, 42 NRT_CLIENT, 43 }; 44 45 /** 46 * enum dpu_crtc_smmu_state: smmu state 47 * @ATTACHED: all the context banks are attached. 48 * @DETACHED: all the context banks are detached. 49 * @ATTACH_ALL_REQ: transient state of attaching context banks. 50 * @DETACH_ALL_REQ: transient state of detaching context banks. 51 */ 52 enum dpu_crtc_smmu_state { 53 ATTACHED = 0, 54 DETACHED, 55 ATTACH_ALL_REQ, 56 DETACH_ALL_REQ, 57 }; 58 59 /** 60 * enum dpu_crtc_smmu_state_transition_type: state transition type 61 * @NONE: no pending state transitions 62 * @PRE_COMMIT: state transitions should be done before processing the commit 63 * @POST_COMMIT: state transitions to be done after processing the commit. 64 */ 65 enum dpu_crtc_smmu_state_transition_type { 66 NONE, 67 PRE_COMMIT, 68 POST_COMMIT 69 }; 70 71 /** 72 * struct dpu_crtc_smmu_state_data: stores the smmu state and transition type 73 * @state: current state of smmu context banks 74 * @transition_type: transition request type 75 * @transition_error: whether there is error while transitioning the state 76 */ 77 struct dpu_crtc_smmu_state_data { 78 uint32_t state; 79 uint32_t transition_type; 80 uint32_t transition_error; 81 }; 82 83 /** 84 * struct dpu_crtc_mixer: stores the map for each virtual pipeline in the CRTC 85 * @hw_lm: LM HW Driver context 86 * @hw_ctl: CTL Path HW driver context 87 * @encoder: Encoder attached to this lm & ctl 88 * @mixer_op_mode: mixer blending operation mode 89 * @flush_mask: mixer flush mask for ctl, mixer and pipe 90 */ 91 struct dpu_crtc_mixer { 92 struct dpu_hw_mixer *hw_lm; 93 struct dpu_hw_ctl *hw_ctl; 94 struct drm_encoder *encoder; 95 u32 mixer_op_mode; 96 u32 flush_mask; 97 }; 98 99 /** 100 * struct dpu_crtc_frame_event: stores crtc frame event for crtc processing 101 * @work: base work structure 102 * @crtc: Pointer to crtc handling this event 103 * @list: event list 104 * @ts: timestamp at queue entry 105 * @event: event identifier 106 */ 107 struct dpu_crtc_frame_event { 108 struct kthread_work work; 109 struct drm_crtc *crtc; 110 struct list_head list; 111 ktime_t ts; 112 u32 event; 113 }; 114 115 /* 116 * Maximum number of free event structures to cache 117 */ 118 #define DPU_CRTC_MAX_EVENT_COUNT 16 119 120 /** 121 * struct dpu_crtc - virtualized CRTC data structure 122 * @base : Base drm crtc structure 123 * @name : ASCII description of this crtc 124 * @num_ctls : Number of ctl paths in use 125 * @num_mixers : Number of mixers in use 126 * @mixers_swapped: Whether the mixers have been swapped for left/right update 127 * especially in the case of DSC Merge. 128 * @mixers : List of active mixers 129 * @event : Pointer to last received drm vblank event. If there is a 130 * pending vblank event, this will be non-null. 131 * @vsync_count : Running count of received vsync events 132 * @drm_requested_vblank : Whether vblanks have been enabled in the encoder 133 * @property_info : Opaque structure for generic property support 134 * @property_defaults : Array of default values for generic property support 135 * @stage_cfg : H/w mixer stage configuration 136 * @debugfs_root : Parent of debugfs node 137 * @vblank_cb_count : count of vblank callback since last reset 138 * @play_count : frame count between crtc enable and disable 139 * @vblank_cb_time : ktime at vblank count reset 140 * @vblank_requested : whether the user has requested vblank events 141 * @suspend : whether or not a suspend operation is in progress 142 * @enabled : whether the DPU CRTC is currently enabled. updated in the 143 * commit-thread, not state-swap time which is earlier, so 144 * safe to make decisions on during VBLANK on/off work 145 * @feature_list : list of color processing features supported on a crtc 146 * @active_list : list of color processing features are active 147 * @dirty_list : list of color processing features are dirty 148 * @ad_dirty: list containing ad properties that are dirty 149 * @ad_active: list containing ad properties that are active 150 * @crtc_lock : crtc lock around create, destroy and access. 151 * @frame_pending : Whether or not an update is pending 152 * @frame_events : static allocation of in-flight frame events 153 * @frame_event_list : available frame event list 154 * @spin_lock : spin lock for frame event, transaction status, etc... 155 * @frame_done_comp : for frame_event_done synchronization 156 * @event_thread : Pointer to event handler thread 157 * @event_worker : Event worker queue 158 * @event_lock : Spinlock around event handling code 159 * @misr_enable : boolean entry indicates misr enable/disable status. 160 * @misr_frame_count : misr frame count provided by client 161 * @misr_data : store misr data before turning off the clocks. 162 * @phandle: Pointer to power handler 163 * @power_event : registered power event handle 164 * @cur_perf : current performance committed to clock/bandwidth driver 165 * @rp_lock : serialization lock for resource pool 166 * @rp_head : list of active resource pool 167 * @scl3_cfg_lut : qseed3 lut config 168 */ 169 struct dpu_crtc { 170 struct drm_crtc base; 171 char name[DPU_CRTC_NAME_SIZE]; 172 173 /* HW Resources reserved for the crtc */ 174 u32 num_ctls; 175 u32 num_mixers; 176 bool mixers_swapped; 177 struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS]; 178 struct dpu_hw_scaler3_lut_cfg *scl3_lut_cfg; 179 180 struct drm_pending_vblank_event *event; 181 u32 vsync_count; 182 183 struct dpu_hw_stage_cfg stage_cfg; 184 struct dentry *debugfs_root; 185 186 u32 vblank_cb_count; 187 u64 play_count; 188 ktime_t vblank_cb_time; 189 bool vblank_requested; 190 bool suspend; 191 bool enabled; 192 193 struct list_head feature_list; 194 struct list_head active_list; 195 struct list_head dirty_list; 196 struct list_head ad_dirty; 197 struct list_head ad_active; 198 199 struct mutex crtc_lock; 200 201 atomic_t frame_pending; 202 struct dpu_crtc_frame_event frame_events[DPU_CRTC_FRAME_EVENT_SIZE]; 203 struct list_head frame_event_list; 204 spinlock_t spin_lock; 205 struct completion frame_done_comp; 206 207 /* for handling internal event thread */ 208 spinlock_t event_lock; 209 bool misr_enable; 210 u32 misr_frame_count; 211 u32 misr_data[CRTC_DUAL_MIXERS]; 212 213 struct dpu_power_handle *phandle; 214 struct dpu_power_event *power_event; 215 216 struct dpu_core_perf_params cur_perf; 217 218 struct mutex rp_lock; 219 struct list_head rp_head; 220 221 struct dpu_crtc_smmu_state_data smmu_state; 222 }; 223 224 #define to_dpu_crtc(x) container_of(x, struct dpu_crtc, base) 225 226 /** 227 * struct dpu_crtc_res_ops - common operations for crtc resources 228 * @get: get given resource 229 * @put: put given resource 230 */ 231 struct dpu_crtc_res_ops { 232 void *(*get)(void *val, u32 type, u64 tag); 233 void (*put)(void *val); 234 }; 235 236 #define DPU_CRTC_RES_FLAG_FREE BIT(0) 237 238 /** 239 * struct dpu_crtc_res - definition of crtc resources 240 * @list: list of crtc resource 241 * @type: crtc resource type 242 * @tag: unique identifier per type 243 * @refcount: reference/usage count 244 * @ops: callback operations 245 * @val: resource handle associated with type/tag 246 * @flags: customization flags 247 */ 248 struct dpu_crtc_res { 249 struct list_head list; 250 u32 type; 251 u64 tag; 252 atomic_t refcount; 253 struct dpu_crtc_res_ops ops; 254 void *val; 255 u32 flags; 256 }; 257 258 /** 259 * dpu_crtc_respool - crtc resource pool 260 * @rp_lock: pointer to serialization lock 261 * @rp_head: pointer to head of active resource pools of this crtc 262 * @rp_list: list of crtc resource pool 263 * @sequence_id: sequence identifier, incremented per state duplication 264 * @res_list: list of resource managed by this resource pool 265 * @ops: resource operations for parent resource pool 266 */ 267 struct dpu_crtc_respool { 268 struct mutex *rp_lock; 269 struct list_head *rp_head; 270 struct list_head rp_list; 271 u32 sequence_id; 272 struct list_head res_list; 273 struct dpu_crtc_res_ops ops; 274 }; 275 276 /** 277 * struct dpu_crtc_state - dpu container for atomic crtc state 278 * @base: Base drm crtc state structure 279 * @is_ppsplit : Whether current topology requires PPSplit special handling 280 * @bw_control : true if bw/clk controlled by core bw/clk properties 281 * @bw_split_vote : true if bw controlled by llcc/dram bw properties 282 * @lm_bounds : LM boundaries based on current mode full resolution, no ROI. 283 * Origin top left of CRTC. 284 * @property_state: Local storage for msm_prop properties 285 * @property_values: Current crtc property values 286 * @input_fence_timeout_ns : Cached input fence timeout, in ns 287 * @new_perf: new performance state being requested 288 */ 289 struct dpu_crtc_state { 290 struct drm_crtc_state base; 291 292 bool bw_control; 293 bool bw_split_vote; 294 295 bool is_ppsplit; 296 struct drm_rect lm_bounds[CRTC_DUAL_MIXERS]; 297 298 uint64_t input_fence_timeout_ns; 299 300 struct dpu_core_perf_params new_perf; 301 struct dpu_crtc_respool rp; 302 }; 303 304 #define to_dpu_crtc_state(x) \ 305 container_of(x, struct dpu_crtc_state, base) 306 307 /** 308 * dpu_crtc_get_mixer_width - get the mixer width 309 * Mixer width will be same as panel width(/2 for split) 310 */ 311 static inline int dpu_crtc_get_mixer_width(struct dpu_crtc *dpu_crtc, 312 struct dpu_crtc_state *cstate, struct drm_display_mode *mode) 313 { 314 u32 mixer_width; 315 316 if (!dpu_crtc || !cstate || !mode) 317 return 0; 318 319 mixer_width = (dpu_crtc->num_mixers == CRTC_DUAL_MIXERS ? 320 mode->hdisplay / CRTC_DUAL_MIXERS : mode->hdisplay); 321 322 return mixer_width; 323 } 324 325 /** 326 * dpu_crtc_get_mixer_height - get the mixer height 327 * Mixer height will be same as panel height 328 */ 329 static inline int dpu_crtc_get_mixer_height(struct dpu_crtc *dpu_crtc, 330 struct dpu_crtc_state *cstate, struct drm_display_mode *mode) 331 { 332 if (!dpu_crtc || !cstate || !mode) 333 return 0; 334 335 return mode->vdisplay; 336 } 337 338 /** 339 * dpu_crtc_frame_pending - retun the number of pending frames 340 * @crtc: Pointer to drm crtc object 341 */ 342 static inline int dpu_crtc_frame_pending(struct drm_crtc *crtc) 343 { 344 struct dpu_crtc *dpu_crtc; 345 346 if (!crtc) 347 return -EINVAL; 348 349 dpu_crtc = to_dpu_crtc(crtc); 350 return atomic_read(&dpu_crtc->frame_pending); 351 } 352 353 /** 354 * dpu_crtc_vblank - enable or disable vblanks for this crtc 355 * @crtc: Pointer to drm crtc object 356 * @en: true to enable vblanks, false to disable 357 */ 358 int dpu_crtc_vblank(struct drm_crtc *crtc, bool en); 359 360 /** 361 * dpu_crtc_commit_kickoff - trigger kickoff of the commit for this crtc 362 * @crtc: Pointer to drm crtc object 363 */ 364 void dpu_crtc_commit_kickoff(struct drm_crtc *crtc); 365 366 /** 367 * dpu_crtc_complete_commit - callback signalling completion of current commit 368 * @crtc: Pointer to drm crtc object 369 * @old_state: Pointer to drm crtc old state object 370 */ 371 void dpu_crtc_complete_commit(struct drm_crtc *crtc, 372 struct drm_crtc_state *old_state); 373 374 /** 375 * dpu_crtc_init - create a new crtc object 376 * @dev: dpu device 377 * @plane: base plane 378 * @Return: new crtc object or error 379 */ 380 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane); 381 382 /** 383 * dpu_crtc_register_custom_event - api for enabling/disabling crtc event 384 * @kms: Pointer to dpu_kms 385 * @crtc_drm: Pointer to crtc object 386 * @event: Event that client is interested 387 * @en: Flag to enable/disable the event 388 */ 389 int dpu_crtc_register_custom_event(struct dpu_kms *kms, 390 struct drm_crtc *crtc_drm, u32 event, bool en); 391 392 /** 393 * dpu_crtc_get_intf_mode - get interface mode of the given crtc 394 * @crtc: Pointert to crtc 395 */ 396 enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc); 397 398 /** 399 * dpu_crtc_get_client_type - check the crtc type- rt, nrt etc. 400 * @crtc: Pointer to crtc 401 */ 402 static inline enum dpu_crtc_client_type dpu_crtc_get_client_type( 403 struct drm_crtc *crtc) 404 { 405 struct dpu_crtc_state *cstate = 406 crtc ? to_dpu_crtc_state(crtc->state) : NULL; 407 408 if (!cstate) 409 return NRT_CLIENT; 410 411 return RT_CLIENT; 412 } 413 414 /** 415 * dpu_crtc_is_enabled - check if dpu crtc is enabled or not 416 * @crtc: Pointer to crtc 417 */ 418 static inline bool dpu_crtc_is_enabled(struct drm_crtc *crtc) 419 { 420 return crtc ? crtc->enabled : false; 421 } 422 423 #endif /* _DPU_CRTC_H_ */ 424