1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 10 #include <linux/sort.h> 11 #include <linux/debugfs.h> 12 #include <linux/ktime.h> 13 #include <linux/bits.h> 14 15 #include <drm/drm_atomic.h> 16 #include <drm/drm_blend.h> 17 #include <drm/drm_crtc.h> 18 #include <drm/drm_flip_work.h> 19 #include <drm/drm_framebuffer.h> 20 #include <drm/drm_mode.h> 21 #include <drm/drm_probe_helper.h> 22 #include <drm/drm_rect.h> 23 #include <drm/drm_vblank.h> 24 #include <drm/drm_self_refresh_helper.h> 25 26 #include "dpu_kms.h" 27 #include "dpu_hw_lm.h" 28 #include "dpu_hw_ctl.h" 29 #include "dpu_hw_dspp.h" 30 #include "dpu_crtc.h" 31 #include "dpu_plane.h" 32 #include "dpu_encoder.h" 33 #include "dpu_vbif.h" 34 #include "dpu_core_perf.h" 35 #include "dpu_trace.h" 36 37 /* layer mixer index on dpu_crtc */ 38 #define LEFT_MIXER 0 39 #define RIGHT_MIXER 1 40 41 /* timeout in ms waiting for frame done */ 42 #define DPU_CRTC_FRAME_DONE_TIMEOUT_MS 60 43 44 #define CONVERT_S3_15(val) \ 45 (((((u64)val) & ~BIT_ULL(63)) >> 17) & GENMASK_ULL(17, 0)) 46 47 static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc) 48 { 49 struct msm_drm_private *priv = crtc->dev->dev_private; 50 51 return to_dpu_kms(priv->kms); 52 } 53 54 static void dpu_crtc_destroy(struct drm_crtc *crtc) 55 { 56 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 57 58 if (!crtc) 59 return; 60 61 drm_crtc_cleanup(crtc); 62 kfree(dpu_crtc); 63 } 64 65 static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc) 66 { 67 struct drm_device *dev = crtc->dev; 68 struct drm_encoder *encoder; 69 70 drm_for_each_encoder(encoder, dev) 71 if (encoder->crtc == crtc) 72 return encoder; 73 74 return NULL; 75 } 76 77 static enum dpu_crtc_crc_source dpu_crtc_parse_crc_source(const char *src_name) 78 { 79 if (!src_name || 80 !strcmp(src_name, "none")) 81 return DPU_CRTC_CRC_SOURCE_NONE; 82 if (!strcmp(src_name, "auto") || 83 !strcmp(src_name, "lm")) 84 return DPU_CRTC_CRC_SOURCE_LAYER_MIXER; 85 if (!strcmp(src_name, "encoder")) 86 return DPU_CRTC_CRC_SOURCE_ENCODER; 87 88 return DPU_CRTC_CRC_SOURCE_INVALID; 89 } 90 91 static int dpu_crtc_verify_crc_source(struct drm_crtc *crtc, 92 const char *src_name, size_t *values_cnt) 93 { 94 enum dpu_crtc_crc_source source = dpu_crtc_parse_crc_source(src_name); 95 struct dpu_crtc_state *crtc_state = to_dpu_crtc_state(crtc->state); 96 97 if (source < 0) { 98 DRM_DEBUG_DRIVER("Invalid source %s for CRTC%d\n", src_name, crtc->index); 99 return -EINVAL; 100 } 101 102 if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER) { 103 *values_cnt = crtc_state->num_mixers; 104 } else if (source == DPU_CRTC_CRC_SOURCE_ENCODER) { 105 struct drm_encoder *drm_enc; 106 107 *values_cnt = 0; 108 109 drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask) 110 *values_cnt += dpu_encoder_get_crc_values_cnt(drm_enc); 111 } 112 113 return 0; 114 } 115 116 static void dpu_crtc_setup_lm_misr(struct dpu_crtc_state *crtc_state) 117 { 118 struct dpu_crtc_mixer *m; 119 int i; 120 121 for (i = 0; i < crtc_state->num_mixers; ++i) { 122 m = &crtc_state->mixers[i]; 123 124 if (!m->hw_lm || !m->hw_lm->ops.setup_misr) 125 continue; 126 127 /* Calculate MISR over 1 frame */ 128 m->hw_lm->ops.setup_misr(m->hw_lm, true, 1); 129 } 130 } 131 132 static void dpu_crtc_setup_encoder_misr(struct drm_crtc *crtc) 133 { 134 struct drm_encoder *drm_enc; 135 136 drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask) 137 dpu_encoder_setup_misr(drm_enc); 138 } 139 140 static int dpu_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) 141 { 142 enum dpu_crtc_crc_source source = dpu_crtc_parse_crc_source(src_name); 143 enum dpu_crtc_crc_source current_source; 144 struct dpu_crtc_state *crtc_state; 145 struct drm_device *drm_dev = crtc->dev; 146 147 bool was_enabled; 148 bool enable = false; 149 int ret = 0; 150 151 if (source < 0) { 152 DRM_DEBUG_DRIVER("Invalid CRC source %s for CRTC%d\n", src_name, crtc->index); 153 return -EINVAL; 154 } 155 156 ret = drm_modeset_lock(&crtc->mutex, NULL); 157 158 if (ret) 159 return ret; 160 161 enable = (source != DPU_CRTC_CRC_SOURCE_NONE); 162 crtc_state = to_dpu_crtc_state(crtc->state); 163 164 spin_lock_irq(&drm_dev->event_lock); 165 current_source = crtc_state->crc_source; 166 spin_unlock_irq(&drm_dev->event_lock); 167 168 was_enabled = (current_source != DPU_CRTC_CRC_SOURCE_NONE); 169 170 if (!was_enabled && enable) { 171 ret = drm_crtc_vblank_get(crtc); 172 173 if (ret) 174 goto cleanup; 175 176 } else if (was_enabled && !enable) { 177 drm_crtc_vblank_put(crtc); 178 } 179 180 spin_lock_irq(&drm_dev->event_lock); 181 crtc_state->crc_source = source; 182 spin_unlock_irq(&drm_dev->event_lock); 183 184 crtc_state->crc_frame_skip_count = 0; 185 186 if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER) 187 dpu_crtc_setup_lm_misr(crtc_state); 188 else if (source == DPU_CRTC_CRC_SOURCE_ENCODER) 189 dpu_crtc_setup_encoder_misr(crtc); 190 else 191 ret = -EINVAL; 192 193 cleanup: 194 drm_modeset_unlock(&crtc->mutex); 195 196 return ret; 197 } 198 199 static u32 dpu_crtc_get_vblank_counter(struct drm_crtc *crtc) 200 { 201 struct drm_encoder *encoder = get_encoder_from_crtc(crtc); 202 if (!encoder) { 203 DRM_ERROR("no encoder found for crtc %d\n", crtc->index); 204 return 0; 205 } 206 207 return dpu_encoder_get_vsync_count(encoder); 208 } 209 210 static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc, 211 struct dpu_crtc_state *crtc_state) 212 { 213 struct dpu_crtc_mixer *m; 214 u32 crcs[CRTC_DUAL_MIXERS]; 215 216 int rc = 0; 217 int i; 218 219 BUILD_BUG_ON(ARRAY_SIZE(crcs) != ARRAY_SIZE(crtc_state->mixers)); 220 221 for (i = 0; i < crtc_state->num_mixers; ++i) { 222 223 m = &crtc_state->mixers[i]; 224 225 if (!m->hw_lm || !m->hw_lm->ops.collect_misr) 226 continue; 227 228 rc = m->hw_lm->ops.collect_misr(m->hw_lm, &crcs[i]); 229 230 if (rc) { 231 if (rc != -ENODATA) 232 DRM_DEBUG_DRIVER("MISR read failed\n"); 233 return rc; 234 } 235 } 236 237 return drm_crtc_add_crc_entry(crtc, true, 238 drm_crtc_accurate_vblank_count(crtc), crcs); 239 } 240 241 static int dpu_crtc_get_encoder_crc(struct drm_crtc *crtc) 242 { 243 struct drm_encoder *drm_enc; 244 int rc, pos = 0; 245 u32 crcs[INTF_MAX]; 246 247 drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask) { 248 rc = dpu_encoder_get_crc(drm_enc, crcs, pos); 249 if (rc < 0) { 250 if (rc != -ENODATA) 251 DRM_DEBUG_DRIVER("MISR read failed\n"); 252 253 return rc; 254 } 255 256 pos += rc; 257 } 258 259 return drm_crtc_add_crc_entry(crtc, true, 260 drm_crtc_accurate_vblank_count(crtc), crcs); 261 } 262 263 static int dpu_crtc_get_crc(struct drm_crtc *crtc) 264 { 265 struct dpu_crtc_state *crtc_state = to_dpu_crtc_state(crtc->state); 266 267 /* Skip first 2 frames in case of "uncooked" CRCs */ 268 if (crtc_state->crc_frame_skip_count < 2) { 269 crtc_state->crc_frame_skip_count++; 270 return 0; 271 } 272 273 if (crtc_state->crc_source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER) 274 return dpu_crtc_get_lm_crc(crtc, crtc_state); 275 else if (crtc_state->crc_source == DPU_CRTC_CRC_SOURCE_ENCODER) 276 return dpu_crtc_get_encoder_crc(crtc); 277 278 return -EINVAL; 279 } 280 281 static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc, 282 bool in_vblank_irq, 283 int *vpos, int *hpos, 284 ktime_t *stime, ktime_t *etime, 285 const struct drm_display_mode *mode) 286 { 287 unsigned int pipe = crtc->index; 288 struct drm_encoder *encoder; 289 int line, vsw, vbp, vactive_start, vactive_end, vfp_end; 290 291 encoder = get_encoder_from_crtc(crtc); 292 if (!encoder) { 293 DRM_ERROR("no encoder found for crtc %d\n", pipe); 294 return false; 295 } 296 297 vsw = mode->crtc_vsync_end - mode->crtc_vsync_start; 298 vbp = mode->crtc_vtotal - mode->crtc_vsync_end; 299 300 /* 301 * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at 302 * the end of VFP. Translate the porch values relative to the line 303 * counter positions. 304 */ 305 306 vactive_start = vsw + vbp + 1; 307 vactive_end = vactive_start + mode->crtc_vdisplay; 308 309 /* last scan line before VSYNC */ 310 vfp_end = mode->crtc_vtotal; 311 312 if (stime) 313 *stime = ktime_get(); 314 315 line = dpu_encoder_get_linecount(encoder); 316 317 if (line < vactive_start) 318 line -= vactive_start; 319 else if (line > vactive_end) 320 line = line - vfp_end - vactive_start; 321 else 322 line -= vactive_start; 323 324 *vpos = line; 325 *hpos = 0; 326 327 if (etime) 328 *etime = ktime_get(); 329 330 return true; 331 } 332 333 static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, 334 struct dpu_plane_state *pstate, struct dpu_format *format) 335 { 336 struct dpu_hw_mixer *lm = mixer->hw_lm; 337 uint32_t blend_op; 338 uint32_t fg_alpha, bg_alpha; 339 340 fg_alpha = pstate->base.alpha >> 8; 341 bg_alpha = 0xff - fg_alpha; 342 343 /* default to opaque blending */ 344 if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE || 345 !format->alpha_enable) { 346 blend_op = DPU_BLEND_FG_ALPHA_FG_CONST | 347 DPU_BLEND_BG_ALPHA_BG_CONST; 348 } else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) { 349 blend_op = DPU_BLEND_FG_ALPHA_FG_CONST | 350 DPU_BLEND_BG_ALPHA_FG_PIXEL; 351 if (fg_alpha != 0xff) { 352 bg_alpha = fg_alpha; 353 blend_op |= DPU_BLEND_BG_MOD_ALPHA | 354 DPU_BLEND_BG_INV_MOD_ALPHA; 355 } else { 356 blend_op |= DPU_BLEND_BG_INV_ALPHA; 357 } 358 } else { 359 /* coverage blending */ 360 blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL | 361 DPU_BLEND_BG_ALPHA_FG_PIXEL; 362 if (fg_alpha != 0xff) { 363 bg_alpha = fg_alpha; 364 blend_op |= DPU_BLEND_FG_MOD_ALPHA | 365 DPU_BLEND_FG_INV_MOD_ALPHA | 366 DPU_BLEND_BG_MOD_ALPHA | 367 DPU_BLEND_BG_INV_MOD_ALPHA; 368 } else { 369 blend_op |= DPU_BLEND_BG_INV_ALPHA; 370 } 371 } 372 373 lm->ops.setup_blend_config(lm, pstate->stage, 374 fg_alpha, bg_alpha, blend_op); 375 376 DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n", 377 &format->base.pixel_format, format->alpha_enable, blend_op); 378 } 379 380 static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) 381 { 382 struct dpu_crtc_state *crtc_state; 383 int lm_idx, lm_horiz_position; 384 385 crtc_state = to_dpu_crtc_state(crtc->state); 386 387 lm_horiz_position = 0; 388 for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) { 389 const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx]; 390 struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm; 391 struct dpu_hw_mixer_cfg cfg; 392 393 if (!lm_roi || !drm_rect_visible(lm_roi)) 394 continue; 395 396 cfg.out_width = drm_rect_width(lm_roi); 397 cfg.out_height = drm_rect_height(lm_roi); 398 cfg.right_mixer = lm_horiz_position++; 399 cfg.flags = 0; 400 hw_lm->ops.setup_mixer_out(hw_lm, &cfg); 401 } 402 } 403 404 static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, 405 struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer, 406 struct dpu_hw_stage_cfg *stage_cfg) 407 { 408 struct drm_plane *plane; 409 struct drm_framebuffer *fb; 410 struct drm_plane_state *state; 411 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 412 struct dpu_plane_state *pstate = NULL; 413 struct dpu_format *format; 414 struct dpu_hw_ctl *ctl = mixer->lm_ctl; 415 416 uint32_t stage_idx, lm_idx; 417 int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 }; 418 bool bg_alpha_enable = false; 419 DECLARE_BITMAP(fetch_active, SSPP_MAX); 420 421 memset(fetch_active, 0, sizeof(fetch_active)); 422 drm_atomic_crtc_for_each_plane(plane, crtc) { 423 enum dpu_sspp sspp_idx; 424 425 state = plane->state; 426 if (!state) 427 continue; 428 429 if (!state->visible) 430 continue; 431 432 pstate = to_dpu_plane_state(state); 433 fb = state->fb; 434 435 sspp_idx = pstate->pipe.sspp->idx; 436 set_bit(sspp_idx, fetch_active); 437 438 DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n", 439 crtc->base.id, 440 pstate->stage, 441 plane->base.id, 442 sspp_idx - SSPP_VIG0, 443 state->fb ? state->fb->base.id : -1); 444 445 format = to_dpu_format(msm_framebuffer_format(pstate->base.fb)); 446 447 if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) 448 bg_alpha_enable = true; 449 450 stage_idx = zpos_cnt[pstate->stage]++; 451 stage_cfg->stage[pstate->stage][stage_idx] = 452 sspp_idx; 453 stage_cfg->multirect_index[pstate->stage][stage_idx] = 454 pstate->pipe.multirect_index; 455 456 trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), 457 state, pstate, stage_idx, 458 format->base.pixel_format, 459 fb ? fb->modifier : 0); 460 461 /* blend config update */ 462 for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) { 463 _dpu_crtc_setup_blend_cfg(mixer + lm_idx, 464 pstate, format); 465 466 mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl, 467 sspp_idx); 468 469 if (bg_alpha_enable && !format->alpha_enable) 470 mixer[lm_idx].mixer_op_mode = 0; 471 else 472 mixer[lm_idx].mixer_op_mode |= 473 1 << pstate->stage; 474 } 475 } 476 477 if (ctl->ops.set_active_pipes) 478 ctl->ops.set_active_pipes(ctl, fetch_active); 479 480 _dpu_crtc_program_lm_output_roi(crtc); 481 } 482 483 /** 484 * _dpu_crtc_blend_setup - configure crtc mixers 485 * @crtc: Pointer to drm crtc structure 486 */ 487 static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) 488 { 489 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 490 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 491 struct dpu_crtc_mixer *mixer = cstate->mixers; 492 struct dpu_hw_ctl *ctl; 493 struct dpu_hw_mixer *lm; 494 struct dpu_hw_stage_cfg stage_cfg; 495 int i; 496 497 DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name); 498 499 for (i = 0; i < cstate->num_mixers; i++) { 500 mixer[i].mixer_op_mode = 0; 501 if (mixer[i].lm_ctl->ops.clear_all_blendstages) 502 mixer[i].lm_ctl->ops.clear_all_blendstages( 503 mixer[i].lm_ctl); 504 } 505 506 /* initialize stage cfg */ 507 memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg)); 508 509 _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg); 510 511 for (i = 0; i < cstate->num_mixers; i++) { 512 ctl = mixer[i].lm_ctl; 513 lm = mixer[i].hw_lm; 514 515 lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode); 516 517 /* stage config flush mask */ 518 ctl->ops.update_pending_flush_mixer(ctl, 519 mixer[i].hw_lm->idx); 520 521 DRM_DEBUG_ATOMIC("lm %d, op_mode 0x%X, ctl %d\n", 522 mixer[i].hw_lm->idx - LM_0, 523 mixer[i].mixer_op_mode, 524 ctl->idx - CTL_0); 525 526 ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, 527 &stage_cfg); 528 } 529 } 530 531 /** 532 * _dpu_crtc_complete_flip - signal pending page_flip events 533 * Any pending vblank events are added to the vblank_event_list 534 * so that the next vblank interrupt shall signal them. 535 * However PAGE_FLIP events are not handled through the vblank_event_list. 536 * This API signals any pending PAGE_FLIP events requested through 537 * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the dpu_crtc->event. 538 * @crtc: Pointer to drm crtc structure 539 */ 540 static void _dpu_crtc_complete_flip(struct drm_crtc *crtc) 541 { 542 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 543 struct drm_device *dev = crtc->dev; 544 unsigned long flags; 545 546 spin_lock_irqsave(&dev->event_lock, flags); 547 if (dpu_crtc->event) { 548 DRM_DEBUG_VBL("%s: send event: %pK\n", dpu_crtc->name, 549 dpu_crtc->event); 550 trace_dpu_crtc_complete_flip(DRMID(crtc)); 551 drm_crtc_send_vblank_event(crtc, dpu_crtc->event); 552 dpu_crtc->event = NULL; 553 } 554 spin_unlock_irqrestore(&dev->event_lock, flags); 555 } 556 557 enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc) 558 { 559 struct drm_encoder *encoder; 560 561 /* 562 * TODO: This function is called from dpu debugfs and as part of atomic 563 * check. When called from debugfs, the crtc->mutex must be held to 564 * read crtc->state. However reading crtc->state from atomic check isn't 565 * allowed (unless you have a good reason, a big comment, and a deep 566 * understanding of how the atomic/modeset locks work (<- and this is 567 * probably not possible)). So we'll keep the WARN_ON here for now, but 568 * really we need to figure out a better way to track our operating mode 569 */ 570 WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); 571 572 /* TODO: Returns the first INTF_MODE, could there be multiple values? */ 573 drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) 574 return dpu_encoder_get_intf_mode(encoder); 575 576 return INTF_MODE_NONE; 577 } 578 579 void dpu_crtc_vblank_callback(struct drm_crtc *crtc) 580 { 581 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 582 583 /* keep statistics on vblank callback - with auto reset via debugfs */ 584 if (ktime_compare(dpu_crtc->vblank_cb_time, ktime_set(0, 0)) == 0) 585 dpu_crtc->vblank_cb_time = ktime_get(); 586 else 587 dpu_crtc->vblank_cb_count++; 588 589 dpu_crtc_get_crc(crtc); 590 591 drm_crtc_handle_vblank(crtc); 592 trace_dpu_crtc_vblank_cb(DRMID(crtc)); 593 } 594 595 static void dpu_crtc_frame_event_work(struct kthread_work *work) 596 { 597 struct dpu_crtc_frame_event *fevent = container_of(work, 598 struct dpu_crtc_frame_event, work); 599 struct drm_crtc *crtc = fevent->crtc; 600 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 601 unsigned long flags; 602 bool frame_done = false; 603 604 DPU_ATRACE_BEGIN("crtc_frame_event"); 605 606 DRM_DEBUG_ATOMIC("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event, 607 ktime_to_ns(fevent->ts)); 608 609 if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE 610 | DPU_ENCODER_FRAME_EVENT_ERROR 611 | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) { 612 613 if (atomic_read(&dpu_crtc->frame_pending) < 1) { 614 /* ignore vblank when not pending */ 615 } else if (atomic_dec_return(&dpu_crtc->frame_pending) == 0) { 616 /* release bandwidth and other resources */ 617 trace_dpu_crtc_frame_event_done(DRMID(crtc), 618 fevent->event); 619 dpu_core_perf_crtc_release_bw(crtc); 620 } else { 621 trace_dpu_crtc_frame_event_more_pending(DRMID(crtc), 622 fevent->event); 623 } 624 625 if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE 626 | DPU_ENCODER_FRAME_EVENT_ERROR)) 627 frame_done = true; 628 } 629 630 if (fevent->event & DPU_ENCODER_FRAME_EVENT_PANEL_DEAD) 631 DPU_ERROR("crtc%d ts:%lld received panel dead event\n", 632 crtc->base.id, ktime_to_ns(fevent->ts)); 633 634 if (frame_done) 635 complete_all(&dpu_crtc->frame_done_comp); 636 637 spin_lock_irqsave(&dpu_crtc->spin_lock, flags); 638 list_add_tail(&fevent->list, &dpu_crtc->frame_event_list); 639 spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags); 640 DPU_ATRACE_END("crtc_frame_event"); 641 } 642 643 /* 644 * dpu_crtc_frame_event_cb - crtc frame event callback API. CRTC module 645 * registers this API to encoder for all frame event callbacks like 646 * frame_error, frame_done, idle_timeout, etc. Encoder may call different events 647 * from different context - IRQ, user thread, commit_thread, etc. Each event 648 * should be carefully reviewed and should be processed in proper task context 649 * to avoid schedulin delay or properly manage the irq context's bottom half 650 * processing. 651 */ 652 static void dpu_crtc_frame_event_cb(void *data, u32 event) 653 { 654 struct drm_crtc *crtc = (struct drm_crtc *)data; 655 struct dpu_crtc *dpu_crtc; 656 struct msm_drm_private *priv; 657 struct dpu_crtc_frame_event *fevent; 658 unsigned long flags; 659 u32 crtc_id; 660 661 /* Nothing to do on idle event */ 662 if (event & DPU_ENCODER_FRAME_EVENT_IDLE) 663 return; 664 665 dpu_crtc = to_dpu_crtc(crtc); 666 priv = crtc->dev->dev_private; 667 crtc_id = drm_crtc_index(crtc); 668 669 trace_dpu_crtc_frame_event_cb(DRMID(crtc), event); 670 671 spin_lock_irqsave(&dpu_crtc->spin_lock, flags); 672 fevent = list_first_entry_or_null(&dpu_crtc->frame_event_list, 673 struct dpu_crtc_frame_event, list); 674 if (fevent) 675 list_del_init(&fevent->list); 676 spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags); 677 678 if (!fevent) { 679 DRM_ERROR_RATELIMITED("crtc%d event %d overflow\n", crtc->base.id, event); 680 return; 681 } 682 683 fevent->event = event; 684 fevent->crtc = crtc; 685 fevent->ts = ktime_get(); 686 kthread_queue_work(priv->event_thread[crtc_id].worker, &fevent->work); 687 } 688 689 void dpu_crtc_complete_commit(struct drm_crtc *crtc) 690 { 691 trace_dpu_crtc_complete_commit(DRMID(crtc)); 692 dpu_core_perf_crtc_update(crtc, 0, false); 693 _dpu_crtc_complete_flip(crtc); 694 } 695 696 static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc, 697 struct drm_crtc_state *state) 698 { 699 struct dpu_crtc_state *cstate = to_dpu_crtc_state(state); 700 struct drm_display_mode *adj_mode = &state->adjusted_mode; 701 u32 crtc_split_width = adj_mode->hdisplay / cstate->num_mixers; 702 int i; 703 704 for (i = 0; i < cstate->num_mixers; i++) { 705 struct drm_rect *r = &cstate->lm_bounds[i]; 706 r->x1 = crtc_split_width * i; 707 r->y1 = 0; 708 r->x2 = r->x1 + crtc_split_width; 709 r->y2 = adj_mode->vdisplay; 710 711 trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i, r); 712 } 713 } 714 715 static void _dpu_crtc_get_pcc_coeff(struct drm_crtc_state *state, 716 struct dpu_hw_pcc_cfg *cfg) 717 { 718 struct drm_color_ctm *ctm; 719 720 memset(cfg, 0, sizeof(struct dpu_hw_pcc_cfg)); 721 722 ctm = (struct drm_color_ctm *)state->ctm->data; 723 724 if (!ctm) 725 return; 726 727 cfg->r.r = CONVERT_S3_15(ctm->matrix[0]); 728 cfg->g.r = CONVERT_S3_15(ctm->matrix[1]); 729 cfg->b.r = CONVERT_S3_15(ctm->matrix[2]); 730 731 cfg->r.g = CONVERT_S3_15(ctm->matrix[3]); 732 cfg->g.g = CONVERT_S3_15(ctm->matrix[4]); 733 cfg->b.g = CONVERT_S3_15(ctm->matrix[5]); 734 735 cfg->r.b = CONVERT_S3_15(ctm->matrix[6]); 736 cfg->g.b = CONVERT_S3_15(ctm->matrix[7]); 737 cfg->b.b = CONVERT_S3_15(ctm->matrix[8]); 738 } 739 740 static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc) 741 { 742 struct drm_crtc_state *state = crtc->state; 743 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 744 struct dpu_crtc_mixer *mixer = cstate->mixers; 745 struct dpu_hw_pcc_cfg cfg; 746 struct dpu_hw_ctl *ctl; 747 struct dpu_hw_dspp *dspp; 748 int i; 749 750 751 if (!state->color_mgmt_changed && !drm_atomic_crtc_needs_modeset(state)) 752 return; 753 754 for (i = 0; i < cstate->num_mixers; i++) { 755 ctl = mixer[i].lm_ctl; 756 dspp = mixer[i].hw_dspp; 757 758 if (!dspp || !dspp->ops.setup_pcc) 759 continue; 760 761 if (!state->ctm) { 762 dspp->ops.setup_pcc(dspp, NULL); 763 } else { 764 _dpu_crtc_get_pcc_coeff(state, &cfg); 765 dspp->ops.setup_pcc(dspp, &cfg); 766 } 767 768 /* stage config flush mask */ 769 ctl->ops.update_pending_flush_dspp(ctl, 770 mixer[i].hw_dspp->idx, DPU_DSPP_PCC); 771 } 772 } 773 774 static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, 775 struct drm_atomic_state *state) 776 { 777 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 778 struct drm_encoder *encoder; 779 780 if (!crtc->state->enable) { 781 DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_begin\n", 782 crtc->base.id, crtc->state->enable); 783 return; 784 } 785 786 DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id); 787 788 _dpu_crtc_setup_lm_bounds(crtc, crtc->state); 789 790 /* encoder will trigger pending mask now */ 791 drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) 792 dpu_encoder_trigger_kickoff_pending(encoder); 793 794 /* 795 * If no mixers have been allocated in dpu_crtc_atomic_check(), 796 * it means we are trying to flush a CRTC whose state is disabled: 797 * nothing else needs to be done. 798 */ 799 if (unlikely(!cstate->num_mixers)) 800 return; 801 802 _dpu_crtc_blend_setup(crtc); 803 804 _dpu_crtc_setup_cp_blocks(crtc); 805 806 /* 807 * PP_DONE irq is only used by command mode for now. 808 * It is better to request pending before FLUSH and START trigger 809 * to make sure no pp_done irq missed. 810 * This is safe because no pp_done will happen before SW trigger 811 * in command mode. 812 */ 813 } 814 815 static void dpu_crtc_atomic_flush(struct drm_crtc *crtc, 816 struct drm_atomic_state *state) 817 { 818 struct dpu_crtc *dpu_crtc; 819 struct drm_device *dev; 820 struct drm_plane *plane; 821 struct msm_drm_private *priv; 822 unsigned long flags; 823 struct dpu_crtc_state *cstate; 824 825 if (!crtc->state->enable) { 826 DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_flush\n", 827 crtc->base.id, crtc->state->enable); 828 return; 829 } 830 831 DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id); 832 833 dpu_crtc = to_dpu_crtc(crtc); 834 cstate = to_dpu_crtc_state(crtc->state); 835 dev = crtc->dev; 836 priv = dev->dev_private; 837 838 if (crtc->index >= ARRAY_SIZE(priv->event_thread)) { 839 DPU_ERROR("invalid crtc index[%d]\n", crtc->index); 840 return; 841 } 842 843 WARN_ON(dpu_crtc->event); 844 spin_lock_irqsave(&dev->event_lock, flags); 845 dpu_crtc->event = crtc->state->event; 846 crtc->state->event = NULL; 847 spin_unlock_irqrestore(&dev->event_lock, flags); 848 849 /* 850 * If no mixers has been allocated in dpu_crtc_atomic_check(), 851 * it means we are trying to flush a CRTC whose state is disabled: 852 * nothing else needs to be done. 853 */ 854 if (unlikely(!cstate->num_mixers)) 855 return; 856 857 /* update performance setting before crtc kickoff */ 858 dpu_core_perf_crtc_update(crtc, 1, false); 859 860 /* 861 * Final plane updates: Give each plane a chance to complete all 862 * required writes/flushing before crtc's "flush 863 * everything" call below. 864 */ 865 drm_atomic_crtc_for_each_plane(plane, crtc) { 866 if (dpu_crtc->smmu_state.transition_error) 867 dpu_plane_set_error(plane, true); 868 dpu_plane_flush(plane); 869 } 870 871 /* Kickoff will be scheduled by outer layer */ 872 } 873 874 /** 875 * dpu_crtc_destroy_state - state destroy hook 876 * @crtc: drm CRTC 877 * @state: CRTC state object to release 878 */ 879 static void dpu_crtc_destroy_state(struct drm_crtc *crtc, 880 struct drm_crtc_state *state) 881 { 882 struct dpu_crtc_state *cstate = to_dpu_crtc_state(state); 883 884 DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id); 885 886 __drm_atomic_helper_crtc_destroy_state(state); 887 888 kfree(cstate); 889 } 890 891 static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc) 892 { 893 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 894 int ret, rc = 0; 895 896 if (!atomic_read(&dpu_crtc->frame_pending)) { 897 DRM_DEBUG_ATOMIC("no frames pending\n"); 898 return 0; 899 } 900 901 DPU_ATRACE_BEGIN("frame done completion wait"); 902 ret = wait_for_completion_timeout(&dpu_crtc->frame_done_comp, 903 msecs_to_jiffies(DPU_CRTC_FRAME_DONE_TIMEOUT_MS)); 904 if (!ret) { 905 DRM_ERROR("frame done wait timed out, ret:%d\n", ret); 906 rc = -ETIMEDOUT; 907 } 908 DPU_ATRACE_END("frame done completion wait"); 909 910 return rc; 911 } 912 913 void dpu_crtc_commit_kickoff(struct drm_crtc *crtc) 914 { 915 struct drm_encoder *encoder; 916 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 917 struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); 918 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 919 920 /* 921 * If no mixers has been allocated in dpu_crtc_atomic_check(), 922 * it means we are trying to start a CRTC whose state is disabled: 923 * nothing else needs to be done. 924 */ 925 if (unlikely(!cstate->num_mixers)) 926 return; 927 928 DPU_ATRACE_BEGIN("crtc_commit"); 929 930 drm_for_each_encoder_mask(encoder, crtc->dev, 931 crtc->state->encoder_mask) { 932 if (!dpu_encoder_is_valid_for_commit(encoder)) { 933 DRM_DEBUG_ATOMIC("invalid FB not kicking off crtc\n"); 934 goto end; 935 } 936 } 937 /* 938 * Encoder will flush/start now, unless it has a tx pending. If so, it 939 * may delay and flush at an irq event (e.g. ppdone) 940 */ 941 drm_for_each_encoder_mask(encoder, crtc->dev, 942 crtc->state->encoder_mask) 943 dpu_encoder_prepare_for_kickoff(encoder); 944 945 if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) { 946 /* acquire bandwidth and other resources */ 947 DRM_DEBUG_ATOMIC("crtc%d first commit\n", crtc->base.id); 948 } else 949 DRM_DEBUG_ATOMIC("crtc%d commit\n", crtc->base.id); 950 951 dpu_crtc->play_count++; 952 953 dpu_vbif_clear_errors(dpu_kms); 954 955 drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) 956 dpu_encoder_kickoff(encoder); 957 958 reinit_completion(&dpu_crtc->frame_done_comp); 959 960 end: 961 DPU_ATRACE_END("crtc_commit"); 962 } 963 964 static void dpu_crtc_reset(struct drm_crtc *crtc) 965 { 966 struct dpu_crtc_state *cstate = kzalloc(sizeof(*cstate), GFP_KERNEL); 967 968 if (crtc->state) 969 dpu_crtc_destroy_state(crtc, crtc->state); 970 971 if (cstate) 972 __drm_atomic_helper_crtc_reset(crtc, &cstate->base); 973 else 974 __drm_atomic_helper_crtc_reset(crtc, NULL); 975 } 976 977 /** 978 * dpu_crtc_duplicate_state - state duplicate hook 979 * @crtc: Pointer to drm crtc structure 980 */ 981 static struct drm_crtc_state *dpu_crtc_duplicate_state(struct drm_crtc *crtc) 982 { 983 struct dpu_crtc_state *cstate, *old_cstate = to_dpu_crtc_state(crtc->state); 984 985 cstate = kmemdup(old_cstate, sizeof(*old_cstate), GFP_KERNEL); 986 if (!cstate) { 987 DPU_ERROR("failed to allocate state\n"); 988 return NULL; 989 } 990 991 /* duplicate base helper */ 992 __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base); 993 994 return &cstate->base; 995 } 996 997 static void dpu_crtc_atomic_print_state(struct drm_printer *p, 998 const struct drm_crtc_state *state) 999 { 1000 const struct dpu_crtc_state *cstate = to_dpu_crtc_state(state); 1001 int i; 1002 1003 for (i = 0; i < cstate->num_mixers; i++) { 1004 drm_printf(p, "\tlm[%d]=%d\n", i, cstate->mixers[i].hw_lm->idx - LM_0); 1005 drm_printf(p, "\tctl[%d]=%d\n", i, cstate->mixers[i].lm_ctl->idx - CTL_0); 1006 if (cstate->mixers[i].hw_dspp) 1007 drm_printf(p, "\tdspp[%d]=%d\n", i, cstate->mixers[i].hw_dspp->idx - DSPP_0); 1008 } 1009 } 1010 1011 static void dpu_crtc_disable(struct drm_crtc *crtc, 1012 struct drm_atomic_state *state) 1013 { 1014 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, 1015 crtc); 1016 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 1017 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 1018 struct drm_encoder *encoder; 1019 unsigned long flags; 1020 bool release_bandwidth = false; 1021 1022 DRM_DEBUG_KMS("crtc%d\n", crtc->base.id); 1023 1024 /* If disable is triggered while in self refresh mode, 1025 * reset the encoder software state so that in enable 1026 * it won't trigger a warn while assigning crtc. 1027 */ 1028 if (old_crtc_state->self_refresh_active) { 1029 drm_for_each_encoder_mask(encoder, crtc->dev, 1030 old_crtc_state->encoder_mask) { 1031 dpu_encoder_assign_crtc(encoder, NULL); 1032 } 1033 return; 1034 } 1035 1036 /* Disable/save vblank irq handling */ 1037 drm_crtc_vblank_off(crtc); 1038 1039 drm_for_each_encoder_mask(encoder, crtc->dev, 1040 old_crtc_state->encoder_mask) { 1041 /* in video mode, we hold an extra bandwidth reference 1042 * as we cannot drop bandwidth at frame-done if any 1043 * crtc is being used in video mode. 1044 */ 1045 if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO) 1046 release_bandwidth = true; 1047 1048 /* 1049 * If disable is triggered during psr active(e.g: screen dim in PSR), 1050 * we will need encoder->crtc connection to process the device sleep & 1051 * preserve it during psr sequence. 1052 */ 1053 if (!crtc->state->self_refresh_active) 1054 dpu_encoder_assign_crtc(encoder, NULL); 1055 } 1056 1057 /* wait for frame_event_done completion */ 1058 if (_dpu_crtc_wait_for_frame_done(crtc)) 1059 DPU_ERROR("crtc%d wait for frame done failed;frame_pending%d\n", 1060 crtc->base.id, 1061 atomic_read(&dpu_crtc->frame_pending)); 1062 1063 trace_dpu_crtc_disable(DRMID(crtc), false, dpu_crtc); 1064 dpu_crtc->enabled = false; 1065 1066 if (atomic_read(&dpu_crtc->frame_pending)) { 1067 trace_dpu_crtc_disable_frame_pending(DRMID(crtc), 1068 atomic_read(&dpu_crtc->frame_pending)); 1069 if (release_bandwidth) 1070 dpu_core_perf_crtc_release_bw(crtc); 1071 atomic_set(&dpu_crtc->frame_pending, 0); 1072 } 1073 1074 dpu_core_perf_crtc_update(crtc, 0, true); 1075 1076 drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) 1077 dpu_encoder_register_frame_event_callback(encoder, NULL, NULL); 1078 1079 memset(cstate->mixers, 0, sizeof(cstate->mixers)); 1080 cstate->num_mixers = 0; 1081 1082 /* disable clk & bw control until clk & bw properties are set */ 1083 cstate->bw_control = false; 1084 cstate->bw_split_vote = false; 1085 1086 if (crtc->state->event && !crtc->state->active) { 1087 spin_lock_irqsave(&crtc->dev->event_lock, flags); 1088 drm_crtc_send_vblank_event(crtc, crtc->state->event); 1089 crtc->state->event = NULL; 1090 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 1091 } 1092 1093 pm_runtime_put_sync(crtc->dev->dev); 1094 } 1095 1096 static void dpu_crtc_enable(struct drm_crtc *crtc, 1097 struct drm_atomic_state *state) 1098 { 1099 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 1100 struct drm_encoder *encoder; 1101 bool request_bandwidth = false; 1102 struct drm_crtc_state *old_crtc_state; 1103 1104 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); 1105 1106 pm_runtime_get_sync(crtc->dev->dev); 1107 1108 DRM_DEBUG_KMS("crtc%d\n", crtc->base.id); 1109 1110 drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) { 1111 /* in video mode, we hold an extra bandwidth reference 1112 * as we cannot drop bandwidth at frame-done if any 1113 * crtc is being used in video mode. 1114 */ 1115 if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO) 1116 request_bandwidth = true; 1117 dpu_encoder_register_frame_event_callback(encoder, 1118 dpu_crtc_frame_event_cb, (void *)crtc); 1119 } 1120 1121 if (request_bandwidth) 1122 atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref); 1123 1124 trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc); 1125 dpu_crtc->enabled = true; 1126 1127 if (!old_crtc_state->self_refresh_active) { 1128 drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) 1129 dpu_encoder_assign_crtc(encoder, crtc); 1130 } 1131 1132 /* Enable/restore vblank irq handling */ 1133 drm_crtc_vblank_on(crtc); 1134 } 1135 1136 static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate) 1137 { 1138 struct drm_crtc *crtc = cstate->crtc; 1139 struct drm_encoder *encoder; 1140 1141 drm_for_each_encoder_mask (encoder, crtc->dev, cstate->encoder_mask) { 1142 if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_CMD) { 1143 return true; 1144 } 1145 } 1146 1147 return false; 1148 } 1149 1150 static int dpu_crtc_atomic_check(struct drm_crtc *crtc, 1151 struct drm_atomic_state *state) 1152 { 1153 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 1154 crtc); 1155 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 1156 struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state); 1157 1158 const struct drm_plane_state *pstate; 1159 struct drm_plane *plane; 1160 struct drm_display_mode *mode; 1161 1162 int rc = 0; 1163 1164 struct drm_rect crtc_rect = { 0 }; 1165 bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state); 1166 1167 if (!crtc_state->enable || !crtc_state->active) { 1168 DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n", 1169 crtc->base.id, crtc_state->enable, 1170 crtc_state->active); 1171 memset(&cstate->new_perf, 0, sizeof(cstate->new_perf)); 1172 return 0; 1173 } 1174 1175 mode = &crtc_state->adjusted_mode; 1176 DRM_DEBUG_ATOMIC("%s: check\n", dpu_crtc->name); 1177 1178 /* force a full mode set if active state changed */ 1179 if (crtc_state->active_changed) 1180 crtc_state->mode_changed = true; 1181 1182 if (cstate->num_mixers) 1183 _dpu_crtc_setup_lm_bounds(crtc, crtc_state); 1184 1185 crtc_rect.x2 = mode->hdisplay; 1186 crtc_rect.y2 = mode->vdisplay; 1187 1188 /* get plane state for all drm planes associated with crtc state */ 1189 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) { 1190 struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate); 1191 struct drm_rect dst, clip = crtc_rect; 1192 int z_pos; 1193 1194 if (IS_ERR_OR_NULL(pstate)) { 1195 rc = PTR_ERR(pstate); 1196 DPU_ERROR("%s: failed to get plane%d state, %d\n", 1197 dpu_crtc->name, plane->base.id, rc); 1198 return rc; 1199 } 1200 1201 if (!pstate->visible) 1202 continue; 1203 1204 dpu_pstate->needs_dirtyfb = needs_dirtyfb; 1205 1206 dpu_plane_clear_multirect(pstate); 1207 1208 dst = drm_plane_state_dest(pstate); 1209 if (!drm_rect_intersect(&clip, &dst)) { 1210 DPU_ERROR("invalid vertical/horizontal destination\n"); 1211 DPU_ERROR("display: " DRM_RECT_FMT " plane: " 1212 DRM_RECT_FMT "\n", DRM_RECT_ARG(&crtc_rect), 1213 DRM_RECT_ARG(&dst)); 1214 return -E2BIG; 1215 } 1216 1217 z_pos = pstate->normalized_zpos; 1218 1219 /* verify z_pos setting before using it */ 1220 if (z_pos >= DPU_STAGE_MAX - DPU_STAGE_0) { 1221 DPU_ERROR("> %d plane stages assigned\n", 1222 DPU_STAGE_MAX - DPU_STAGE_0); 1223 return -EINVAL; 1224 } 1225 1226 to_dpu_plane_state(pstate)->stage = z_pos + DPU_STAGE_0; 1227 DRM_DEBUG_ATOMIC("%s: zpos %d\n", dpu_crtc->name, z_pos); 1228 1229 } 1230 1231 atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref); 1232 1233 rc = dpu_core_perf_crtc_check(crtc, crtc_state); 1234 if (rc) { 1235 DPU_ERROR("crtc%d failed performance check %d\n", 1236 crtc->base.id, rc); 1237 return rc; 1238 } 1239 1240 return 0; 1241 } 1242 1243 int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) 1244 { 1245 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 1246 struct drm_encoder *enc; 1247 1248 trace_dpu_crtc_vblank(DRMID(&dpu_crtc->base), en, dpu_crtc); 1249 1250 /* 1251 * Normally we would iterate through encoder_mask in crtc state to find 1252 * attached encoders. In this case, we might be disabling vblank _after_ 1253 * encoder_mask has been cleared. 1254 * 1255 * Instead, we "assign" a crtc to the encoder in enable and clear it in 1256 * disable (which is also after encoder_mask is cleared). So instead of 1257 * using encoder mask, we'll ask the encoder to toggle itself iff it's 1258 * currently assigned to our crtc. 1259 * 1260 * Note also that this function cannot be called while crtc is disabled 1261 * since we use drm_crtc_vblank_on/off. So we don't need to worry 1262 * about the assigned crtcs being inconsistent with the current state 1263 * (which means no need to worry about modeset locks). 1264 */ 1265 list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) { 1266 trace_dpu_crtc_vblank_enable(DRMID(crtc), DRMID(enc), en, 1267 dpu_crtc); 1268 1269 dpu_encoder_toggle_vblank_for_crtc(enc, crtc, en); 1270 } 1271 1272 return 0; 1273 } 1274 1275 #ifdef CONFIG_DEBUG_FS 1276 static int _dpu_debugfs_status_show(struct seq_file *s, void *data) 1277 { 1278 struct dpu_crtc *dpu_crtc; 1279 struct dpu_plane_state *pstate = NULL; 1280 struct dpu_crtc_mixer *m; 1281 1282 struct drm_crtc *crtc; 1283 struct drm_plane *plane; 1284 struct drm_display_mode *mode; 1285 struct drm_framebuffer *fb; 1286 struct drm_plane_state *state; 1287 struct dpu_crtc_state *cstate; 1288 1289 int i, out_width; 1290 1291 dpu_crtc = s->private; 1292 crtc = &dpu_crtc->base; 1293 1294 drm_modeset_lock_all(crtc->dev); 1295 cstate = to_dpu_crtc_state(crtc->state); 1296 1297 mode = &crtc->state->adjusted_mode; 1298 out_width = mode->hdisplay / cstate->num_mixers; 1299 1300 seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id, 1301 mode->hdisplay, mode->vdisplay); 1302 1303 seq_puts(s, "\n"); 1304 1305 for (i = 0; i < cstate->num_mixers; ++i) { 1306 m = &cstate->mixers[i]; 1307 seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n", 1308 m->hw_lm->idx - LM_0, m->lm_ctl->idx - CTL_0, 1309 out_width, mode->vdisplay); 1310 } 1311 1312 seq_puts(s, "\n"); 1313 1314 drm_atomic_crtc_for_each_plane(plane, crtc) { 1315 pstate = to_dpu_plane_state(plane->state); 1316 state = plane->state; 1317 1318 if (!pstate || !state) 1319 continue; 1320 1321 seq_printf(s, "\tplane:%u stage:%d\n", plane->base.id, 1322 pstate->stage); 1323 1324 if (plane->state->fb) { 1325 fb = plane->state->fb; 1326 1327 seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u ", 1328 fb->base.id, (char *) &fb->format->format, 1329 fb->width, fb->height); 1330 for (i = 0; i < ARRAY_SIZE(fb->format->cpp); ++i) 1331 seq_printf(s, "cpp[%d]:%u ", 1332 i, fb->format->cpp[i]); 1333 seq_puts(s, "\n\t"); 1334 1335 seq_printf(s, "modifier:%8llu ", fb->modifier); 1336 seq_puts(s, "\n"); 1337 1338 seq_puts(s, "\t"); 1339 for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) 1340 seq_printf(s, "pitches[%d]:%8u ", i, 1341 fb->pitches[i]); 1342 seq_puts(s, "\n"); 1343 1344 seq_puts(s, "\t"); 1345 for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) 1346 seq_printf(s, "offsets[%d]:%8u ", i, 1347 fb->offsets[i]); 1348 seq_puts(s, "\n"); 1349 } 1350 1351 seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n", 1352 state->src_x, state->src_y, state->src_w, state->src_h); 1353 1354 seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", 1355 state->crtc_x, state->crtc_y, state->crtc_w, 1356 state->crtc_h); 1357 seq_printf(s, "\tmultirect: mode: %d index: %d\n", 1358 pstate->pipe.multirect_mode, pstate->pipe.multirect_index); 1359 1360 seq_puts(s, "\n"); 1361 } 1362 if (dpu_crtc->vblank_cb_count) { 1363 ktime_t diff = ktime_sub(ktime_get(), dpu_crtc->vblank_cb_time); 1364 s64 diff_ms = ktime_to_ms(diff); 1365 s64 fps = diff_ms ? div_s64( 1366 dpu_crtc->vblank_cb_count * 1000, diff_ms) : 0; 1367 1368 seq_printf(s, 1369 "vblank fps:%lld count:%u total:%llums total_framecount:%llu\n", 1370 fps, dpu_crtc->vblank_cb_count, 1371 ktime_to_ms(diff), dpu_crtc->play_count); 1372 1373 /* reset time & count for next measurement */ 1374 dpu_crtc->vblank_cb_count = 0; 1375 dpu_crtc->vblank_cb_time = ktime_set(0, 0); 1376 } 1377 1378 drm_modeset_unlock_all(crtc->dev); 1379 1380 return 0; 1381 } 1382 1383 DEFINE_SHOW_ATTRIBUTE(_dpu_debugfs_status); 1384 1385 static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v) 1386 { 1387 struct drm_crtc *crtc = (struct drm_crtc *) s->private; 1388 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 1389 1390 seq_printf(s, "client type: %d\n", dpu_crtc_get_client_type(crtc)); 1391 seq_printf(s, "intf_mode: %d\n", dpu_crtc_get_intf_mode(crtc)); 1392 seq_printf(s, "core_clk_rate: %llu\n", 1393 dpu_crtc->cur_perf.core_clk_rate); 1394 seq_printf(s, "bw_ctl: %llu\n", dpu_crtc->cur_perf.bw_ctl); 1395 seq_printf(s, "max_per_pipe_ib: %llu\n", 1396 dpu_crtc->cur_perf.max_per_pipe_ib); 1397 1398 return 0; 1399 } 1400 DEFINE_SHOW_ATTRIBUTE(dpu_crtc_debugfs_state); 1401 1402 static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc) 1403 { 1404 struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 1405 1406 debugfs_create_file("status", 0400, 1407 crtc->debugfs_entry, 1408 dpu_crtc, &_dpu_debugfs_status_fops); 1409 debugfs_create_file("state", 0600, 1410 crtc->debugfs_entry, 1411 &dpu_crtc->base, 1412 &dpu_crtc_debugfs_state_fops); 1413 1414 return 0; 1415 } 1416 #else 1417 static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc) 1418 { 1419 return 0; 1420 } 1421 #endif /* CONFIG_DEBUG_FS */ 1422 1423 static int dpu_crtc_late_register(struct drm_crtc *crtc) 1424 { 1425 return _dpu_crtc_init_debugfs(crtc); 1426 } 1427 1428 static const struct drm_crtc_funcs dpu_crtc_funcs = { 1429 .set_config = drm_atomic_helper_set_config, 1430 .destroy = dpu_crtc_destroy, 1431 .page_flip = drm_atomic_helper_page_flip, 1432 .reset = dpu_crtc_reset, 1433 .atomic_duplicate_state = dpu_crtc_duplicate_state, 1434 .atomic_destroy_state = dpu_crtc_destroy_state, 1435 .atomic_print_state = dpu_crtc_atomic_print_state, 1436 .late_register = dpu_crtc_late_register, 1437 .verify_crc_source = dpu_crtc_verify_crc_source, 1438 .set_crc_source = dpu_crtc_set_crc_source, 1439 .enable_vblank = msm_crtc_enable_vblank, 1440 .disable_vblank = msm_crtc_disable_vblank, 1441 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 1442 .get_vblank_counter = dpu_crtc_get_vblank_counter, 1443 }; 1444 1445 static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = { 1446 .atomic_disable = dpu_crtc_disable, 1447 .atomic_enable = dpu_crtc_enable, 1448 .atomic_check = dpu_crtc_atomic_check, 1449 .atomic_begin = dpu_crtc_atomic_begin, 1450 .atomic_flush = dpu_crtc_atomic_flush, 1451 .get_scanout_position = dpu_crtc_get_scanout_position, 1452 }; 1453 1454 /* initialize crtc */ 1455 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, 1456 struct drm_plane *cursor) 1457 { 1458 struct drm_crtc *crtc = NULL; 1459 struct dpu_crtc *dpu_crtc = NULL; 1460 int i, ret; 1461 1462 dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL); 1463 if (!dpu_crtc) 1464 return ERR_PTR(-ENOMEM); 1465 1466 crtc = &dpu_crtc->base; 1467 crtc->dev = dev; 1468 1469 spin_lock_init(&dpu_crtc->spin_lock); 1470 atomic_set(&dpu_crtc->frame_pending, 0); 1471 1472 init_completion(&dpu_crtc->frame_done_comp); 1473 1474 INIT_LIST_HEAD(&dpu_crtc->frame_event_list); 1475 1476 for (i = 0; i < ARRAY_SIZE(dpu_crtc->frame_events); i++) { 1477 INIT_LIST_HEAD(&dpu_crtc->frame_events[i].list); 1478 list_add(&dpu_crtc->frame_events[i].list, 1479 &dpu_crtc->frame_event_list); 1480 kthread_init_work(&dpu_crtc->frame_events[i].work, 1481 dpu_crtc_frame_event_work); 1482 } 1483 1484 drm_crtc_init_with_planes(dev, crtc, plane, cursor, &dpu_crtc_funcs, 1485 NULL); 1486 1487 drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs); 1488 1489 drm_crtc_enable_color_mgmt(crtc, 0, true, 0); 1490 1491 /* save user friendly CRTC name for later */ 1492 snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id); 1493 1494 /* initialize event handling */ 1495 spin_lock_init(&dpu_crtc->event_lock); 1496 1497 ret = drm_self_refresh_helper_init(crtc); 1498 if (ret) { 1499 DPU_ERROR("Failed to initialize %s with self-refresh helpers %d\n", 1500 crtc->name, ret); 1501 return ERR_PTR(ret); 1502 } 1503 1504 DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc->name); 1505 return crtc; 1506 } 1507