1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
4  * Copyright (C) 2013 Red Hat
5  * Author: Rob Clark <robdclark@gmail.com>
6  */
7 
8 #define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
9 #include <linux/sort.h>
10 #include <linux/debugfs.h>
11 #include <linux/ktime.h>
12 #include <linux/bits.h>
13 
14 #include <drm/drm_atomic.h>
15 #include <drm/drm_crtc.h>
16 #include <drm/drm_flip_work.h>
17 #include <drm/drm_mode.h>
18 #include <drm/drm_probe_helper.h>
19 #include <drm/drm_rect.h>
20 #include <drm/drm_vblank.h>
21 
22 #include "dpu_kms.h"
23 #include "dpu_hw_lm.h"
24 #include "dpu_hw_ctl.h"
25 #include "dpu_hw_dspp.h"
26 #include "dpu_crtc.h"
27 #include "dpu_plane.h"
28 #include "dpu_encoder.h"
29 #include "dpu_vbif.h"
30 #include "dpu_core_perf.h"
31 #include "dpu_trace.h"
32 
33 /* layer mixer index on dpu_crtc */
34 #define LEFT_MIXER 0
35 #define RIGHT_MIXER 1
36 
37 /* timeout in ms waiting for frame done */
38 #define DPU_CRTC_FRAME_DONE_TIMEOUT_MS	60
39 
40 #define	CONVERT_S3_15(val) \
41 	(((((u64)val) & ~BIT_ULL(63)) >> 17) & GENMASK_ULL(17, 0))
42 
43 static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
44 {
45 	struct msm_drm_private *priv = crtc->dev->dev_private;
46 
47 	return to_dpu_kms(priv->kms);
48 }
49 
50 static void dpu_crtc_destroy(struct drm_crtc *crtc)
51 {
52 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
53 
54 	if (!crtc)
55 		return;
56 
57 	drm_crtc_cleanup(crtc);
58 	kfree(dpu_crtc);
59 }
60 
61 static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc)
62 {
63 	struct drm_device *dev = crtc->dev;
64 	struct drm_encoder *encoder;
65 
66 	drm_for_each_encoder(encoder, dev)
67 		if (encoder->crtc == crtc)
68 			return encoder;
69 
70 	return NULL;
71 }
72 
73 static enum dpu_crtc_crc_source dpu_crtc_parse_crc_source(const char *src_name)
74 {
75 	if (!src_name ||
76 	    !strcmp(src_name, "none"))
77 		return DPU_CRTC_CRC_SOURCE_NONE;
78 	if (!strcmp(src_name, "auto") ||
79 	    !strcmp(src_name, "lm"))
80 		return DPU_CRTC_CRC_SOURCE_LAYER_MIXER;
81 
82 	return DPU_CRTC_CRC_SOURCE_INVALID;
83 }
84 
85 static int dpu_crtc_verify_crc_source(struct drm_crtc *crtc,
86 		const char *src_name, size_t *values_cnt)
87 {
88 	enum dpu_crtc_crc_source source = dpu_crtc_parse_crc_source(src_name);
89 	struct dpu_crtc_state *crtc_state = to_dpu_crtc_state(crtc->state);
90 
91 	if (source < 0) {
92 		DRM_DEBUG_DRIVER("Invalid source %s for CRTC%d\n", src_name, crtc->index);
93 		return -EINVAL;
94 	}
95 
96 	if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER)
97 		*values_cnt = crtc_state->num_mixers;
98 
99 	return 0;
100 }
101 
102 static int dpu_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
103 {
104 	enum dpu_crtc_crc_source source = dpu_crtc_parse_crc_source(src_name);
105 	enum dpu_crtc_crc_source current_source;
106 	struct dpu_crtc_state *crtc_state;
107 	struct drm_device *drm_dev = crtc->dev;
108 	struct dpu_crtc_mixer *m;
109 
110 	bool was_enabled;
111 	bool enable = false;
112 	int i, ret = 0;
113 
114 	if (source < 0) {
115 		DRM_DEBUG_DRIVER("Invalid CRC source %s for CRTC%d\n", src_name, crtc->index);
116 		return -EINVAL;
117 	}
118 
119 	ret = drm_modeset_lock(&crtc->mutex, NULL);
120 
121 	if (ret)
122 		return ret;
123 
124 	enable = (source != DPU_CRTC_CRC_SOURCE_NONE);
125 	crtc_state = to_dpu_crtc_state(crtc->state);
126 
127 	spin_lock_irq(&drm_dev->event_lock);
128 	current_source = crtc_state->crc_source;
129 	spin_unlock_irq(&drm_dev->event_lock);
130 
131 	was_enabled = (current_source != DPU_CRTC_CRC_SOURCE_NONE);
132 
133 	if (!was_enabled && enable) {
134 		ret = drm_crtc_vblank_get(crtc);
135 
136 		if (ret)
137 			goto cleanup;
138 
139 	} else if (was_enabled && !enable) {
140 		drm_crtc_vblank_put(crtc);
141 	}
142 
143 	spin_lock_irq(&drm_dev->event_lock);
144 	crtc_state->crc_source = source;
145 	spin_unlock_irq(&drm_dev->event_lock);
146 
147 	crtc_state->crc_frame_skip_count = 0;
148 
149 	for (i = 0; i < crtc_state->num_mixers; ++i) {
150 		m = &crtc_state->mixers[i];
151 
152 		if (!m->hw_lm || !m->hw_lm->ops.setup_misr)
153 			continue;
154 
155 		/* Calculate MISR over 1 frame */
156 		m->hw_lm->ops.setup_misr(m->hw_lm, true, 1);
157 	}
158 
159 
160 cleanup:
161 	drm_modeset_unlock(&crtc->mutex);
162 
163 	return ret;
164 }
165 
166 static u32 dpu_crtc_get_vblank_counter(struct drm_crtc *crtc)
167 {
168 	struct drm_encoder *encoder = get_encoder_from_crtc(crtc);
169 	if (!encoder) {
170 		DRM_ERROR("no encoder found for crtc %d\n", crtc->index);
171 		return 0;
172 	}
173 
174 	return dpu_encoder_get_vsync_count(encoder);
175 }
176 
177 
178 static int dpu_crtc_get_crc(struct drm_crtc *crtc)
179 {
180 	struct dpu_crtc_state *crtc_state;
181 	struct dpu_crtc_mixer *m;
182 	u32 crcs[CRTC_DUAL_MIXERS];
183 
184 	int i = 0;
185 	int rc = 0;
186 
187 	crtc_state = to_dpu_crtc_state(crtc->state);
188 
189 	BUILD_BUG_ON(ARRAY_SIZE(crcs) != ARRAY_SIZE(crtc_state->mixers));
190 
191 	/* Skip first 2 frames in case of "uncooked" CRCs */
192 	if (crtc_state->crc_frame_skip_count < 2) {
193 		crtc_state->crc_frame_skip_count++;
194 		return 0;
195 	}
196 
197 	for (i = 0; i < crtc_state->num_mixers; ++i) {
198 
199 		m = &crtc_state->mixers[i];
200 
201 		if (!m->hw_lm || !m->hw_lm->ops.collect_misr)
202 			continue;
203 
204 		rc = m->hw_lm->ops.collect_misr(m->hw_lm, &crcs[i]);
205 
206 		if (rc) {
207 			DRM_DEBUG_DRIVER("MISR read failed\n");
208 			return rc;
209 		}
210 	}
211 
212 	return drm_crtc_add_crc_entry(crtc, true,
213 			drm_crtc_accurate_vblank_count(crtc), crcs);
214 }
215 
216 static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc,
217 					   bool in_vblank_irq,
218 					   int *vpos, int *hpos,
219 					   ktime_t *stime, ktime_t *etime,
220 					   const struct drm_display_mode *mode)
221 {
222 	unsigned int pipe = crtc->index;
223 	struct drm_encoder *encoder;
224 	int line, vsw, vbp, vactive_start, vactive_end, vfp_end;
225 
226 	encoder = get_encoder_from_crtc(crtc);
227 	if (!encoder) {
228 		DRM_ERROR("no encoder found for crtc %d\n", pipe);
229 		return false;
230 	}
231 
232 	vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
233 	vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
234 
235 	/*
236 	 * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at
237 	 * the end of VFP. Translate the porch values relative to the line
238 	 * counter positions.
239 	 */
240 
241 	vactive_start = vsw + vbp + 1;
242 	vactive_end = vactive_start + mode->crtc_vdisplay;
243 
244 	/* last scan line before VSYNC */
245 	vfp_end = mode->crtc_vtotal;
246 
247 	if (stime)
248 		*stime = ktime_get();
249 
250 	line = dpu_encoder_get_linecount(encoder);
251 
252 	if (line < vactive_start)
253 		line -= vactive_start;
254 	else if (line > vactive_end)
255 		line = line - vfp_end - vactive_start;
256 	else
257 		line -= vactive_start;
258 
259 	*vpos = line;
260 	*hpos = 0;
261 
262 	if (etime)
263 		*etime = ktime_get();
264 
265 	return true;
266 }
267 
268 static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
269 		struct dpu_plane_state *pstate, struct dpu_format *format)
270 {
271 	struct dpu_hw_mixer *lm = mixer->hw_lm;
272 	uint32_t blend_op;
273 	uint32_t fg_alpha, bg_alpha;
274 
275 	fg_alpha = pstate->base.alpha >> 8;
276 	bg_alpha = 0xff - fg_alpha;
277 
278 	/* default to opaque blending */
279 	if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
280 	    !format->alpha_enable) {
281 		blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
282 			DPU_BLEND_BG_ALPHA_BG_CONST;
283 	} else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
284 		blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
285 			DPU_BLEND_BG_ALPHA_FG_PIXEL;
286 		if (fg_alpha != 0xff) {
287 			bg_alpha = fg_alpha;
288 			blend_op |= DPU_BLEND_BG_MOD_ALPHA |
289 				    DPU_BLEND_BG_INV_MOD_ALPHA;
290 		} else {
291 			blend_op |= DPU_BLEND_BG_INV_ALPHA;
292 		}
293 	} else {
294 		/* coverage blending */
295 		blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL |
296 			DPU_BLEND_BG_ALPHA_FG_PIXEL;
297 		if (fg_alpha != 0xff) {
298 			bg_alpha = fg_alpha;
299 			blend_op |= DPU_BLEND_FG_MOD_ALPHA |
300 				    DPU_BLEND_FG_INV_MOD_ALPHA |
301 				    DPU_BLEND_BG_MOD_ALPHA |
302 				    DPU_BLEND_BG_INV_MOD_ALPHA;
303 		} else {
304 			blend_op |= DPU_BLEND_BG_INV_ALPHA;
305 		}
306 	}
307 
308 	lm->ops.setup_blend_config(lm, pstate->stage,
309 				fg_alpha, bg_alpha, blend_op);
310 
311 	DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
312 		  &format->base.pixel_format, format->alpha_enable, blend_op);
313 }
314 
315 static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
316 {
317 	struct dpu_crtc_state *crtc_state;
318 	int lm_idx, lm_horiz_position;
319 
320 	crtc_state = to_dpu_crtc_state(crtc->state);
321 
322 	lm_horiz_position = 0;
323 	for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) {
324 		const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx];
325 		struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm;
326 		struct dpu_hw_mixer_cfg cfg;
327 
328 		if (!lm_roi || !drm_rect_visible(lm_roi))
329 			continue;
330 
331 		cfg.out_width = drm_rect_width(lm_roi);
332 		cfg.out_height = drm_rect_height(lm_roi);
333 		cfg.right_mixer = lm_horiz_position++;
334 		cfg.flags = 0;
335 		hw_lm->ops.setup_mixer_out(hw_lm, &cfg);
336 	}
337 }
338 
339 static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
340 	struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer,
341 	struct dpu_hw_stage_cfg *stage_cfg)
342 {
343 	struct drm_plane *plane;
344 	struct drm_framebuffer *fb;
345 	struct drm_plane_state *state;
346 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
347 	struct dpu_plane_state *pstate = NULL;
348 	struct dpu_format *format;
349 	struct dpu_hw_ctl *ctl = mixer->lm_ctl;
350 
351 	u32 flush_mask;
352 	uint32_t stage_idx, lm_idx;
353 	int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 };
354 	bool bg_alpha_enable = false;
355 	DECLARE_BITMAP(fetch_active, SSPP_MAX);
356 
357 	memset(fetch_active, 0, sizeof(fetch_active));
358 	drm_atomic_crtc_for_each_plane(plane, crtc) {
359 		state = plane->state;
360 		if (!state)
361 			continue;
362 
363 		pstate = to_dpu_plane_state(state);
364 		fb = state->fb;
365 
366 		dpu_plane_get_ctl_flush(plane, ctl, &flush_mask);
367 		set_bit(dpu_plane_pipe(plane), fetch_active);
368 
369 		DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d\n",
370 				crtc->base.id,
371 				pstate->stage,
372 				plane->base.id,
373 				dpu_plane_pipe(plane) - SSPP_VIG0,
374 				state->fb ? state->fb->base.id : -1);
375 
376 		format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));
377 
378 		if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
379 			bg_alpha_enable = true;
380 
381 		stage_idx = zpos_cnt[pstate->stage]++;
382 		stage_cfg->stage[pstate->stage][stage_idx] =
383 					dpu_plane_pipe(plane);
384 		stage_cfg->multirect_index[pstate->stage][stage_idx] =
385 					pstate->multirect_index;
386 
387 		trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
388 					   state, pstate, stage_idx,
389 					   dpu_plane_pipe(plane) - SSPP_VIG0,
390 					   format->base.pixel_format,
391 					   fb ? fb->modifier : 0);
392 
393 		/* blend config update */
394 		for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
395 			_dpu_crtc_setup_blend_cfg(mixer + lm_idx,
396 						pstate, format);
397 
398 			mixer[lm_idx].flush_mask |= flush_mask;
399 
400 			if (bg_alpha_enable && !format->alpha_enable)
401 				mixer[lm_idx].mixer_op_mode = 0;
402 			else
403 				mixer[lm_idx].mixer_op_mode |=
404 						1 << pstate->stage;
405 		}
406 	}
407 
408 	if (ctl->ops.set_active_pipes)
409 		ctl->ops.set_active_pipes(ctl, fetch_active);
410 
411 	_dpu_crtc_program_lm_output_roi(crtc);
412 }
413 
414 /**
415  * _dpu_crtc_blend_setup - configure crtc mixers
416  * @crtc: Pointer to drm crtc structure
417  */
418 static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
419 {
420 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
421 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
422 	struct dpu_crtc_mixer *mixer = cstate->mixers;
423 	struct dpu_hw_ctl *ctl;
424 	struct dpu_hw_mixer *lm;
425 	struct dpu_hw_stage_cfg stage_cfg;
426 	int i;
427 
428 	DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name);
429 
430 	for (i = 0; i < cstate->num_mixers; i++) {
431 		mixer[i].mixer_op_mode = 0;
432 		mixer[i].flush_mask = 0;
433 		if (mixer[i].lm_ctl->ops.clear_all_blendstages)
434 			mixer[i].lm_ctl->ops.clear_all_blendstages(
435 					mixer[i].lm_ctl);
436 	}
437 
438 	/* initialize stage cfg */
439 	memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg));
440 
441 	_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg);
442 
443 	for (i = 0; i < cstate->num_mixers; i++) {
444 		ctl = mixer[i].lm_ctl;
445 		lm = mixer[i].hw_lm;
446 
447 		lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
448 
449 		mixer[i].flush_mask |= ctl->ops.get_bitmask_mixer(ctl,
450 			mixer[i].hw_lm->idx);
451 
452 		/* stage config flush mask */
453 		ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask);
454 
455 		DRM_DEBUG_ATOMIC("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n",
456 			mixer[i].hw_lm->idx - LM_0,
457 			mixer[i].mixer_op_mode,
458 			ctl->idx - CTL_0,
459 			mixer[i].flush_mask);
460 
461 		ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
462 			&stage_cfg);
463 	}
464 }
465 
466 /**
467  *  _dpu_crtc_complete_flip - signal pending page_flip events
468  * Any pending vblank events are added to the vblank_event_list
469  * so that the next vblank interrupt shall signal them.
470  * However PAGE_FLIP events are not handled through the vblank_event_list.
471  * This API signals any pending PAGE_FLIP events requested through
472  * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the dpu_crtc->event.
473  * @crtc: Pointer to drm crtc structure
474  */
475 static void _dpu_crtc_complete_flip(struct drm_crtc *crtc)
476 {
477 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
478 	struct drm_device *dev = crtc->dev;
479 	unsigned long flags;
480 
481 	spin_lock_irqsave(&dev->event_lock, flags);
482 	if (dpu_crtc->event) {
483 		DRM_DEBUG_VBL("%s: send event: %pK\n", dpu_crtc->name,
484 			      dpu_crtc->event);
485 		trace_dpu_crtc_complete_flip(DRMID(crtc));
486 		drm_crtc_send_vblank_event(crtc, dpu_crtc->event);
487 		dpu_crtc->event = NULL;
488 	}
489 	spin_unlock_irqrestore(&dev->event_lock, flags);
490 }
491 
492 enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc)
493 {
494 	struct drm_encoder *encoder;
495 
496 	/*
497 	 * TODO: This function is called from dpu debugfs and as part of atomic
498 	 * check. When called from debugfs, the crtc->mutex must be held to
499 	 * read crtc->state. However reading crtc->state from atomic check isn't
500 	 * allowed (unless you have a good reason, a big comment, and a deep
501 	 * understanding of how the atomic/modeset locks work (<- and this is
502 	 * probably not possible)). So we'll keep the WARN_ON here for now, but
503 	 * really we need to figure out a better way to track our operating mode
504 	 */
505 	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
506 
507 	/* TODO: Returns the first INTF_MODE, could there be multiple values? */
508 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
509 		return dpu_encoder_get_intf_mode(encoder);
510 
511 	return INTF_MODE_NONE;
512 }
513 
514 void dpu_crtc_vblank_callback(struct drm_crtc *crtc)
515 {
516 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
517 
518 	/* keep statistics on vblank callback - with auto reset via debugfs */
519 	if (ktime_compare(dpu_crtc->vblank_cb_time, ktime_set(0, 0)) == 0)
520 		dpu_crtc->vblank_cb_time = ktime_get();
521 	else
522 		dpu_crtc->vblank_cb_count++;
523 
524 	dpu_crtc_get_crc(crtc);
525 
526 	drm_crtc_handle_vblank(crtc);
527 	trace_dpu_crtc_vblank_cb(DRMID(crtc));
528 }
529 
530 static void dpu_crtc_frame_event_work(struct kthread_work *work)
531 {
532 	struct dpu_crtc_frame_event *fevent = container_of(work,
533 			struct dpu_crtc_frame_event, work);
534 	struct drm_crtc *crtc = fevent->crtc;
535 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
536 	unsigned long flags;
537 	bool frame_done = false;
538 
539 	DPU_ATRACE_BEGIN("crtc_frame_event");
540 
541 	DRM_DEBUG_ATOMIC("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
542 			ktime_to_ns(fevent->ts));
543 
544 	if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE
545 				| DPU_ENCODER_FRAME_EVENT_ERROR
546 				| DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
547 
548 		if (atomic_read(&dpu_crtc->frame_pending) < 1) {
549 			/* ignore vblank when not pending */
550 		} else if (atomic_dec_return(&dpu_crtc->frame_pending) == 0) {
551 			/* release bandwidth and other resources */
552 			trace_dpu_crtc_frame_event_done(DRMID(crtc),
553 							fevent->event);
554 			dpu_core_perf_crtc_release_bw(crtc);
555 		} else {
556 			trace_dpu_crtc_frame_event_more_pending(DRMID(crtc),
557 								fevent->event);
558 		}
559 
560 		if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE
561 					| DPU_ENCODER_FRAME_EVENT_ERROR))
562 			frame_done = true;
563 	}
564 
565 	if (fevent->event & DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)
566 		DPU_ERROR("crtc%d ts:%lld received panel dead event\n",
567 				crtc->base.id, ktime_to_ns(fevent->ts));
568 
569 	if (frame_done)
570 		complete_all(&dpu_crtc->frame_done_comp);
571 
572 	spin_lock_irqsave(&dpu_crtc->spin_lock, flags);
573 	list_add_tail(&fevent->list, &dpu_crtc->frame_event_list);
574 	spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
575 	DPU_ATRACE_END("crtc_frame_event");
576 }
577 
578 /*
579  * dpu_crtc_frame_event_cb - crtc frame event callback API. CRTC module
580  * registers this API to encoder for all frame event callbacks like
581  * frame_error, frame_done, idle_timeout, etc. Encoder may call different events
582  * from different context - IRQ, user thread, commit_thread, etc. Each event
583  * should be carefully reviewed and should be processed in proper task context
584  * to avoid schedulin delay or properly manage the irq context's bottom half
585  * processing.
586  */
587 static void dpu_crtc_frame_event_cb(void *data, u32 event)
588 {
589 	struct drm_crtc *crtc = (struct drm_crtc *)data;
590 	struct dpu_crtc *dpu_crtc;
591 	struct msm_drm_private *priv;
592 	struct dpu_crtc_frame_event *fevent;
593 	unsigned long flags;
594 	u32 crtc_id;
595 
596 	/* Nothing to do on idle event */
597 	if (event & DPU_ENCODER_FRAME_EVENT_IDLE)
598 		return;
599 
600 	dpu_crtc = to_dpu_crtc(crtc);
601 	priv = crtc->dev->dev_private;
602 	crtc_id = drm_crtc_index(crtc);
603 
604 	trace_dpu_crtc_frame_event_cb(DRMID(crtc), event);
605 
606 	spin_lock_irqsave(&dpu_crtc->spin_lock, flags);
607 	fevent = list_first_entry_or_null(&dpu_crtc->frame_event_list,
608 			struct dpu_crtc_frame_event, list);
609 	if (fevent)
610 		list_del_init(&fevent->list);
611 	spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
612 
613 	if (!fevent) {
614 		DRM_ERROR_RATELIMITED("crtc%d event %d overflow\n", crtc->base.id, event);
615 		return;
616 	}
617 
618 	fevent->event = event;
619 	fevent->crtc = crtc;
620 	fevent->ts = ktime_get();
621 	kthread_queue_work(priv->event_thread[crtc_id].worker, &fevent->work);
622 }
623 
624 void dpu_crtc_complete_commit(struct drm_crtc *crtc)
625 {
626 	trace_dpu_crtc_complete_commit(DRMID(crtc));
627 	dpu_core_perf_crtc_update(crtc, 0, false);
628 	_dpu_crtc_complete_flip(crtc);
629 }
630 
631 static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
632 		struct drm_crtc_state *state)
633 {
634 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
635 	struct drm_display_mode *adj_mode = &state->adjusted_mode;
636 	u32 crtc_split_width = adj_mode->hdisplay / cstate->num_mixers;
637 	int i;
638 
639 	for (i = 0; i < cstate->num_mixers; i++) {
640 		struct drm_rect *r = &cstate->lm_bounds[i];
641 		r->x1 = crtc_split_width * i;
642 		r->y1 = 0;
643 		r->x2 = r->x1 + crtc_split_width;
644 		r->y2 = adj_mode->vdisplay;
645 
646 		trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i, r);
647 	}
648 }
649 
650 static void _dpu_crtc_get_pcc_coeff(struct drm_crtc_state *state,
651 		struct dpu_hw_pcc_cfg *cfg)
652 {
653 	struct drm_color_ctm *ctm;
654 
655 	memset(cfg, 0, sizeof(struct dpu_hw_pcc_cfg));
656 
657 	ctm = (struct drm_color_ctm *)state->ctm->data;
658 
659 	if (!ctm)
660 		return;
661 
662 	cfg->r.r = CONVERT_S3_15(ctm->matrix[0]);
663 	cfg->g.r = CONVERT_S3_15(ctm->matrix[1]);
664 	cfg->b.r = CONVERT_S3_15(ctm->matrix[2]);
665 
666 	cfg->r.g = CONVERT_S3_15(ctm->matrix[3]);
667 	cfg->g.g = CONVERT_S3_15(ctm->matrix[4]);
668 	cfg->b.g = CONVERT_S3_15(ctm->matrix[5]);
669 
670 	cfg->r.b = CONVERT_S3_15(ctm->matrix[6]);
671 	cfg->g.b = CONVERT_S3_15(ctm->matrix[7]);
672 	cfg->b.b = CONVERT_S3_15(ctm->matrix[8]);
673 }
674 
675 static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc)
676 {
677 	struct drm_crtc_state *state = crtc->state;
678 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
679 	struct dpu_crtc_mixer *mixer = cstate->mixers;
680 	struct dpu_hw_pcc_cfg cfg;
681 	struct dpu_hw_ctl *ctl;
682 	struct dpu_hw_dspp *dspp;
683 	int i;
684 
685 
686 	if (!state->color_mgmt_changed)
687 		return;
688 
689 	for (i = 0; i < cstate->num_mixers; i++) {
690 		ctl = mixer[i].lm_ctl;
691 		dspp = mixer[i].hw_dspp;
692 
693 		if (!dspp || !dspp->ops.setup_pcc)
694 			continue;
695 
696 		if (!state->ctm) {
697 			dspp->ops.setup_pcc(dspp, NULL);
698 		} else {
699 			_dpu_crtc_get_pcc_coeff(state, &cfg);
700 			dspp->ops.setup_pcc(dspp, &cfg);
701 		}
702 
703 		mixer[i].flush_mask |= ctl->ops.get_bitmask_dspp(ctl,
704 			mixer[i].hw_dspp->idx);
705 
706 		/* stage config flush mask */
707 		ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask);
708 
709 		DRM_DEBUG_ATOMIC("lm %d, ctl %d, flush mask 0x%x\n",
710 			mixer[i].hw_lm->idx - DSPP_0,
711 			ctl->idx - CTL_0,
712 			mixer[i].flush_mask);
713 	}
714 }
715 
716 static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
717 		struct drm_atomic_state *state)
718 {
719 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
720 	struct drm_encoder *encoder;
721 
722 	if (!crtc->state->enable) {
723 		DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_begin\n",
724 				crtc->base.id, crtc->state->enable);
725 		return;
726 	}
727 
728 	DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
729 
730 	_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
731 
732 	/* encoder will trigger pending mask now */
733 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
734 		dpu_encoder_trigger_kickoff_pending(encoder);
735 
736 	/*
737 	 * If no mixers have been allocated in dpu_crtc_atomic_check(),
738 	 * it means we are trying to flush a CRTC whose state is disabled:
739 	 * nothing else needs to be done.
740 	 */
741 	if (unlikely(!cstate->num_mixers))
742 		return;
743 
744 	_dpu_crtc_blend_setup(crtc);
745 
746 	_dpu_crtc_setup_cp_blocks(crtc);
747 
748 	/*
749 	 * PP_DONE irq is only used by command mode for now.
750 	 * It is better to request pending before FLUSH and START trigger
751 	 * to make sure no pp_done irq missed.
752 	 * This is safe because no pp_done will happen before SW trigger
753 	 * in command mode.
754 	 */
755 }
756 
757 static void dpu_crtc_atomic_flush(struct drm_crtc *crtc,
758 		struct drm_atomic_state *state)
759 {
760 	struct dpu_crtc *dpu_crtc;
761 	struct drm_device *dev;
762 	struct drm_plane *plane;
763 	struct msm_drm_private *priv;
764 	unsigned long flags;
765 	struct dpu_crtc_state *cstate;
766 
767 	if (!crtc->state->enable) {
768 		DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_flush\n",
769 				crtc->base.id, crtc->state->enable);
770 		return;
771 	}
772 
773 	DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
774 
775 	dpu_crtc = to_dpu_crtc(crtc);
776 	cstate = to_dpu_crtc_state(crtc->state);
777 	dev = crtc->dev;
778 	priv = dev->dev_private;
779 
780 	if (crtc->index >= ARRAY_SIZE(priv->event_thread)) {
781 		DPU_ERROR("invalid crtc index[%d]\n", crtc->index);
782 		return;
783 	}
784 
785 	WARN_ON(dpu_crtc->event);
786 	spin_lock_irqsave(&dev->event_lock, flags);
787 	dpu_crtc->event = crtc->state->event;
788 	crtc->state->event = NULL;
789 	spin_unlock_irqrestore(&dev->event_lock, flags);
790 
791 	/*
792 	 * If no mixers has been allocated in dpu_crtc_atomic_check(),
793 	 * it means we are trying to flush a CRTC whose state is disabled:
794 	 * nothing else needs to be done.
795 	 */
796 	if (unlikely(!cstate->num_mixers))
797 		return;
798 
799 	/* update performance setting before crtc kickoff */
800 	dpu_core_perf_crtc_update(crtc, 1, false);
801 
802 	/*
803 	 * Final plane updates: Give each plane a chance to complete all
804 	 *                      required writes/flushing before crtc's "flush
805 	 *                      everything" call below.
806 	 */
807 	drm_atomic_crtc_for_each_plane(plane, crtc) {
808 		if (dpu_crtc->smmu_state.transition_error)
809 			dpu_plane_set_error(plane, true);
810 		dpu_plane_flush(plane);
811 	}
812 
813 	/* Kickoff will be scheduled by outer layer */
814 }
815 
816 /**
817  * dpu_crtc_destroy_state - state destroy hook
818  * @crtc: drm CRTC
819  * @state: CRTC state object to release
820  */
821 static void dpu_crtc_destroy_state(struct drm_crtc *crtc,
822 		struct drm_crtc_state *state)
823 {
824 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
825 
826 	DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
827 
828 	__drm_atomic_helper_crtc_destroy_state(state);
829 
830 	kfree(cstate);
831 }
832 
833 static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc)
834 {
835 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
836 	int ret, rc = 0;
837 
838 	if (!atomic_read(&dpu_crtc->frame_pending)) {
839 		DRM_DEBUG_ATOMIC("no frames pending\n");
840 		return 0;
841 	}
842 
843 	DPU_ATRACE_BEGIN("frame done completion wait");
844 	ret = wait_for_completion_timeout(&dpu_crtc->frame_done_comp,
845 			msecs_to_jiffies(DPU_CRTC_FRAME_DONE_TIMEOUT_MS));
846 	if (!ret) {
847 		DRM_ERROR("frame done wait timed out, ret:%d\n", ret);
848 		rc = -ETIMEDOUT;
849 	}
850 	DPU_ATRACE_END("frame done completion wait");
851 
852 	return rc;
853 }
854 
855 void dpu_crtc_commit_kickoff(struct drm_crtc *crtc)
856 {
857 	struct drm_encoder *encoder;
858 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
859 	struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
860 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
861 
862 	/*
863 	 * If no mixers has been allocated in dpu_crtc_atomic_check(),
864 	 * it means we are trying to start a CRTC whose state is disabled:
865 	 * nothing else needs to be done.
866 	 */
867 	if (unlikely(!cstate->num_mixers))
868 		return;
869 
870 	DPU_ATRACE_BEGIN("crtc_commit");
871 
872 	/*
873 	 * Encoder will flush/start now, unless it has a tx pending. If so, it
874 	 * may delay and flush at an irq event (e.g. ppdone)
875 	 */
876 	drm_for_each_encoder_mask(encoder, crtc->dev,
877 				  crtc->state->encoder_mask)
878 		dpu_encoder_prepare_for_kickoff(encoder);
879 
880 	if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) {
881 		/* acquire bandwidth and other resources */
882 		DRM_DEBUG_ATOMIC("crtc%d first commit\n", crtc->base.id);
883 	} else
884 		DRM_DEBUG_ATOMIC("crtc%d commit\n", crtc->base.id);
885 
886 	dpu_crtc->play_count++;
887 
888 	dpu_vbif_clear_errors(dpu_kms);
889 
890 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
891 		dpu_encoder_kickoff(encoder);
892 
893 	reinit_completion(&dpu_crtc->frame_done_comp);
894 	DPU_ATRACE_END("crtc_commit");
895 }
896 
897 static void dpu_crtc_reset(struct drm_crtc *crtc)
898 {
899 	struct dpu_crtc_state *cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
900 
901 	if (crtc->state)
902 		dpu_crtc_destroy_state(crtc, crtc->state);
903 
904 	__drm_atomic_helper_crtc_reset(crtc, &cstate->base);
905 }
906 
907 /**
908  * dpu_crtc_duplicate_state - state duplicate hook
909  * @crtc: Pointer to drm crtc structure
910  */
911 static struct drm_crtc_state *dpu_crtc_duplicate_state(struct drm_crtc *crtc)
912 {
913 	struct dpu_crtc_state *cstate, *old_cstate = to_dpu_crtc_state(crtc->state);
914 
915 	cstate = kmemdup(old_cstate, sizeof(*old_cstate), GFP_KERNEL);
916 	if (!cstate) {
917 		DPU_ERROR("failed to allocate state\n");
918 		return NULL;
919 	}
920 
921 	/* duplicate base helper */
922 	__drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base);
923 
924 	return &cstate->base;
925 }
926 
927 static void dpu_crtc_atomic_print_state(struct drm_printer *p,
928 					const struct drm_crtc_state *state)
929 {
930 	const struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
931 	int i;
932 
933 	for (i = 0; i < cstate->num_mixers; i++) {
934 		drm_printf(p, "\tlm[%d]=%d\n", i, cstate->mixers[i].hw_lm->idx - LM_0);
935 		drm_printf(p, "\tctl[%d]=%d\n", i, cstate->mixers[i].lm_ctl->idx - CTL_0);
936 		if (cstate->mixers[i].hw_dspp)
937 			drm_printf(p, "\tdspp[%d]=%d\n", i, cstate->mixers[i].hw_dspp->idx - DSPP_0);
938 	}
939 }
940 
941 static void dpu_crtc_disable(struct drm_crtc *crtc,
942 			     struct drm_atomic_state *state)
943 {
944 	struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
945 									      crtc);
946 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
947 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
948 	struct drm_encoder *encoder;
949 	unsigned long flags;
950 	bool release_bandwidth = false;
951 
952 	DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
953 
954 	/* Disable/save vblank irq handling */
955 	drm_crtc_vblank_off(crtc);
956 
957 	drm_for_each_encoder_mask(encoder, crtc->dev,
958 				  old_crtc_state->encoder_mask) {
959 		/* in video mode, we hold an extra bandwidth reference
960 		 * as we cannot drop bandwidth at frame-done if any
961 		 * crtc is being used in video mode.
962 		 */
963 		if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
964 			release_bandwidth = true;
965 		dpu_encoder_assign_crtc(encoder, NULL);
966 	}
967 
968 	/* wait for frame_event_done completion */
969 	if (_dpu_crtc_wait_for_frame_done(crtc))
970 		DPU_ERROR("crtc%d wait for frame done failed;frame_pending%d\n",
971 				crtc->base.id,
972 				atomic_read(&dpu_crtc->frame_pending));
973 
974 	trace_dpu_crtc_disable(DRMID(crtc), false, dpu_crtc);
975 	dpu_crtc->enabled = false;
976 
977 	if (atomic_read(&dpu_crtc->frame_pending)) {
978 		trace_dpu_crtc_disable_frame_pending(DRMID(crtc),
979 				     atomic_read(&dpu_crtc->frame_pending));
980 		if (release_bandwidth)
981 			dpu_core_perf_crtc_release_bw(crtc);
982 		atomic_set(&dpu_crtc->frame_pending, 0);
983 	}
984 
985 	dpu_core_perf_crtc_update(crtc, 0, true);
986 
987 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
988 		dpu_encoder_register_frame_event_callback(encoder, NULL, NULL);
989 
990 	memset(cstate->mixers, 0, sizeof(cstate->mixers));
991 	cstate->num_mixers = 0;
992 
993 	/* disable clk & bw control until clk & bw properties are set */
994 	cstate->bw_control = false;
995 	cstate->bw_split_vote = false;
996 
997 	if (crtc->state->event && !crtc->state->active) {
998 		spin_lock_irqsave(&crtc->dev->event_lock, flags);
999 		drm_crtc_send_vblank_event(crtc, crtc->state->event);
1000 		crtc->state->event = NULL;
1001 		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
1002 	}
1003 
1004 	pm_runtime_put_sync(crtc->dev->dev);
1005 }
1006 
1007 static void dpu_crtc_enable(struct drm_crtc *crtc,
1008 		struct drm_atomic_state *state)
1009 {
1010 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1011 	struct drm_encoder *encoder;
1012 	bool request_bandwidth = false;
1013 
1014 	pm_runtime_get_sync(crtc->dev->dev);
1015 
1016 	DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
1017 
1018 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) {
1019 		/* in video mode, we hold an extra bandwidth reference
1020 		 * as we cannot drop bandwidth at frame-done if any
1021 		 * crtc is being used in video mode.
1022 		 */
1023 		if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
1024 			request_bandwidth = true;
1025 		dpu_encoder_register_frame_event_callback(encoder,
1026 				dpu_crtc_frame_event_cb, (void *)crtc);
1027 	}
1028 
1029 	if (request_bandwidth)
1030 		atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref);
1031 
1032 	trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc);
1033 	dpu_crtc->enabled = true;
1034 
1035 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
1036 		dpu_encoder_assign_crtc(encoder, crtc);
1037 
1038 	/* Enable/restore vblank irq handling */
1039 	drm_crtc_vblank_on(crtc);
1040 }
1041 
1042 struct plane_state {
1043 	struct dpu_plane_state *dpu_pstate;
1044 	const struct drm_plane_state *drm_pstate;
1045 	int stage;
1046 	u32 pipe_id;
1047 };
1048 
1049 static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate)
1050 {
1051 	struct drm_crtc *crtc = cstate->crtc;
1052 	struct drm_encoder *encoder;
1053 
1054 	drm_for_each_encoder_mask (encoder, crtc->dev, cstate->encoder_mask) {
1055 		if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_CMD) {
1056 			return true;
1057 		}
1058 	}
1059 
1060 	return false;
1061 }
1062 
1063 static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
1064 		struct drm_atomic_state *state)
1065 {
1066 	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1067 									  crtc);
1068 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1069 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state);
1070 	struct plane_state *pstates;
1071 
1072 	const struct drm_plane_state *pstate;
1073 	struct drm_plane *plane;
1074 	struct drm_display_mode *mode;
1075 
1076 	int cnt = 0, rc = 0, mixer_width = 0, i, z_pos;
1077 
1078 	struct dpu_multirect_plane_states multirect_plane[DPU_STAGE_MAX * 2];
1079 	int multirect_count = 0;
1080 	const struct drm_plane_state *pipe_staged[SSPP_MAX];
1081 	int left_zpos_cnt = 0, right_zpos_cnt = 0;
1082 	struct drm_rect crtc_rect = { 0 };
1083 	bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state);
1084 
1085 	pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL);
1086 
1087 	if (!crtc_state->enable || !crtc_state->active) {
1088 		DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n",
1089 				crtc->base.id, crtc_state->enable,
1090 				crtc_state->active);
1091 		memset(&cstate->new_perf, 0, sizeof(cstate->new_perf));
1092 		goto end;
1093 	}
1094 
1095 	mode = &crtc_state->adjusted_mode;
1096 	DRM_DEBUG_ATOMIC("%s: check\n", dpu_crtc->name);
1097 
1098 	/* force a full mode set if active state changed */
1099 	if (crtc_state->active_changed)
1100 		crtc_state->mode_changed = true;
1101 
1102 	memset(pipe_staged, 0, sizeof(pipe_staged));
1103 
1104 	if (cstate->num_mixers) {
1105 		mixer_width = mode->hdisplay / cstate->num_mixers;
1106 
1107 		_dpu_crtc_setup_lm_bounds(crtc, crtc_state);
1108 	}
1109 
1110 	crtc_rect.x2 = mode->hdisplay;
1111 	crtc_rect.y2 = mode->vdisplay;
1112 
1113 	 /* get plane state for all drm planes associated with crtc state */
1114 	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
1115 		struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate);
1116 		struct drm_rect dst, clip = crtc_rect;
1117 
1118 		if (IS_ERR_OR_NULL(pstate)) {
1119 			rc = PTR_ERR(pstate);
1120 			DPU_ERROR("%s: failed to get plane%d state, %d\n",
1121 					dpu_crtc->name, plane->base.id, rc);
1122 			goto end;
1123 		}
1124 		if (cnt >= DPU_STAGE_MAX * 4)
1125 			continue;
1126 
1127 		pstates[cnt].dpu_pstate = dpu_pstate;
1128 		pstates[cnt].drm_pstate = pstate;
1129 		pstates[cnt].stage = pstate->normalized_zpos;
1130 		pstates[cnt].pipe_id = dpu_plane_pipe(plane);
1131 
1132 		dpu_pstate->needs_dirtyfb = needs_dirtyfb;
1133 
1134 		if (pipe_staged[pstates[cnt].pipe_id]) {
1135 			multirect_plane[multirect_count].r0 =
1136 				pipe_staged[pstates[cnt].pipe_id];
1137 			multirect_plane[multirect_count].r1 = pstate;
1138 			multirect_count++;
1139 
1140 			pipe_staged[pstates[cnt].pipe_id] = NULL;
1141 		} else {
1142 			pipe_staged[pstates[cnt].pipe_id] = pstate;
1143 		}
1144 
1145 		cnt++;
1146 
1147 		dst = drm_plane_state_dest(pstate);
1148 		if (!drm_rect_intersect(&clip, &dst)) {
1149 			DPU_ERROR("invalid vertical/horizontal destination\n");
1150 			DPU_ERROR("display: " DRM_RECT_FMT " plane: "
1151 				  DRM_RECT_FMT "\n", DRM_RECT_ARG(&crtc_rect),
1152 				  DRM_RECT_ARG(&dst));
1153 			rc = -E2BIG;
1154 			goto end;
1155 		}
1156 	}
1157 
1158 	for (i = 1; i < SSPP_MAX; i++) {
1159 		if (pipe_staged[i]) {
1160 			dpu_plane_clear_multirect(pipe_staged[i]);
1161 
1162 			if (is_dpu_plane_virtual(pipe_staged[i]->plane)) {
1163 				DPU_ERROR(
1164 					"r1 only virt plane:%d not supported\n",
1165 					pipe_staged[i]->plane->base.id);
1166 				rc  = -EINVAL;
1167 				goto end;
1168 			}
1169 		}
1170 	}
1171 
1172 	z_pos = -1;
1173 	for (i = 0; i < cnt; i++) {
1174 		/* reset counts at every new blend stage */
1175 		if (pstates[i].stage != z_pos) {
1176 			left_zpos_cnt = 0;
1177 			right_zpos_cnt = 0;
1178 			z_pos = pstates[i].stage;
1179 		}
1180 
1181 		/* verify z_pos setting before using it */
1182 		if (z_pos >= DPU_STAGE_MAX - DPU_STAGE_0) {
1183 			DPU_ERROR("> %d plane stages assigned\n",
1184 					DPU_STAGE_MAX - DPU_STAGE_0);
1185 			rc = -EINVAL;
1186 			goto end;
1187 		} else if (pstates[i].drm_pstate->crtc_x < mixer_width) {
1188 			if (left_zpos_cnt == 2) {
1189 				DPU_ERROR("> 2 planes @ stage %d on left\n",
1190 					z_pos);
1191 				rc = -EINVAL;
1192 				goto end;
1193 			}
1194 			left_zpos_cnt++;
1195 
1196 		} else {
1197 			if (right_zpos_cnt == 2) {
1198 				DPU_ERROR("> 2 planes @ stage %d on right\n",
1199 					z_pos);
1200 				rc = -EINVAL;
1201 				goto end;
1202 			}
1203 			right_zpos_cnt++;
1204 		}
1205 
1206 		pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0;
1207 		DRM_DEBUG_ATOMIC("%s: zpos %d\n", dpu_crtc->name, z_pos);
1208 	}
1209 
1210 	for (i = 0; i < multirect_count; i++) {
1211 		if (dpu_plane_validate_multirect_v2(&multirect_plane[i])) {
1212 			DPU_ERROR(
1213 			"multirect validation failed for planes (%d - %d)\n",
1214 					multirect_plane[i].r0->plane->base.id,
1215 					multirect_plane[i].r1->plane->base.id);
1216 			rc = -EINVAL;
1217 			goto end;
1218 		}
1219 	}
1220 
1221 	atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref);
1222 
1223 	rc = dpu_core_perf_crtc_check(crtc, crtc_state);
1224 	if (rc) {
1225 		DPU_ERROR("crtc%d failed performance check %d\n",
1226 				crtc->base.id, rc);
1227 		goto end;
1228 	}
1229 
1230 	/* validate source split:
1231 	 * use pstates sorted by stage to check planes on same stage
1232 	 * we assume that all pipes are in source split so its valid to compare
1233 	 * without taking into account left/right mixer placement
1234 	 */
1235 	for (i = 1; i < cnt; i++) {
1236 		struct plane_state *prv_pstate, *cur_pstate;
1237 		struct drm_rect left_rect, right_rect;
1238 		int32_t left_pid, right_pid;
1239 		int32_t stage;
1240 
1241 		prv_pstate = &pstates[i - 1];
1242 		cur_pstate = &pstates[i];
1243 		if (prv_pstate->stage != cur_pstate->stage)
1244 			continue;
1245 
1246 		stage = cur_pstate->stage;
1247 
1248 		left_pid = prv_pstate->dpu_pstate->base.plane->base.id;
1249 		left_rect = drm_plane_state_dest(prv_pstate->drm_pstate);
1250 
1251 		right_pid = cur_pstate->dpu_pstate->base.plane->base.id;
1252 		right_rect = drm_plane_state_dest(cur_pstate->drm_pstate);
1253 
1254 		if (right_rect.x1 < left_rect.x1) {
1255 			swap(left_pid, right_pid);
1256 			swap(left_rect, right_rect);
1257 		}
1258 
1259 		/**
1260 		 * - planes are enumerated in pipe-priority order such that
1261 		 *   planes with lower drm_id must be left-most in a shared
1262 		 *   blend-stage when using source split.
1263 		 * - planes in source split must be contiguous in width
1264 		 * - planes in source split must have same dest yoff and height
1265 		 */
1266 		if (right_pid < left_pid) {
1267 			DPU_ERROR(
1268 				"invalid src split cfg. priority mismatch. stage: %d left: %d right: %d\n",
1269 				stage, left_pid, right_pid);
1270 			rc = -EINVAL;
1271 			goto end;
1272 		} else if (right_rect.x1 != drm_rect_width(&left_rect)) {
1273 			DPU_ERROR("non-contiguous coordinates for src split. "
1274 				  "stage: %d left: " DRM_RECT_FMT " right: "
1275 				  DRM_RECT_FMT "\n", stage,
1276 				  DRM_RECT_ARG(&left_rect),
1277 				  DRM_RECT_ARG(&right_rect));
1278 			rc = -EINVAL;
1279 			goto end;
1280 		} else if (left_rect.y1 != right_rect.y1 ||
1281 			   drm_rect_height(&left_rect) != drm_rect_height(&right_rect)) {
1282 			DPU_ERROR("source split at stage: %d. invalid "
1283 				  "yoff/height: left: " DRM_RECT_FMT " right: "
1284 				  DRM_RECT_FMT "\n", stage,
1285 				  DRM_RECT_ARG(&left_rect),
1286 				  DRM_RECT_ARG(&right_rect));
1287 			rc = -EINVAL;
1288 			goto end;
1289 		}
1290 	}
1291 
1292 end:
1293 	kfree(pstates);
1294 	return rc;
1295 }
1296 
1297 int dpu_crtc_vblank(struct drm_crtc *crtc, bool en)
1298 {
1299 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1300 	struct drm_encoder *enc;
1301 
1302 	trace_dpu_crtc_vblank(DRMID(&dpu_crtc->base), en, dpu_crtc);
1303 
1304 	/*
1305 	 * Normally we would iterate through encoder_mask in crtc state to find
1306 	 * attached encoders. In this case, we might be disabling vblank _after_
1307 	 * encoder_mask has been cleared.
1308 	 *
1309 	 * Instead, we "assign" a crtc to the encoder in enable and clear it in
1310 	 * disable (which is also after encoder_mask is cleared). So instead of
1311 	 * using encoder mask, we'll ask the encoder to toggle itself iff it's
1312 	 * currently assigned to our crtc.
1313 	 *
1314 	 * Note also that this function cannot be called while crtc is disabled
1315 	 * since we use drm_crtc_vblank_on/off. So we don't need to worry
1316 	 * about the assigned crtcs being inconsistent with the current state
1317 	 * (which means no need to worry about modeset locks).
1318 	 */
1319 	list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) {
1320 		trace_dpu_crtc_vblank_enable(DRMID(crtc), DRMID(enc), en,
1321 					     dpu_crtc);
1322 
1323 		dpu_encoder_toggle_vblank_for_crtc(enc, crtc, en);
1324 	}
1325 
1326 	return 0;
1327 }
1328 
1329 #ifdef CONFIG_DEBUG_FS
1330 static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
1331 {
1332 	struct dpu_crtc *dpu_crtc;
1333 	struct dpu_plane_state *pstate = NULL;
1334 	struct dpu_crtc_mixer *m;
1335 
1336 	struct drm_crtc *crtc;
1337 	struct drm_plane *plane;
1338 	struct drm_display_mode *mode;
1339 	struct drm_framebuffer *fb;
1340 	struct drm_plane_state *state;
1341 	struct dpu_crtc_state *cstate;
1342 
1343 	int i, out_width;
1344 
1345 	dpu_crtc = s->private;
1346 	crtc = &dpu_crtc->base;
1347 
1348 	drm_modeset_lock_all(crtc->dev);
1349 	cstate = to_dpu_crtc_state(crtc->state);
1350 
1351 	mode = &crtc->state->adjusted_mode;
1352 	out_width = mode->hdisplay / cstate->num_mixers;
1353 
1354 	seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id,
1355 				mode->hdisplay, mode->vdisplay);
1356 
1357 	seq_puts(s, "\n");
1358 
1359 	for (i = 0; i < cstate->num_mixers; ++i) {
1360 		m = &cstate->mixers[i];
1361 		seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n",
1362 			m->hw_lm->idx - LM_0, m->lm_ctl->idx - CTL_0,
1363 			out_width, mode->vdisplay);
1364 	}
1365 
1366 	seq_puts(s, "\n");
1367 
1368 	drm_atomic_crtc_for_each_plane(plane, crtc) {
1369 		pstate = to_dpu_plane_state(plane->state);
1370 		state = plane->state;
1371 
1372 		if (!pstate || !state)
1373 			continue;
1374 
1375 		seq_printf(s, "\tplane:%u stage:%d\n", plane->base.id,
1376 			pstate->stage);
1377 
1378 		if (plane->state->fb) {
1379 			fb = plane->state->fb;
1380 
1381 			seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u ",
1382 				fb->base.id, (char *) &fb->format->format,
1383 				fb->width, fb->height);
1384 			for (i = 0; i < ARRAY_SIZE(fb->format->cpp); ++i)
1385 				seq_printf(s, "cpp[%d]:%u ",
1386 						i, fb->format->cpp[i]);
1387 			seq_puts(s, "\n\t");
1388 
1389 			seq_printf(s, "modifier:%8llu ", fb->modifier);
1390 			seq_puts(s, "\n");
1391 
1392 			seq_puts(s, "\t");
1393 			for (i = 0; i < ARRAY_SIZE(fb->pitches); i++)
1394 				seq_printf(s, "pitches[%d]:%8u ", i,
1395 							fb->pitches[i]);
1396 			seq_puts(s, "\n");
1397 
1398 			seq_puts(s, "\t");
1399 			for (i = 0; i < ARRAY_SIZE(fb->offsets); i++)
1400 				seq_printf(s, "offsets[%d]:%8u ", i,
1401 							fb->offsets[i]);
1402 			seq_puts(s, "\n");
1403 		}
1404 
1405 		seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n",
1406 			state->src_x, state->src_y, state->src_w, state->src_h);
1407 
1408 		seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
1409 			state->crtc_x, state->crtc_y, state->crtc_w,
1410 			state->crtc_h);
1411 		seq_printf(s, "\tmultirect: mode: %d index: %d\n",
1412 			pstate->multirect_mode, pstate->multirect_index);
1413 
1414 		seq_puts(s, "\n");
1415 	}
1416 	if (dpu_crtc->vblank_cb_count) {
1417 		ktime_t diff = ktime_sub(ktime_get(), dpu_crtc->vblank_cb_time);
1418 		s64 diff_ms = ktime_to_ms(diff);
1419 		s64 fps = diff_ms ? div_s64(
1420 				dpu_crtc->vblank_cb_count * 1000, diff_ms) : 0;
1421 
1422 		seq_printf(s,
1423 			"vblank fps:%lld count:%u total:%llums total_framecount:%llu\n",
1424 				fps, dpu_crtc->vblank_cb_count,
1425 				ktime_to_ms(diff), dpu_crtc->play_count);
1426 
1427 		/* reset time & count for next measurement */
1428 		dpu_crtc->vblank_cb_count = 0;
1429 		dpu_crtc->vblank_cb_time = ktime_set(0, 0);
1430 	}
1431 
1432 	drm_modeset_unlock_all(crtc->dev);
1433 
1434 	return 0;
1435 }
1436 
1437 DEFINE_SHOW_ATTRIBUTE(_dpu_debugfs_status);
1438 
1439 static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v)
1440 {
1441 	struct drm_crtc *crtc = (struct drm_crtc *) s->private;
1442 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1443 
1444 	seq_printf(s, "client type: %d\n", dpu_crtc_get_client_type(crtc));
1445 	seq_printf(s, "intf_mode: %d\n", dpu_crtc_get_intf_mode(crtc));
1446 	seq_printf(s, "core_clk_rate: %llu\n",
1447 			dpu_crtc->cur_perf.core_clk_rate);
1448 	seq_printf(s, "bw_ctl: %llu\n", dpu_crtc->cur_perf.bw_ctl);
1449 	seq_printf(s, "max_per_pipe_ib: %llu\n",
1450 				dpu_crtc->cur_perf.max_per_pipe_ib);
1451 
1452 	return 0;
1453 }
1454 DEFINE_SHOW_ATTRIBUTE(dpu_crtc_debugfs_state);
1455 
1456 static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc)
1457 {
1458 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1459 	struct dentry *debugfs_root;
1460 
1461 	debugfs_root = debugfs_create_dir(dpu_crtc->name,
1462 			crtc->dev->primary->debugfs_root);
1463 
1464 	debugfs_create_file("status", 0400,
1465 			debugfs_root,
1466 			dpu_crtc, &_dpu_debugfs_status_fops);
1467 	debugfs_create_file("state", 0600,
1468 			debugfs_root,
1469 			&dpu_crtc->base,
1470 			&dpu_crtc_debugfs_state_fops);
1471 
1472 	return 0;
1473 }
1474 #else
1475 static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc)
1476 {
1477 	return 0;
1478 }
1479 #endif /* CONFIG_DEBUG_FS */
1480 
1481 static int dpu_crtc_late_register(struct drm_crtc *crtc)
1482 {
1483 	return _dpu_crtc_init_debugfs(crtc);
1484 }
1485 
1486 static const struct drm_crtc_funcs dpu_crtc_funcs = {
1487 	.set_config = drm_atomic_helper_set_config,
1488 	.destroy = dpu_crtc_destroy,
1489 	.page_flip = drm_atomic_helper_page_flip,
1490 	.reset = dpu_crtc_reset,
1491 	.atomic_duplicate_state = dpu_crtc_duplicate_state,
1492 	.atomic_destroy_state = dpu_crtc_destroy_state,
1493 	.atomic_print_state = dpu_crtc_atomic_print_state,
1494 	.late_register = dpu_crtc_late_register,
1495 	.verify_crc_source = dpu_crtc_verify_crc_source,
1496 	.set_crc_source = dpu_crtc_set_crc_source,
1497 	.enable_vblank  = msm_crtc_enable_vblank,
1498 	.disable_vblank = msm_crtc_disable_vblank,
1499 	.get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1500 	.get_vblank_counter = dpu_crtc_get_vblank_counter,
1501 };
1502 
1503 static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = {
1504 	.atomic_disable = dpu_crtc_disable,
1505 	.atomic_enable = dpu_crtc_enable,
1506 	.atomic_check = dpu_crtc_atomic_check,
1507 	.atomic_begin = dpu_crtc_atomic_begin,
1508 	.atomic_flush = dpu_crtc_atomic_flush,
1509 	.get_scanout_position = dpu_crtc_get_scanout_position,
1510 };
1511 
1512 /* initialize crtc */
1513 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
1514 				struct drm_plane *cursor)
1515 {
1516 	struct drm_crtc *crtc = NULL;
1517 	struct dpu_crtc *dpu_crtc = NULL;
1518 	int i;
1519 
1520 	dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL);
1521 	if (!dpu_crtc)
1522 		return ERR_PTR(-ENOMEM);
1523 
1524 	crtc = &dpu_crtc->base;
1525 	crtc->dev = dev;
1526 
1527 	spin_lock_init(&dpu_crtc->spin_lock);
1528 	atomic_set(&dpu_crtc->frame_pending, 0);
1529 
1530 	init_completion(&dpu_crtc->frame_done_comp);
1531 
1532 	INIT_LIST_HEAD(&dpu_crtc->frame_event_list);
1533 
1534 	for (i = 0; i < ARRAY_SIZE(dpu_crtc->frame_events); i++) {
1535 		INIT_LIST_HEAD(&dpu_crtc->frame_events[i].list);
1536 		list_add(&dpu_crtc->frame_events[i].list,
1537 				&dpu_crtc->frame_event_list);
1538 		kthread_init_work(&dpu_crtc->frame_events[i].work,
1539 				dpu_crtc_frame_event_work);
1540 	}
1541 
1542 	drm_crtc_init_with_planes(dev, crtc, plane, cursor, &dpu_crtc_funcs,
1543 				NULL);
1544 
1545 	drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
1546 
1547 	drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
1548 
1549 	/* save user friendly CRTC name for later */
1550 	snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
1551 
1552 	/* initialize event handling */
1553 	spin_lock_init(&dpu_crtc->event_lock);
1554 
1555 	DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc->name);
1556 	return crtc;
1557 }
1558