1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2014-2018 The Linux Foundation. All rights reserved.
4  * Copyright (C) 2013 Red Hat
5  * Author: Rob Clark <robdclark@gmail.com>
6  */
7 
8 #define pr_fmt(fmt)	"[drm:%s:%d] " fmt, __func__, __LINE__
9 #include <linux/sort.h>
10 #include <linux/debugfs.h>
11 #include <linux/ktime.h>
12 #include <drm/drm_crtc.h>
13 #include <drm/drm_flip_work.h>
14 #include <drm/drm_mode.h>
15 #include <drm/drm_probe_helper.h>
16 #include <drm/drm_rect.h>
17 
18 #include "dpu_kms.h"
19 #include "dpu_hw_lm.h"
20 #include "dpu_hw_ctl.h"
21 #include "dpu_crtc.h"
22 #include "dpu_plane.h"
23 #include "dpu_encoder.h"
24 #include "dpu_vbif.h"
25 #include "dpu_core_perf.h"
26 #include "dpu_trace.h"
27 
28 #define DPU_DRM_BLEND_OP_NOT_DEFINED    0
29 #define DPU_DRM_BLEND_OP_OPAQUE         1
30 #define DPU_DRM_BLEND_OP_PREMULTIPLIED  2
31 #define DPU_DRM_BLEND_OP_COVERAGE       3
32 #define DPU_DRM_BLEND_OP_MAX            4
33 
34 /* layer mixer index on dpu_crtc */
35 #define LEFT_MIXER 0
36 #define RIGHT_MIXER 1
37 
38 /* timeout in ms waiting for frame done */
39 #define DPU_CRTC_FRAME_DONE_TIMEOUT_MS	60
40 
41 static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
42 {
43 	struct msm_drm_private *priv = crtc->dev->dev_private;
44 
45 	return to_dpu_kms(priv->kms);
46 }
47 
48 static void dpu_crtc_destroy(struct drm_crtc *crtc)
49 {
50 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
51 
52 	DPU_DEBUG("\n");
53 
54 	if (!crtc)
55 		return;
56 
57 	drm_crtc_cleanup(crtc);
58 	kfree(dpu_crtc);
59 }
60 
61 static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
62 		struct dpu_plane_state *pstate, struct dpu_format *format)
63 {
64 	struct dpu_hw_mixer *lm = mixer->hw_lm;
65 	uint32_t blend_op;
66 	struct drm_format_name_buf format_name;
67 
68 	/* default to opaque blending */
69 	blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
70 		DPU_BLEND_BG_ALPHA_BG_CONST;
71 
72 	if (format->alpha_enable) {
73 		/* coverage blending */
74 		blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL |
75 			DPU_BLEND_BG_ALPHA_FG_PIXEL |
76 			DPU_BLEND_BG_INV_ALPHA;
77 	}
78 
79 	lm->ops.setup_blend_config(lm, pstate->stage,
80 				0xFF, 0, blend_op);
81 
82 	DPU_DEBUG("format:%s, alpha_en:%u blend_op:0x%x\n",
83 		drm_get_format_name(format->base.pixel_format, &format_name),
84 		format->alpha_enable, blend_op);
85 }
86 
87 static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
88 {
89 	struct dpu_crtc *dpu_crtc;
90 	struct dpu_crtc_state *crtc_state;
91 	int lm_idx, lm_horiz_position;
92 
93 	dpu_crtc = to_dpu_crtc(crtc);
94 	crtc_state = to_dpu_crtc_state(crtc->state);
95 
96 	lm_horiz_position = 0;
97 	for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) {
98 		const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx];
99 		struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm;
100 		struct dpu_hw_mixer_cfg cfg;
101 
102 		if (!lm_roi || !drm_rect_visible(lm_roi))
103 			continue;
104 
105 		cfg.out_width = drm_rect_width(lm_roi);
106 		cfg.out_height = drm_rect_height(lm_roi);
107 		cfg.right_mixer = lm_horiz_position++;
108 		cfg.flags = 0;
109 		hw_lm->ops.setup_mixer_out(hw_lm, &cfg);
110 	}
111 }
112 
113 static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
114 	struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer)
115 {
116 	struct drm_plane *plane;
117 	struct drm_framebuffer *fb;
118 	struct drm_plane_state *state;
119 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
120 	struct dpu_plane_state *pstate = NULL;
121 	struct dpu_format *format;
122 	struct dpu_hw_ctl *ctl = mixer->lm_ctl;
123 	struct dpu_hw_stage_cfg *stage_cfg = &dpu_crtc->stage_cfg;
124 
125 	u32 flush_mask;
126 	uint32_t stage_idx, lm_idx;
127 	int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 };
128 	bool bg_alpha_enable = false;
129 
130 	drm_atomic_crtc_for_each_plane(plane, crtc) {
131 		state = plane->state;
132 		if (!state)
133 			continue;
134 
135 		pstate = to_dpu_plane_state(state);
136 		fb = state->fb;
137 
138 		dpu_plane_get_ctl_flush(plane, ctl, &flush_mask);
139 
140 		DPU_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n",
141 				crtc->base.id,
142 				pstate->stage,
143 				plane->base.id,
144 				dpu_plane_pipe(plane) - SSPP_VIG0,
145 				state->fb ? state->fb->base.id : -1);
146 
147 		format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));
148 
149 		if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
150 			bg_alpha_enable = true;
151 
152 		stage_idx = zpos_cnt[pstate->stage]++;
153 		stage_cfg->stage[pstate->stage][stage_idx] =
154 					dpu_plane_pipe(plane);
155 		stage_cfg->multirect_index[pstate->stage][stage_idx] =
156 					pstate->multirect_index;
157 
158 		trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
159 					   state, pstate, stage_idx,
160 					   dpu_plane_pipe(plane) - SSPP_VIG0,
161 					   format->base.pixel_format,
162 					   fb ? fb->modifier : 0);
163 
164 		/* blend config update */
165 		for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
166 			_dpu_crtc_setup_blend_cfg(mixer + lm_idx,
167 						pstate, format);
168 
169 			mixer[lm_idx].flush_mask |= flush_mask;
170 
171 			if (bg_alpha_enable && !format->alpha_enable)
172 				mixer[lm_idx].mixer_op_mode = 0;
173 			else
174 				mixer[lm_idx].mixer_op_mode |=
175 						1 << pstate->stage;
176 		}
177 	}
178 
179 	 _dpu_crtc_program_lm_output_roi(crtc);
180 }
181 
182 /**
183  * _dpu_crtc_blend_setup - configure crtc mixers
184  * @crtc: Pointer to drm crtc structure
185  */
186 static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
187 {
188 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
189 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
190 	struct dpu_crtc_mixer *mixer = cstate->mixers;
191 	struct dpu_hw_ctl *ctl;
192 	struct dpu_hw_mixer *lm;
193 	int i;
194 
195 	DPU_DEBUG("%s\n", dpu_crtc->name);
196 
197 	for (i = 0; i < cstate->num_mixers; i++) {
198 		if (!mixer[i].hw_lm || !mixer[i].lm_ctl) {
199 			DPU_ERROR("invalid lm or ctl assigned to mixer\n");
200 			return;
201 		}
202 		mixer[i].mixer_op_mode = 0;
203 		mixer[i].flush_mask = 0;
204 		if (mixer[i].lm_ctl->ops.clear_all_blendstages)
205 			mixer[i].lm_ctl->ops.clear_all_blendstages(
206 					mixer[i].lm_ctl);
207 	}
208 
209 	/* initialize stage cfg */
210 	memset(&dpu_crtc->stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg));
211 
212 	_dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer);
213 
214 	for (i = 0; i < cstate->num_mixers; i++) {
215 		ctl = mixer[i].lm_ctl;
216 		lm = mixer[i].hw_lm;
217 
218 		lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
219 
220 		mixer[i].flush_mask |= ctl->ops.get_bitmask_mixer(ctl,
221 			mixer[i].hw_lm->idx);
222 
223 		/* stage config flush mask */
224 		ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask);
225 
226 		DPU_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n",
227 			mixer[i].hw_lm->idx - LM_0,
228 			mixer[i].mixer_op_mode,
229 			ctl->idx - CTL_0,
230 			mixer[i].flush_mask);
231 
232 		ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
233 			&dpu_crtc->stage_cfg);
234 	}
235 }
236 
237 /**
238  *  _dpu_crtc_complete_flip - signal pending page_flip events
239  * Any pending vblank events are added to the vblank_event_list
240  * so that the next vblank interrupt shall signal them.
241  * However PAGE_FLIP events are not handled through the vblank_event_list.
242  * This API signals any pending PAGE_FLIP events requested through
243  * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the dpu_crtc->event.
244  * @crtc: Pointer to drm crtc structure
245  */
246 static void _dpu_crtc_complete_flip(struct drm_crtc *crtc)
247 {
248 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
249 	struct drm_device *dev = crtc->dev;
250 	unsigned long flags;
251 
252 	spin_lock_irqsave(&dev->event_lock, flags);
253 	if (dpu_crtc->event) {
254 		DRM_DEBUG_VBL("%s: send event: %pK\n", dpu_crtc->name,
255 			      dpu_crtc->event);
256 		trace_dpu_crtc_complete_flip(DRMID(crtc));
257 		drm_crtc_send_vblank_event(crtc, dpu_crtc->event);
258 		dpu_crtc->event = NULL;
259 	}
260 	spin_unlock_irqrestore(&dev->event_lock, flags);
261 }
262 
263 enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc)
264 {
265 	struct drm_encoder *encoder;
266 
267 	if (!crtc || !crtc->dev) {
268 		DPU_ERROR("invalid crtc\n");
269 		return INTF_MODE_NONE;
270 	}
271 
272 	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
273 
274 	/* TODO: Returns the first INTF_MODE, could there be multiple values? */
275 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
276 		return dpu_encoder_get_intf_mode(encoder);
277 
278 	return INTF_MODE_NONE;
279 }
280 
281 void dpu_crtc_vblank_callback(struct drm_crtc *crtc)
282 {
283 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
284 
285 	/* keep statistics on vblank callback - with auto reset via debugfs */
286 	if (ktime_compare(dpu_crtc->vblank_cb_time, ktime_set(0, 0)) == 0)
287 		dpu_crtc->vblank_cb_time = ktime_get();
288 	else
289 		dpu_crtc->vblank_cb_count++;
290 	_dpu_crtc_complete_flip(crtc);
291 	drm_crtc_handle_vblank(crtc);
292 	trace_dpu_crtc_vblank_cb(DRMID(crtc));
293 }
294 
295 static void dpu_crtc_release_bw_unlocked(struct drm_crtc *crtc)
296 {
297 	int ret = 0;
298 	struct drm_modeset_acquire_ctx ctx;
299 
300 	DRM_MODESET_LOCK_ALL_BEGIN(crtc->dev, ctx, 0, ret);
301 	dpu_core_perf_crtc_release_bw(crtc);
302 	DRM_MODESET_LOCK_ALL_END(ctx, ret);
303 	if (ret)
304 		DRM_ERROR("Failed to acquire modeset locks to release bw, %d\n",
305 			  ret);
306 }
307 
308 static void dpu_crtc_frame_event_work(struct kthread_work *work)
309 {
310 	struct dpu_crtc_frame_event *fevent = container_of(work,
311 			struct dpu_crtc_frame_event, work);
312 	struct drm_crtc *crtc = fevent->crtc;
313 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
314 	unsigned long flags;
315 	bool frame_done = false;
316 
317 	DPU_ATRACE_BEGIN("crtc_frame_event");
318 
319 	DRM_DEBUG_KMS("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
320 			ktime_to_ns(fevent->ts));
321 
322 	if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE
323 				| DPU_ENCODER_FRAME_EVENT_ERROR
324 				| DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
325 
326 		if (atomic_read(&dpu_crtc->frame_pending) < 1) {
327 			/* this should not happen */
328 			DRM_ERROR("crtc%d ev:%u ts:%lld frame_pending:%d\n",
329 					crtc->base.id,
330 					fevent->event,
331 					ktime_to_ns(fevent->ts),
332 					atomic_read(&dpu_crtc->frame_pending));
333 		} else if (atomic_dec_return(&dpu_crtc->frame_pending) == 0) {
334 			/* release bandwidth and other resources */
335 			trace_dpu_crtc_frame_event_done(DRMID(crtc),
336 							fevent->event);
337 			dpu_crtc_release_bw_unlocked(crtc);
338 		} else {
339 			trace_dpu_crtc_frame_event_more_pending(DRMID(crtc),
340 								fevent->event);
341 		}
342 
343 		if (fevent->event & DPU_ENCODER_FRAME_EVENT_DONE)
344 			dpu_core_perf_crtc_update(crtc, 0, false);
345 
346 		if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE
347 					| DPU_ENCODER_FRAME_EVENT_ERROR))
348 			frame_done = true;
349 	}
350 
351 	if (fevent->event & DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)
352 		DPU_ERROR("crtc%d ts:%lld received panel dead event\n",
353 				crtc->base.id, ktime_to_ns(fevent->ts));
354 
355 	if (frame_done)
356 		complete_all(&dpu_crtc->frame_done_comp);
357 
358 	spin_lock_irqsave(&dpu_crtc->spin_lock, flags);
359 	list_add_tail(&fevent->list, &dpu_crtc->frame_event_list);
360 	spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
361 	DPU_ATRACE_END("crtc_frame_event");
362 }
363 
364 /*
365  * dpu_crtc_frame_event_cb - crtc frame event callback API. CRTC module
366  * registers this API to encoder for all frame event callbacks like
367  * frame_error, frame_done, idle_timeout, etc. Encoder may call different events
368  * from different context - IRQ, user thread, commit_thread, etc. Each event
369  * should be carefully reviewed and should be processed in proper task context
370  * to avoid schedulin delay or properly manage the irq context's bottom half
371  * processing.
372  */
373 static void dpu_crtc_frame_event_cb(void *data, u32 event)
374 {
375 	struct drm_crtc *crtc = (struct drm_crtc *)data;
376 	struct dpu_crtc *dpu_crtc;
377 	struct msm_drm_private *priv;
378 	struct dpu_crtc_frame_event *fevent;
379 	unsigned long flags;
380 	u32 crtc_id;
381 
382 	/* Nothing to do on idle event */
383 	if (event & DPU_ENCODER_FRAME_EVENT_IDLE)
384 		return;
385 
386 	dpu_crtc = to_dpu_crtc(crtc);
387 	priv = crtc->dev->dev_private;
388 	crtc_id = drm_crtc_index(crtc);
389 
390 	trace_dpu_crtc_frame_event_cb(DRMID(crtc), event);
391 
392 	spin_lock_irqsave(&dpu_crtc->spin_lock, flags);
393 	fevent = list_first_entry_or_null(&dpu_crtc->frame_event_list,
394 			struct dpu_crtc_frame_event, list);
395 	if (fevent)
396 		list_del_init(&fevent->list);
397 	spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
398 
399 	if (!fevent) {
400 		DRM_ERROR("crtc%d event %d overflow\n", crtc->base.id, event);
401 		return;
402 	}
403 
404 	fevent->event = event;
405 	fevent->crtc = crtc;
406 	fevent->ts = ktime_get();
407 	kthread_queue_work(&priv->event_thread[crtc_id].worker, &fevent->work);
408 }
409 
410 void dpu_crtc_complete_commit(struct drm_crtc *crtc,
411 		struct drm_crtc_state *old_state)
412 {
413 	if (!crtc || !crtc->state) {
414 		DPU_ERROR("invalid crtc\n");
415 		return;
416 	}
417 	trace_dpu_crtc_complete_commit(DRMID(crtc));
418 }
419 
420 static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
421 		struct drm_crtc_state *state)
422 {
423 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
424 	struct drm_display_mode *adj_mode = &state->adjusted_mode;
425 	u32 crtc_split_width = adj_mode->hdisplay / cstate->num_mixers;
426 	int i;
427 
428 	for (i = 0; i < cstate->num_mixers; i++) {
429 		struct drm_rect *r = &cstate->lm_bounds[i];
430 		r->x1 = crtc_split_width * i;
431 		r->y1 = 0;
432 		r->x2 = r->x1 + crtc_split_width;
433 		r->y2 = adj_mode->vdisplay;
434 
435 		trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i, r);
436 	}
437 
438 	drm_mode_debug_printmodeline(adj_mode);
439 }
440 
441 static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
442 		struct drm_crtc_state *old_state)
443 {
444 	struct dpu_crtc *dpu_crtc;
445 	struct dpu_crtc_state *cstate;
446 	struct drm_encoder *encoder;
447 	struct drm_device *dev;
448 	unsigned long flags;
449 	struct dpu_crtc_smmu_state_data *smmu_state;
450 
451 	if (!crtc) {
452 		DPU_ERROR("invalid crtc\n");
453 		return;
454 	}
455 
456 	if (!crtc->state->enable) {
457 		DPU_DEBUG("crtc%d -> enable %d, skip atomic_begin\n",
458 				crtc->base.id, crtc->state->enable);
459 		return;
460 	}
461 
462 	DPU_DEBUG("crtc%d\n", crtc->base.id);
463 
464 	dpu_crtc = to_dpu_crtc(crtc);
465 	cstate = to_dpu_crtc_state(crtc->state);
466 	dev = crtc->dev;
467 	smmu_state = &dpu_crtc->smmu_state;
468 
469 	_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
470 
471 	if (dpu_crtc->event) {
472 		WARN_ON(dpu_crtc->event);
473 	} else {
474 		spin_lock_irqsave(&dev->event_lock, flags);
475 		dpu_crtc->event = crtc->state->event;
476 		crtc->state->event = NULL;
477 		spin_unlock_irqrestore(&dev->event_lock, flags);
478 	}
479 
480 	/* encoder will trigger pending mask now */
481 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
482 		dpu_encoder_trigger_kickoff_pending(encoder);
483 
484 	/*
485 	 * If no mixers have been allocated in dpu_crtc_atomic_check(),
486 	 * it means we are trying to flush a CRTC whose state is disabled:
487 	 * nothing else needs to be done.
488 	 */
489 	if (unlikely(!cstate->num_mixers))
490 		return;
491 
492 	_dpu_crtc_blend_setup(crtc);
493 
494 	/*
495 	 * PP_DONE irq is only used by command mode for now.
496 	 * It is better to request pending before FLUSH and START trigger
497 	 * to make sure no pp_done irq missed.
498 	 * This is safe because no pp_done will happen before SW trigger
499 	 * in command mode.
500 	 */
501 }
502 
503 static void dpu_crtc_atomic_flush(struct drm_crtc *crtc,
504 		struct drm_crtc_state *old_crtc_state)
505 {
506 	struct dpu_crtc *dpu_crtc;
507 	struct drm_device *dev;
508 	struct drm_plane *plane;
509 	struct msm_drm_private *priv;
510 	struct msm_drm_thread *event_thread;
511 	unsigned long flags;
512 	struct dpu_crtc_state *cstate;
513 
514 	if (!crtc->state->enable) {
515 		DPU_DEBUG("crtc%d -> enable %d, skip atomic_flush\n",
516 				crtc->base.id, crtc->state->enable);
517 		return;
518 	}
519 
520 	DPU_DEBUG("crtc%d\n", crtc->base.id);
521 
522 	dpu_crtc = to_dpu_crtc(crtc);
523 	cstate = to_dpu_crtc_state(crtc->state);
524 	dev = crtc->dev;
525 	priv = dev->dev_private;
526 
527 	if (crtc->index >= ARRAY_SIZE(priv->event_thread)) {
528 		DPU_ERROR("invalid crtc index[%d]\n", crtc->index);
529 		return;
530 	}
531 
532 	event_thread = &priv->event_thread[crtc->index];
533 
534 	if (dpu_crtc->event) {
535 		DPU_DEBUG("already received dpu_crtc->event\n");
536 	} else {
537 		spin_lock_irqsave(&dev->event_lock, flags);
538 		dpu_crtc->event = crtc->state->event;
539 		crtc->state->event = NULL;
540 		spin_unlock_irqrestore(&dev->event_lock, flags);
541 	}
542 
543 	/*
544 	 * If no mixers has been allocated in dpu_crtc_atomic_check(),
545 	 * it means we are trying to flush a CRTC whose state is disabled:
546 	 * nothing else needs to be done.
547 	 */
548 	if (unlikely(!cstate->num_mixers))
549 		return;
550 
551 	/*
552 	 * For planes without commit update, drm framework will not add
553 	 * those planes to current state since hardware update is not
554 	 * required. However, if those planes were power collapsed since
555 	 * last commit cycle, driver has to restore the hardware state
556 	 * of those planes explicitly here prior to plane flush.
557 	 */
558 	drm_atomic_crtc_for_each_plane(plane, crtc)
559 		dpu_plane_restore(plane);
560 
561 	/* update performance setting before crtc kickoff */
562 	dpu_core_perf_crtc_update(crtc, 1, false);
563 
564 	/*
565 	 * Final plane updates: Give each plane a chance to complete all
566 	 *                      required writes/flushing before crtc's "flush
567 	 *                      everything" call below.
568 	 */
569 	drm_atomic_crtc_for_each_plane(plane, crtc) {
570 		if (dpu_crtc->smmu_state.transition_error)
571 			dpu_plane_set_error(plane, true);
572 		dpu_plane_flush(plane);
573 	}
574 
575 	/* Kickoff will be scheduled by outer layer */
576 }
577 
578 /**
579  * dpu_crtc_destroy_state - state destroy hook
580  * @crtc: drm CRTC
581  * @state: CRTC state object to release
582  */
583 static void dpu_crtc_destroy_state(struct drm_crtc *crtc,
584 		struct drm_crtc_state *state)
585 {
586 	struct dpu_crtc *dpu_crtc;
587 	struct dpu_crtc_state *cstate;
588 
589 	if (!crtc || !state) {
590 		DPU_ERROR("invalid argument(s)\n");
591 		return;
592 	}
593 
594 	dpu_crtc = to_dpu_crtc(crtc);
595 	cstate = to_dpu_crtc_state(state);
596 
597 	DPU_DEBUG("crtc%d\n", crtc->base.id);
598 
599 	__drm_atomic_helper_crtc_destroy_state(state);
600 
601 	kfree(cstate);
602 }
603 
604 static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc)
605 {
606 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
607 	int ret, rc = 0;
608 
609 	if (!atomic_read(&dpu_crtc->frame_pending)) {
610 		DPU_DEBUG("no frames pending\n");
611 		return 0;
612 	}
613 
614 	DPU_ATRACE_BEGIN("frame done completion wait");
615 	ret = wait_for_completion_timeout(&dpu_crtc->frame_done_comp,
616 			msecs_to_jiffies(DPU_CRTC_FRAME_DONE_TIMEOUT_MS));
617 	if (!ret) {
618 		DRM_ERROR("frame done wait timed out, ret:%d\n", ret);
619 		rc = -ETIMEDOUT;
620 	}
621 	DPU_ATRACE_END("frame done completion wait");
622 
623 	return rc;
624 }
625 
626 void dpu_crtc_commit_kickoff(struct drm_crtc *crtc, bool async)
627 {
628 	struct drm_encoder *encoder;
629 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
630 	struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
631 	struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
632 	int ret;
633 
634 	/*
635 	 * If no mixers has been allocated in dpu_crtc_atomic_check(),
636 	 * it means we are trying to start a CRTC whose state is disabled:
637 	 * nothing else needs to be done.
638 	 */
639 	if (unlikely(!cstate->num_mixers))
640 		return;
641 
642 	DPU_ATRACE_BEGIN("crtc_commit");
643 
644 	/*
645 	 * Encoder will flush/start now, unless it has a tx pending. If so, it
646 	 * may delay and flush at an irq event (e.g. ppdone)
647 	 */
648 	drm_for_each_encoder_mask(encoder, crtc->dev,
649 				  crtc->state->encoder_mask)
650 		dpu_encoder_prepare_for_kickoff(encoder, async);
651 
652 	if (!async) {
653 		/* wait for frame_event_done completion */
654 		DPU_ATRACE_BEGIN("wait_for_frame_done_event");
655 		ret = _dpu_crtc_wait_for_frame_done(crtc);
656 		DPU_ATRACE_END("wait_for_frame_done_event");
657 		if (ret) {
658 			DPU_ERROR("crtc%d wait for frame done failed;frame_pending%d\n",
659 					crtc->base.id,
660 					atomic_read(&dpu_crtc->frame_pending));
661 			goto end;
662 		}
663 
664 		if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) {
665 			/* acquire bandwidth and other resources */
666 			DPU_DEBUG("crtc%d first commit\n", crtc->base.id);
667 		} else
668 			DPU_DEBUG("crtc%d commit\n", crtc->base.id);
669 
670 		dpu_crtc->play_count++;
671 	}
672 
673 	dpu_vbif_clear_errors(dpu_kms);
674 
675 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
676 		dpu_encoder_kickoff(encoder, async);
677 
678 end:
679 	if (!async)
680 		reinit_completion(&dpu_crtc->frame_done_comp);
681 	DPU_ATRACE_END("crtc_commit");
682 }
683 
684 static void dpu_crtc_reset(struct drm_crtc *crtc)
685 {
686 	struct dpu_crtc_state *cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
687 
688 	if (crtc->state)
689 		dpu_crtc_destroy_state(crtc, crtc->state);
690 
691 	__drm_atomic_helper_crtc_reset(crtc, &cstate->base);
692 }
693 
694 /**
695  * dpu_crtc_duplicate_state - state duplicate hook
696  * @crtc: Pointer to drm crtc structure
697  * @Returns: Pointer to new drm_crtc_state structure
698  */
699 static struct drm_crtc_state *dpu_crtc_duplicate_state(struct drm_crtc *crtc)
700 {
701 	struct dpu_crtc *dpu_crtc;
702 	struct dpu_crtc_state *cstate, *old_cstate;
703 
704 	if (!crtc || !crtc->state) {
705 		DPU_ERROR("invalid argument(s)\n");
706 		return NULL;
707 	}
708 
709 	dpu_crtc = to_dpu_crtc(crtc);
710 	old_cstate = to_dpu_crtc_state(crtc->state);
711 	cstate = kmemdup(old_cstate, sizeof(*old_cstate), GFP_KERNEL);
712 	if (!cstate) {
713 		DPU_ERROR("failed to allocate state\n");
714 		return NULL;
715 	}
716 
717 	/* duplicate base helper */
718 	__drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base);
719 
720 	return &cstate->base;
721 }
722 
723 static void dpu_crtc_disable(struct drm_crtc *crtc,
724 			     struct drm_crtc_state *old_crtc_state)
725 {
726 	struct dpu_crtc *dpu_crtc;
727 	struct dpu_crtc_state *cstate;
728 	struct drm_display_mode *mode;
729 	struct drm_encoder *encoder;
730 	struct msm_drm_private *priv;
731 	unsigned long flags;
732 
733 	if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) {
734 		DPU_ERROR("invalid crtc\n");
735 		return;
736 	}
737 	dpu_crtc = to_dpu_crtc(crtc);
738 	cstate = to_dpu_crtc_state(crtc->state);
739 	mode = &cstate->base.adjusted_mode;
740 	priv = crtc->dev->dev_private;
741 
742 	DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
743 
744 	/* Disable/save vblank irq handling */
745 	drm_crtc_vblank_off(crtc);
746 
747 	drm_for_each_encoder_mask(encoder, crtc->dev,
748 				  old_crtc_state->encoder_mask)
749 		dpu_encoder_assign_crtc(encoder, NULL);
750 
751 	/* wait for frame_event_done completion */
752 	if (_dpu_crtc_wait_for_frame_done(crtc))
753 		DPU_ERROR("crtc%d wait for frame done failed;frame_pending%d\n",
754 				crtc->base.id,
755 				atomic_read(&dpu_crtc->frame_pending));
756 
757 	trace_dpu_crtc_disable(DRMID(crtc), false, dpu_crtc);
758 	dpu_crtc->enabled = false;
759 
760 	if (atomic_read(&dpu_crtc->frame_pending)) {
761 		trace_dpu_crtc_disable_frame_pending(DRMID(crtc),
762 				     atomic_read(&dpu_crtc->frame_pending));
763 		dpu_core_perf_crtc_release_bw(crtc);
764 		atomic_set(&dpu_crtc->frame_pending, 0);
765 	}
766 
767 	dpu_core_perf_crtc_update(crtc, 0, true);
768 
769 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
770 		dpu_encoder_register_frame_event_callback(encoder, NULL, NULL);
771 
772 	memset(cstate->mixers, 0, sizeof(cstate->mixers));
773 	cstate->num_mixers = 0;
774 
775 	/* disable clk & bw control until clk & bw properties are set */
776 	cstate->bw_control = false;
777 	cstate->bw_split_vote = false;
778 
779 	if (crtc->state->event && !crtc->state->active) {
780 		spin_lock_irqsave(&crtc->dev->event_lock, flags);
781 		drm_crtc_send_vblank_event(crtc, crtc->state->event);
782 		crtc->state->event = NULL;
783 		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
784 	}
785 
786 	pm_runtime_put_sync(crtc->dev->dev);
787 }
788 
789 static void dpu_crtc_enable(struct drm_crtc *crtc,
790 		struct drm_crtc_state *old_crtc_state)
791 {
792 	struct dpu_crtc *dpu_crtc;
793 	struct drm_encoder *encoder;
794 	struct msm_drm_private *priv;
795 
796 	if (!crtc || !crtc->dev || !crtc->dev->dev_private) {
797 		DPU_ERROR("invalid crtc\n");
798 		return;
799 	}
800 	priv = crtc->dev->dev_private;
801 
802 	pm_runtime_get_sync(crtc->dev->dev);
803 
804 	DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
805 	dpu_crtc = to_dpu_crtc(crtc);
806 
807 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
808 		dpu_encoder_register_frame_event_callback(encoder,
809 				dpu_crtc_frame_event_cb, (void *)crtc);
810 
811 	trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc);
812 	dpu_crtc->enabled = true;
813 
814 	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
815 		dpu_encoder_assign_crtc(encoder, crtc);
816 
817 	/* Enable/restore vblank irq handling */
818 	drm_crtc_vblank_on(crtc);
819 }
820 
821 struct plane_state {
822 	struct dpu_plane_state *dpu_pstate;
823 	const struct drm_plane_state *drm_pstate;
824 	int stage;
825 	u32 pipe_id;
826 };
827 
828 static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
829 		struct drm_crtc_state *state)
830 {
831 	struct dpu_crtc *dpu_crtc;
832 	struct plane_state *pstates;
833 	struct dpu_crtc_state *cstate;
834 
835 	const struct drm_plane_state *pstate;
836 	struct drm_plane *plane;
837 	struct drm_display_mode *mode;
838 
839 	int cnt = 0, rc = 0, mixer_width, i, z_pos;
840 
841 	struct dpu_multirect_plane_states multirect_plane[DPU_STAGE_MAX * 2];
842 	int multirect_count = 0;
843 	const struct drm_plane_state *pipe_staged[SSPP_MAX];
844 	int left_zpos_cnt = 0, right_zpos_cnt = 0;
845 	struct drm_rect crtc_rect = { 0 };
846 
847 	if (!crtc) {
848 		DPU_ERROR("invalid crtc\n");
849 		return -EINVAL;
850 	}
851 
852 	pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL);
853 
854 	dpu_crtc = to_dpu_crtc(crtc);
855 	cstate = to_dpu_crtc_state(state);
856 
857 	if (!state->enable || !state->active) {
858 		DPU_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n",
859 				crtc->base.id, state->enable, state->active);
860 		goto end;
861 	}
862 
863 	mode = &state->adjusted_mode;
864 	DPU_DEBUG("%s: check", dpu_crtc->name);
865 
866 	/* force a full mode set if active state changed */
867 	if (state->active_changed)
868 		state->mode_changed = true;
869 
870 	memset(pipe_staged, 0, sizeof(pipe_staged));
871 
872 	mixer_width = mode->hdisplay / cstate->num_mixers;
873 
874 	_dpu_crtc_setup_lm_bounds(crtc, state);
875 
876 	crtc_rect.x2 = mode->hdisplay;
877 	crtc_rect.y2 = mode->vdisplay;
878 
879 	 /* get plane state for all drm planes associated with crtc state */
880 	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
881 		struct drm_rect dst, clip = crtc_rect;
882 
883 		if (IS_ERR_OR_NULL(pstate)) {
884 			rc = PTR_ERR(pstate);
885 			DPU_ERROR("%s: failed to get plane%d state, %d\n",
886 					dpu_crtc->name, plane->base.id, rc);
887 			goto end;
888 		}
889 		if (cnt >= DPU_STAGE_MAX * 4)
890 			continue;
891 
892 		pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate);
893 		pstates[cnt].drm_pstate = pstate;
894 		pstates[cnt].stage = pstate->normalized_zpos;
895 		pstates[cnt].pipe_id = dpu_plane_pipe(plane);
896 
897 		if (pipe_staged[pstates[cnt].pipe_id]) {
898 			multirect_plane[multirect_count].r0 =
899 				pipe_staged[pstates[cnt].pipe_id];
900 			multirect_plane[multirect_count].r1 = pstate;
901 			multirect_count++;
902 
903 			pipe_staged[pstates[cnt].pipe_id] = NULL;
904 		} else {
905 			pipe_staged[pstates[cnt].pipe_id] = pstate;
906 		}
907 
908 		cnt++;
909 
910 		dst = drm_plane_state_dest(pstate);
911 		if (!drm_rect_intersect(&clip, &dst)) {
912 			DPU_ERROR("invalid vertical/horizontal destination\n");
913 			DPU_ERROR("display: " DRM_RECT_FMT " plane: "
914 				  DRM_RECT_FMT "\n", DRM_RECT_ARG(&crtc_rect),
915 				  DRM_RECT_ARG(&dst));
916 			rc = -E2BIG;
917 			goto end;
918 		}
919 	}
920 
921 	for (i = 1; i < SSPP_MAX; i++) {
922 		if (pipe_staged[i]) {
923 			dpu_plane_clear_multirect(pipe_staged[i]);
924 
925 			if (is_dpu_plane_virtual(pipe_staged[i]->plane)) {
926 				DPU_ERROR(
927 					"r1 only virt plane:%d not supported\n",
928 					pipe_staged[i]->plane->base.id);
929 				rc  = -EINVAL;
930 				goto end;
931 			}
932 		}
933 	}
934 
935 	z_pos = -1;
936 	for (i = 0; i < cnt; i++) {
937 		/* reset counts at every new blend stage */
938 		if (pstates[i].stage != z_pos) {
939 			left_zpos_cnt = 0;
940 			right_zpos_cnt = 0;
941 			z_pos = pstates[i].stage;
942 		}
943 
944 		/* verify z_pos setting before using it */
945 		if (z_pos >= DPU_STAGE_MAX - DPU_STAGE_0) {
946 			DPU_ERROR("> %d plane stages assigned\n",
947 					DPU_STAGE_MAX - DPU_STAGE_0);
948 			rc = -EINVAL;
949 			goto end;
950 		} else if (pstates[i].drm_pstate->crtc_x < mixer_width) {
951 			if (left_zpos_cnt == 2) {
952 				DPU_ERROR("> 2 planes @ stage %d on left\n",
953 					z_pos);
954 				rc = -EINVAL;
955 				goto end;
956 			}
957 			left_zpos_cnt++;
958 
959 		} else {
960 			if (right_zpos_cnt == 2) {
961 				DPU_ERROR("> 2 planes @ stage %d on right\n",
962 					z_pos);
963 				rc = -EINVAL;
964 				goto end;
965 			}
966 			right_zpos_cnt++;
967 		}
968 
969 		pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0;
970 		DPU_DEBUG("%s: zpos %d", dpu_crtc->name, z_pos);
971 	}
972 
973 	for (i = 0; i < multirect_count; i++) {
974 		if (dpu_plane_validate_multirect_v2(&multirect_plane[i])) {
975 			DPU_ERROR(
976 			"multirect validation failed for planes (%d - %d)\n",
977 					multirect_plane[i].r0->plane->base.id,
978 					multirect_plane[i].r1->plane->base.id);
979 			rc = -EINVAL;
980 			goto end;
981 		}
982 	}
983 
984 	rc = dpu_core_perf_crtc_check(crtc, state);
985 	if (rc) {
986 		DPU_ERROR("crtc%d failed performance check %d\n",
987 				crtc->base.id, rc);
988 		goto end;
989 	}
990 
991 	/* validate source split:
992 	 * use pstates sorted by stage to check planes on same stage
993 	 * we assume that all pipes are in source split so its valid to compare
994 	 * without taking into account left/right mixer placement
995 	 */
996 	for (i = 1; i < cnt; i++) {
997 		struct plane_state *prv_pstate, *cur_pstate;
998 		struct drm_rect left_rect, right_rect;
999 		int32_t left_pid, right_pid;
1000 		int32_t stage;
1001 
1002 		prv_pstate = &pstates[i - 1];
1003 		cur_pstate = &pstates[i];
1004 		if (prv_pstate->stage != cur_pstate->stage)
1005 			continue;
1006 
1007 		stage = cur_pstate->stage;
1008 
1009 		left_pid = prv_pstate->dpu_pstate->base.plane->base.id;
1010 		left_rect = drm_plane_state_dest(prv_pstate->drm_pstate);
1011 
1012 		right_pid = cur_pstate->dpu_pstate->base.plane->base.id;
1013 		right_rect = drm_plane_state_dest(cur_pstate->drm_pstate);
1014 
1015 		if (right_rect.x1 < left_rect.x1) {
1016 			swap(left_pid, right_pid);
1017 			swap(left_rect, right_rect);
1018 		}
1019 
1020 		/**
1021 		 * - planes are enumerated in pipe-priority order such that
1022 		 *   planes with lower drm_id must be left-most in a shared
1023 		 *   blend-stage when using source split.
1024 		 * - planes in source split must be contiguous in width
1025 		 * - planes in source split must have same dest yoff and height
1026 		 */
1027 		if (right_pid < left_pid) {
1028 			DPU_ERROR(
1029 				"invalid src split cfg. priority mismatch. stage: %d left: %d right: %d\n",
1030 				stage, left_pid, right_pid);
1031 			rc = -EINVAL;
1032 			goto end;
1033 		} else if (right_rect.x1 != drm_rect_width(&left_rect)) {
1034 			DPU_ERROR("non-contiguous coordinates for src split. "
1035 				  "stage: %d left: " DRM_RECT_FMT " right: "
1036 				  DRM_RECT_FMT "\n", stage,
1037 				  DRM_RECT_ARG(&left_rect),
1038 				  DRM_RECT_ARG(&right_rect));
1039 			rc = -EINVAL;
1040 			goto end;
1041 		} else if (left_rect.y1 != right_rect.y1 ||
1042 			   drm_rect_height(&left_rect) != drm_rect_height(&right_rect)) {
1043 			DPU_ERROR("source split at stage: %d. invalid "
1044 				  "yoff/height: left: " DRM_RECT_FMT " right: "
1045 				  DRM_RECT_FMT "\n", stage,
1046 				  DRM_RECT_ARG(&left_rect),
1047 				  DRM_RECT_ARG(&right_rect));
1048 			rc = -EINVAL;
1049 			goto end;
1050 		}
1051 	}
1052 
1053 end:
1054 	kfree(pstates);
1055 	return rc;
1056 }
1057 
1058 int dpu_crtc_vblank(struct drm_crtc *crtc, bool en)
1059 {
1060 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1061 	struct drm_encoder *enc;
1062 
1063 	trace_dpu_crtc_vblank(DRMID(&dpu_crtc->base), en, dpu_crtc);
1064 
1065 	/*
1066 	 * Normally we would iterate through encoder_mask in crtc state to find
1067 	 * attached encoders. In this case, we might be disabling vblank _after_
1068 	 * encoder_mask has been cleared.
1069 	 *
1070 	 * Instead, we "assign" a crtc to the encoder in enable and clear it in
1071 	 * disable (which is also after encoder_mask is cleared). So instead of
1072 	 * using encoder mask, we'll ask the encoder to toggle itself iff it's
1073 	 * currently assigned to our crtc.
1074 	 *
1075 	 * Note also that this function cannot be called while crtc is disabled
1076 	 * since we use drm_crtc_vblank_on/off. So we don't need to worry
1077 	 * about the assigned crtcs being inconsistent with the current state
1078 	 * (which means no need to worry about modeset locks).
1079 	 */
1080 	list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) {
1081 		trace_dpu_crtc_vblank_enable(DRMID(crtc), DRMID(enc), en,
1082 					     dpu_crtc);
1083 
1084 		dpu_encoder_toggle_vblank_for_crtc(enc, crtc, en);
1085 	}
1086 
1087 	return 0;
1088 }
1089 
1090 #ifdef CONFIG_DEBUG_FS
1091 static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
1092 {
1093 	struct dpu_crtc *dpu_crtc;
1094 	struct dpu_plane_state *pstate = NULL;
1095 	struct dpu_crtc_mixer *m;
1096 
1097 	struct drm_crtc *crtc;
1098 	struct drm_plane *plane;
1099 	struct drm_display_mode *mode;
1100 	struct drm_framebuffer *fb;
1101 	struct drm_plane_state *state;
1102 	struct dpu_crtc_state *cstate;
1103 
1104 	int i, out_width;
1105 
1106 	dpu_crtc = s->private;
1107 	crtc = &dpu_crtc->base;
1108 
1109 	drm_modeset_lock_all(crtc->dev);
1110 	cstate = to_dpu_crtc_state(crtc->state);
1111 
1112 	mode = &crtc->state->adjusted_mode;
1113 	out_width = mode->hdisplay / cstate->num_mixers;
1114 
1115 	seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id,
1116 				mode->hdisplay, mode->vdisplay);
1117 
1118 	seq_puts(s, "\n");
1119 
1120 	for (i = 0; i < cstate->num_mixers; ++i) {
1121 		m = &cstate->mixers[i];
1122 		if (!m->hw_lm)
1123 			seq_printf(s, "\tmixer[%d] has no lm\n", i);
1124 		else if (!m->lm_ctl)
1125 			seq_printf(s, "\tmixer[%d] has no ctl\n", i);
1126 		else
1127 			seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n",
1128 				m->hw_lm->idx - LM_0, m->lm_ctl->idx - CTL_0,
1129 				out_width, mode->vdisplay);
1130 	}
1131 
1132 	seq_puts(s, "\n");
1133 
1134 	drm_atomic_crtc_for_each_plane(plane, crtc) {
1135 		pstate = to_dpu_plane_state(plane->state);
1136 		state = plane->state;
1137 
1138 		if (!pstate || !state)
1139 			continue;
1140 
1141 		seq_printf(s, "\tplane:%u stage:%d\n", plane->base.id,
1142 			pstate->stage);
1143 
1144 		if (plane->state->fb) {
1145 			fb = plane->state->fb;
1146 
1147 			seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u ",
1148 				fb->base.id, (char *) &fb->format->format,
1149 				fb->width, fb->height);
1150 			for (i = 0; i < ARRAY_SIZE(fb->format->cpp); ++i)
1151 				seq_printf(s, "cpp[%d]:%u ",
1152 						i, fb->format->cpp[i]);
1153 			seq_puts(s, "\n\t");
1154 
1155 			seq_printf(s, "modifier:%8llu ", fb->modifier);
1156 			seq_puts(s, "\n");
1157 
1158 			seq_puts(s, "\t");
1159 			for (i = 0; i < ARRAY_SIZE(fb->pitches); i++)
1160 				seq_printf(s, "pitches[%d]:%8u ", i,
1161 							fb->pitches[i]);
1162 			seq_puts(s, "\n");
1163 
1164 			seq_puts(s, "\t");
1165 			for (i = 0; i < ARRAY_SIZE(fb->offsets); i++)
1166 				seq_printf(s, "offsets[%d]:%8u ", i,
1167 							fb->offsets[i]);
1168 			seq_puts(s, "\n");
1169 		}
1170 
1171 		seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n",
1172 			state->src_x, state->src_y, state->src_w, state->src_h);
1173 
1174 		seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
1175 			state->crtc_x, state->crtc_y, state->crtc_w,
1176 			state->crtc_h);
1177 		seq_printf(s, "\tmultirect: mode: %d index: %d\n",
1178 			pstate->multirect_mode, pstate->multirect_index);
1179 
1180 		seq_puts(s, "\n");
1181 	}
1182 	if (dpu_crtc->vblank_cb_count) {
1183 		ktime_t diff = ktime_sub(ktime_get(), dpu_crtc->vblank_cb_time);
1184 		s64 diff_ms = ktime_to_ms(diff);
1185 		s64 fps = diff_ms ? div_s64(
1186 				dpu_crtc->vblank_cb_count * 1000, diff_ms) : 0;
1187 
1188 		seq_printf(s,
1189 			"vblank fps:%lld count:%u total:%llums total_framecount:%llu\n",
1190 				fps, dpu_crtc->vblank_cb_count,
1191 				ktime_to_ms(diff), dpu_crtc->play_count);
1192 
1193 		/* reset time & count for next measurement */
1194 		dpu_crtc->vblank_cb_count = 0;
1195 		dpu_crtc->vblank_cb_time = ktime_set(0, 0);
1196 	}
1197 
1198 	drm_modeset_unlock_all(crtc->dev);
1199 
1200 	return 0;
1201 }
1202 
1203 static int _dpu_debugfs_status_open(struct inode *inode, struct file *file)
1204 {
1205 	return single_open(file, _dpu_debugfs_status_show, inode->i_private);
1206 }
1207 
1208 #define DEFINE_DPU_DEBUGFS_SEQ_FOPS(__prefix)                          \
1209 static int __prefix ## _open(struct inode *inode, struct file *file)	\
1210 {									\
1211 	return single_open(file, __prefix ## _show, inode->i_private);	\
1212 }									\
1213 static const struct file_operations __prefix ## _fops = {		\
1214 	.owner = THIS_MODULE,						\
1215 	.open = __prefix ## _open,					\
1216 	.release = single_release,					\
1217 	.read = seq_read,						\
1218 	.llseek = seq_lseek,						\
1219 }
1220 
1221 static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v)
1222 {
1223 	struct drm_crtc *crtc = (struct drm_crtc *) s->private;
1224 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1225 
1226 	seq_printf(s, "client type: %d\n", dpu_crtc_get_client_type(crtc));
1227 	seq_printf(s, "intf_mode: %d\n", dpu_crtc_get_intf_mode(crtc));
1228 	seq_printf(s, "core_clk_rate: %llu\n",
1229 			dpu_crtc->cur_perf.core_clk_rate);
1230 	seq_printf(s, "bw_ctl: %llu\n", dpu_crtc->cur_perf.bw_ctl);
1231 	seq_printf(s, "max_per_pipe_ib: %llu\n",
1232 				dpu_crtc->cur_perf.max_per_pipe_ib);
1233 
1234 	return 0;
1235 }
1236 DEFINE_DPU_DEBUGFS_SEQ_FOPS(dpu_crtc_debugfs_state);
1237 
1238 static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc)
1239 {
1240 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1241 
1242 	static const struct file_operations debugfs_status_fops = {
1243 		.open =		_dpu_debugfs_status_open,
1244 		.read =		seq_read,
1245 		.llseek =	seq_lseek,
1246 		.release =	single_release,
1247 	};
1248 
1249 	dpu_crtc->debugfs_root = debugfs_create_dir(dpu_crtc->name,
1250 			crtc->dev->primary->debugfs_root);
1251 
1252 	debugfs_create_file("status", 0400,
1253 			dpu_crtc->debugfs_root,
1254 			dpu_crtc, &debugfs_status_fops);
1255 	debugfs_create_file("state", 0600,
1256 			dpu_crtc->debugfs_root,
1257 			&dpu_crtc->base,
1258 			&dpu_crtc_debugfs_state_fops);
1259 
1260 	return 0;
1261 }
1262 #else
1263 static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc)
1264 {
1265 	return 0;
1266 }
1267 #endif /* CONFIG_DEBUG_FS */
1268 
1269 static int dpu_crtc_late_register(struct drm_crtc *crtc)
1270 {
1271 	return _dpu_crtc_init_debugfs(crtc);
1272 }
1273 
1274 static void dpu_crtc_early_unregister(struct drm_crtc *crtc)
1275 {
1276 	struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1277 
1278 	debugfs_remove_recursive(dpu_crtc->debugfs_root);
1279 }
1280 
1281 static const struct drm_crtc_funcs dpu_crtc_funcs = {
1282 	.set_config = drm_atomic_helper_set_config,
1283 	.destroy = dpu_crtc_destroy,
1284 	.page_flip = drm_atomic_helper_page_flip,
1285 	.reset = dpu_crtc_reset,
1286 	.atomic_duplicate_state = dpu_crtc_duplicate_state,
1287 	.atomic_destroy_state = dpu_crtc_destroy_state,
1288 	.late_register = dpu_crtc_late_register,
1289 	.early_unregister = dpu_crtc_early_unregister,
1290 };
1291 
1292 static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = {
1293 	.atomic_disable = dpu_crtc_disable,
1294 	.atomic_enable = dpu_crtc_enable,
1295 	.atomic_check = dpu_crtc_atomic_check,
1296 	.atomic_begin = dpu_crtc_atomic_begin,
1297 	.atomic_flush = dpu_crtc_atomic_flush,
1298 };
1299 
1300 /* initialize crtc */
1301 struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
1302 				struct drm_plane *cursor)
1303 {
1304 	struct drm_crtc *crtc = NULL;
1305 	struct dpu_crtc *dpu_crtc = NULL;
1306 	struct msm_drm_private *priv = NULL;
1307 	struct dpu_kms *kms = NULL;
1308 	int i;
1309 
1310 	priv = dev->dev_private;
1311 	kms = to_dpu_kms(priv->kms);
1312 
1313 	dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL);
1314 	if (!dpu_crtc)
1315 		return ERR_PTR(-ENOMEM);
1316 
1317 	crtc = &dpu_crtc->base;
1318 	crtc->dev = dev;
1319 
1320 	spin_lock_init(&dpu_crtc->spin_lock);
1321 	atomic_set(&dpu_crtc->frame_pending, 0);
1322 
1323 	init_completion(&dpu_crtc->frame_done_comp);
1324 
1325 	INIT_LIST_HEAD(&dpu_crtc->frame_event_list);
1326 
1327 	for (i = 0; i < ARRAY_SIZE(dpu_crtc->frame_events); i++) {
1328 		INIT_LIST_HEAD(&dpu_crtc->frame_events[i].list);
1329 		list_add(&dpu_crtc->frame_events[i].list,
1330 				&dpu_crtc->frame_event_list);
1331 		kthread_init_work(&dpu_crtc->frame_events[i].work,
1332 				dpu_crtc_frame_event_work);
1333 	}
1334 
1335 	drm_crtc_init_with_planes(dev, crtc, plane, cursor, &dpu_crtc_funcs,
1336 				NULL);
1337 
1338 	drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
1339 
1340 	/* save user friendly CRTC name for later */
1341 	snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
1342 
1343 	/* initialize event handling */
1344 	spin_lock_init(&dpu_crtc->event_lock);
1345 
1346 	DPU_DEBUG("%s: successfully initialized crtc\n", dpu_crtc->name);
1347 	return crtc;
1348 }
1349