1caab277bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 225fdd593SJeykumar Sankaran /* 325fdd593SJeykumar Sankaran * Copyright (c) 2014-2018 The Linux Foundation. All rights reserved. 425fdd593SJeykumar Sankaran * Copyright (C) 2013 Red Hat 525fdd593SJeykumar Sankaran * Author: Rob Clark <robdclark@gmail.com> 625fdd593SJeykumar Sankaran */ 725fdd593SJeykumar Sankaran 825fdd593SJeykumar Sankaran #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 925fdd593SJeykumar Sankaran #include <linux/sort.h> 1025fdd593SJeykumar Sankaran #include <linux/debugfs.h> 1125fdd593SJeykumar Sankaran #include <linux/ktime.h> 1225fdd593SJeykumar Sankaran #include <drm/drm_crtc.h> 1325fdd593SJeykumar Sankaran #include <drm/drm_flip_work.h> 14fcd70cd3SDaniel Vetter #include <drm/drm_mode.h> 15fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h> 1625fdd593SJeykumar Sankaran #include <drm/drm_rect.h> 1725fdd593SJeykumar Sankaran 1825fdd593SJeykumar Sankaran #include "dpu_kms.h" 1925fdd593SJeykumar Sankaran #include "dpu_hw_lm.h" 2025fdd593SJeykumar Sankaran #include "dpu_hw_ctl.h" 2125fdd593SJeykumar Sankaran #include "dpu_crtc.h" 2225fdd593SJeykumar Sankaran #include "dpu_plane.h" 2325fdd593SJeykumar Sankaran #include "dpu_encoder.h" 2425fdd593SJeykumar Sankaran #include "dpu_vbif.h" 2525fdd593SJeykumar Sankaran #include "dpu_core_perf.h" 2625fdd593SJeykumar Sankaran #include "dpu_trace.h" 2725fdd593SJeykumar Sankaran 2825fdd593SJeykumar Sankaran #define DPU_DRM_BLEND_OP_NOT_DEFINED 0 2925fdd593SJeykumar Sankaran #define DPU_DRM_BLEND_OP_OPAQUE 1 3025fdd593SJeykumar Sankaran #define DPU_DRM_BLEND_OP_PREMULTIPLIED 2 3125fdd593SJeykumar Sankaran #define DPU_DRM_BLEND_OP_COVERAGE 3 3225fdd593SJeykumar Sankaran #define DPU_DRM_BLEND_OP_MAX 4 3325fdd593SJeykumar Sankaran 3425fdd593SJeykumar Sankaran /* layer mixer index on dpu_crtc */ 3525fdd593SJeykumar Sankaran #define LEFT_MIXER 0 3625fdd593SJeykumar Sankaran #define RIGHT_MIXER 1 3725fdd593SJeykumar Sankaran 3870df9610SSean Paul /* timeout in ms waiting for frame done */ 3970df9610SSean Paul #define DPU_CRTC_FRAME_DONE_TIMEOUT_MS 60 4070df9610SSean Paul 4158fba464SSean Paul static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc) 4225fdd593SJeykumar Sankaran { 4304b96b63SBruce Wang struct msm_drm_private *priv = crtc->dev->dev_private; 4425fdd593SJeykumar Sankaran 4525fdd593SJeykumar Sankaran return to_dpu_kms(priv->kms); 4625fdd593SJeykumar Sankaran } 4725fdd593SJeykumar Sankaran 4825fdd593SJeykumar Sankaran static void dpu_crtc_destroy(struct drm_crtc *crtc) 4925fdd593SJeykumar Sankaran { 5025fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 5125fdd593SJeykumar Sankaran 5225fdd593SJeykumar Sankaran DPU_DEBUG("\n"); 5325fdd593SJeykumar Sankaran 5425fdd593SJeykumar Sankaran if (!crtc) 5525fdd593SJeykumar Sankaran return; 5625fdd593SJeykumar Sankaran 5725fdd593SJeykumar Sankaran drm_crtc_cleanup(crtc); 5825fdd593SJeykumar Sankaran kfree(dpu_crtc); 5925fdd593SJeykumar Sankaran } 6025fdd593SJeykumar Sankaran 6125fdd593SJeykumar Sankaran static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, 6274593a28SSravanthi Kollukuduru struct dpu_plane_state *pstate, struct dpu_format *format) 6325fdd593SJeykumar Sankaran { 6425fdd593SJeykumar Sankaran struct dpu_hw_mixer *lm = mixer->hw_lm; 6574593a28SSravanthi Kollukuduru uint32_t blend_op; 6674593a28SSravanthi Kollukuduru struct drm_format_name_buf format_name; 6725fdd593SJeykumar Sankaran 6825fdd593SJeykumar Sankaran /* default to opaque blending */ 6974593a28SSravanthi Kollukuduru blend_op = DPU_BLEND_FG_ALPHA_FG_CONST | 7074593a28SSravanthi Kollukuduru DPU_BLEND_BG_ALPHA_BG_CONST; 7174593a28SSravanthi Kollukuduru 7274593a28SSravanthi Kollukuduru if (format->alpha_enable) { 7374593a28SSravanthi Kollukuduru /* coverage blending */ 7474593a28SSravanthi Kollukuduru blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL | 7574593a28SSravanthi Kollukuduru DPU_BLEND_BG_ALPHA_FG_PIXEL | 7674593a28SSravanthi Kollukuduru DPU_BLEND_BG_INV_ALPHA; 7774593a28SSravanthi Kollukuduru } 7874593a28SSravanthi Kollukuduru 7974593a28SSravanthi Kollukuduru lm->ops.setup_blend_config(lm, pstate->stage, 8074593a28SSravanthi Kollukuduru 0xFF, 0, blend_op); 8174593a28SSravanthi Kollukuduru 8274593a28SSravanthi Kollukuduru DPU_DEBUG("format:%s, alpha_en:%u blend_op:0x%x\n", 8374593a28SSravanthi Kollukuduru drm_get_format_name(format->base.pixel_format, &format_name), 8474593a28SSravanthi Kollukuduru format->alpha_enable, blend_op); 8525fdd593SJeykumar Sankaran } 8625fdd593SJeykumar Sankaran 8725fdd593SJeykumar Sankaran static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) 8825fdd593SJeykumar Sankaran { 8925fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 9025fdd593SJeykumar Sankaran struct dpu_crtc_state *crtc_state; 9125fdd593SJeykumar Sankaran int lm_idx, lm_horiz_position; 9225fdd593SJeykumar Sankaran 9325fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 9425fdd593SJeykumar Sankaran crtc_state = to_dpu_crtc_state(crtc->state); 9525fdd593SJeykumar Sankaran 9625fdd593SJeykumar Sankaran lm_horiz_position = 0; 979222cdd2SJeykumar Sankaran for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) { 9825fdd593SJeykumar Sankaran const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx]; 999222cdd2SJeykumar Sankaran struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm; 10025fdd593SJeykumar Sankaran struct dpu_hw_mixer_cfg cfg; 10125fdd593SJeykumar Sankaran 10225fdd593SJeykumar Sankaran if (!lm_roi || !drm_rect_visible(lm_roi)) 10325fdd593SJeykumar Sankaran continue; 10425fdd593SJeykumar Sankaran 10525fdd593SJeykumar Sankaran cfg.out_width = drm_rect_width(lm_roi); 10625fdd593SJeykumar Sankaran cfg.out_height = drm_rect_height(lm_roi); 10725fdd593SJeykumar Sankaran cfg.right_mixer = lm_horiz_position++; 10825fdd593SJeykumar Sankaran cfg.flags = 0; 10925fdd593SJeykumar Sankaran hw_lm->ops.setup_mixer_out(hw_lm, &cfg); 11025fdd593SJeykumar Sankaran } 11125fdd593SJeykumar Sankaran } 11225fdd593SJeykumar Sankaran 11325fdd593SJeykumar Sankaran static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, 11425fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer) 11525fdd593SJeykumar Sankaran { 11625fdd593SJeykumar Sankaran struct drm_plane *plane; 11725fdd593SJeykumar Sankaran struct drm_framebuffer *fb; 11825fdd593SJeykumar Sankaran struct drm_plane_state *state; 11904b96b63SBruce Wang struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 12025fdd593SJeykumar Sankaran struct dpu_plane_state *pstate = NULL; 12125fdd593SJeykumar Sankaran struct dpu_format *format; 12204b96b63SBruce Wang struct dpu_hw_ctl *ctl = mixer->lm_ctl; 12304b96b63SBruce Wang struct dpu_hw_stage_cfg *stage_cfg = &dpu_crtc->stage_cfg; 12425fdd593SJeykumar Sankaran 12525fdd593SJeykumar Sankaran u32 flush_mask; 12625fdd593SJeykumar Sankaran uint32_t stage_idx, lm_idx; 12725fdd593SJeykumar Sankaran int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 }; 12825fdd593SJeykumar Sankaran bool bg_alpha_enable = false; 12925fdd593SJeykumar Sankaran 13025fdd593SJeykumar Sankaran drm_atomic_crtc_for_each_plane(plane, crtc) { 13125fdd593SJeykumar Sankaran state = plane->state; 13225fdd593SJeykumar Sankaran if (!state) 13325fdd593SJeykumar Sankaran continue; 13425fdd593SJeykumar Sankaran 13525fdd593SJeykumar Sankaran pstate = to_dpu_plane_state(state); 13625fdd593SJeykumar Sankaran fb = state->fb; 13725fdd593SJeykumar Sankaran 13825fdd593SJeykumar Sankaran dpu_plane_get_ctl_flush(plane, ctl, &flush_mask); 13925fdd593SJeykumar Sankaran 14025fdd593SJeykumar Sankaran DPU_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n", 14125fdd593SJeykumar Sankaran crtc->base.id, 14225fdd593SJeykumar Sankaran pstate->stage, 14325fdd593SJeykumar Sankaran plane->base.id, 14425fdd593SJeykumar Sankaran dpu_plane_pipe(plane) - SSPP_VIG0, 14525fdd593SJeykumar Sankaran state->fb ? state->fb->base.id : -1); 14625fdd593SJeykumar Sankaran 14725fdd593SJeykumar Sankaran format = to_dpu_format(msm_framebuffer_format(pstate->base.fb)); 14825fdd593SJeykumar Sankaran 14925fdd593SJeykumar Sankaran if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) 15025fdd593SJeykumar Sankaran bg_alpha_enable = true; 15125fdd593SJeykumar Sankaran 15225fdd593SJeykumar Sankaran stage_idx = zpos_cnt[pstate->stage]++; 15325fdd593SJeykumar Sankaran stage_cfg->stage[pstate->stage][stage_idx] = 15425fdd593SJeykumar Sankaran dpu_plane_pipe(plane); 15525fdd593SJeykumar Sankaran stage_cfg->multirect_index[pstate->stage][stage_idx] = 15625fdd593SJeykumar Sankaran pstate->multirect_index; 15725fdd593SJeykumar Sankaran 15825fdd593SJeykumar Sankaran trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), 15925fdd593SJeykumar Sankaran state, pstate, stage_idx, 16025fdd593SJeykumar Sankaran dpu_plane_pipe(plane) - SSPP_VIG0, 16125fdd593SJeykumar Sankaran format->base.pixel_format, 16225fdd593SJeykumar Sankaran fb ? fb->modifier : 0); 16325fdd593SJeykumar Sankaran 16425fdd593SJeykumar Sankaran /* blend config update */ 1659222cdd2SJeykumar Sankaran for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) { 16674593a28SSravanthi Kollukuduru _dpu_crtc_setup_blend_cfg(mixer + lm_idx, 16774593a28SSravanthi Kollukuduru pstate, format); 16825fdd593SJeykumar Sankaran 16925fdd593SJeykumar Sankaran mixer[lm_idx].flush_mask |= flush_mask; 17025fdd593SJeykumar Sankaran 17125fdd593SJeykumar Sankaran if (bg_alpha_enable && !format->alpha_enable) 17225fdd593SJeykumar Sankaran mixer[lm_idx].mixer_op_mode = 0; 17325fdd593SJeykumar Sankaran else 17425fdd593SJeykumar Sankaran mixer[lm_idx].mixer_op_mode |= 17525fdd593SJeykumar Sankaran 1 << pstate->stage; 17625fdd593SJeykumar Sankaran } 17725fdd593SJeykumar Sankaran } 17825fdd593SJeykumar Sankaran 17925fdd593SJeykumar Sankaran _dpu_crtc_program_lm_output_roi(crtc); 18025fdd593SJeykumar Sankaran } 18125fdd593SJeykumar Sankaran 18225fdd593SJeykumar Sankaran /** 18325fdd593SJeykumar Sankaran * _dpu_crtc_blend_setup - configure crtc mixers 18425fdd593SJeykumar Sankaran * @crtc: Pointer to drm crtc structure 18525fdd593SJeykumar Sankaran */ 18625fdd593SJeykumar Sankaran static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) 18725fdd593SJeykumar Sankaran { 18804b96b63SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 18904b96b63SBruce Wang struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 19004b96b63SBruce Wang struct dpu_crtc_mixer *mixer = cstate->mixers; 19125fdd593SJeykumar Sankaran struct dpu_hw_ctl *ctl; 19225fdd593SJeykumar Sankaran struct dpu_hw_mixer *lm; 19325fdd593SJeykumar Sankaran int i; 19425fdd593SJeykumar Sankaran 19525fdd593SJeykumar Sankaran DPU_DEBUG("%s\n", dpu_crtc->name); 19625fdd593SJeykumar Sankaran 1979222cdd2SJeykumar Sankaran for (i = 0; i < cstate->num_mixers; i++) { 198cf6916f4SJeykumar Sankaran if (!mixer[i].hw_lm || !mixer[i].lm_ctl) { 19925fdd593SJeykumar Sankaran DPU_ERROR("invalid lm or ctl assigned to mixer\n"); 20025fdd593SJeykumar Sankaran return; 20125fdd593SJeykumar Sankaran } 20225fdd593SJeykumar Sankaran mixer[i].mixer_op_mode = 0; 20325fdd593SJeykumar Sankaran mixer[i].flush_mask = 0; 204cf6916f4SJeykumar Sankaran if (mixer[i].lm_ctl->ops.clear_all_blendstages) 205cf6916f4SJeykumar Sankaran mixer[i].lm_ctl->ops.clear_all_blendstages( 206cf6916f4SJeykumar Sankaran mixer[i].lm_ctl); 20725fdd593SJeykumar Sankaran } 20825fdd593SJeykumar Sankaran 20925fdd593SJeykumar Sankaran /* initialize stage cfg */ 21025fdd593SJeykumar Sankaran memset(&dpu_crtc->stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg)); 21125fdd593SJeykumar Sankaran 21225fdd593SJeykumar Sankaran _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer); 21325fdd593SJeykumar Sankaran 2149222cdd2SJeykumar Sankaran for (i = 0; i < cstate->num_mixers; i++) { 215cf6916f4SJeykumar Sankaran ctl = mixer[i].lm_ctl; 21625fdd593SJeykumar Sankaran lm = mixer[i].hw_lm; 21725fdd593SJeykumar Sankaran 21825fdd593SJeykumar Sankaran lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode); 21925fdd593SJeykumar Sankaran 22025fdd593SJeykumar Sankaran mixer[i].flush_mask |= ctl->ops.get_bitmask_mixer(ctl, 22125fdd593SJeykumar Sankaran mixer[i].hw_lm->idx); 22225fdd593SJeykumar Sankaran 22325fdd593SJeykumar Sankaran /* stage config flush mask */ 22425fdd593SJeykumar Sankaran ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); 22525fdd593SJeykumar Sankaran 22625fdd593SJeykumar Sankaran DPU_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n", 22725fdd593SJeykumar Sankaran mixer[i].hw_lm->idx - LM_0, 22825fdd593SJeykumar Sankaran mixer[i].mixer_op_mode, 22925fdd593SJeykumar Sankaran ctl->idx - CTL_0, 23025fdd593SJeykumar Sankaran mixer[i].flush_mask); 23125fdd593SJeykumar Sankaran 23225fdd593SJeykumar Sankaran ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, 23325fdd593SJeykumar Sankaran &dpu_crtc->stage_cfg); 23425fdd593SJeykumar Sankaran } 23525fdd593SJeykumar Sankaran } 23625fdd593SJeykumar Sankaran 23725fdd593SJeykumar Sankaran /** 23825fdd593SJeykumar Sankaran * _dpu_crtc_complete_flip - signal pending page_flip events 23925fdd593SJeykumar Sankaran * Any pending vblank events are added to the vblank_event_list 24025fdd593SJeykumar Sankaran * so that the next vblank interrupt shall signal them. 24125fdd593SJeykumar Sankaran * However PAGE_FLIP events are not handled through the vblank_event_list. 24225fdd593SJeykumar Sankaran * This API signals any pending PAGE_FLIP events requested through 24325fdd593SJeykumar Sankaran * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the dpu_crtc->event. 24425fdd593SJeykumar Sankaran * @crtc: Pointer to drm crtc structure 24525fdd593SJeykumar Sankaran */ 24625fdd593SJeykumar Sankaran static void _dpu_crtc_complete_flip(struct drm_crtc *crtc) 24725fdd593SJeykumar Sankaran { 24825fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 24925fdd593SJeykumar Sankaran struct drm_device *dev = crtc->dev; 25025fdd593SJeykumar Sankaran unsigned long flags; 25125fdd593SJeykumar Sankaran 25225fdd593SJeykumar Sankaran spin_lock_irqsave(&dev->event_lock, flags); 25325fdd593SJeykumar Sankaran if (dpu_crtc->event) { 25425fdd593SJeykumar Sankaran DRM_DEBUG_VBL("%s: send event: %pK\n", dpu_crtc->name, 25525fdd593SJeykumar Sankaran dpu_crtc->event); 25625fdd593SJeykumar Sankaran trace_dpu_crtc_complete_flip(DRMID(crtc)); 25725fdd593SJeykumar Sankaran drm_crtc_send_vblank_event(crtc, dpu_crtc->event); 25825fdd593SJeykumar Sankaran dpu_crtc->event = NULL; 25925fdd593SJeykumar Sankaran } 26025fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dev->event_lock, flags); 26125fdd593SJeykumar Sankaran } 26225fdd593SJeykumar Sankaran 26325fdd593SJeykumar Sankaran enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc) 26425fdd593SJeykumar Sankaran { 26525fdd593SJeykumar Sankaran struct drm_encoder *encoder; 26625fdd593SJeykumar Sankaran 26725fdd593SJeykumar Sankaran if (!crtc || !crtc->dev) { 26825fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 26925fdd593SJeykumar Sankaran return INTF_MODE_NONE; 27025fdd593SJeykumar Sankaran } 27125fdd593SJeykumar Sankaran 2721dfdb0e1SSean Paul WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); 2731dfdb0e1SSean Paul 2744b8c6279SSean Paul /* TODO: Returns the first INTF_MODE, could there be multiple values? */ 2754b8c6279SSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) 27625fdd593SJeykumar Sankaran return dpu_encoder_get_intf_mode(encoder); 27725fdd593SJeykumar Sankaran 27825fdd593SJeykumar Sankaran return INTF_MODE_NONE; 27925fdd593SJeykumar Sankaran } 28025fdd593SJeykumar Sankaran 281e4914867SSean Paul void dpu_crtc_vblank_callback(struct drm_crtc *crtc) 28225fdd593SJeykumar Sankaran { 28325fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 28425fdd593SJeykumar Sankaran 28525fdd593SJeykumar Sankaran /* keep statistics on vblank callback - with auto reset via debugfs */ 28625fdd593SJeykumar Sankaran if (ktime_compare(dpu_crtc->vblank_cb_time, ktime_set(0, 0)) == 0) 28725fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_time = ktime_get(); 28825fdd593SJeykumar Sankaran else 28925fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_count++; 29025fdd593SJeykumar Sankaran _dpu_crtc_complete_flip(crtc); 29125fdd593SJeykumar Sankaran drm_crtc_handle_vblank(crtc); 29225fdd593SJeykumar Sankaran trace_dpu_crtc_vblank_cb(DRMID(crtc)); 29325fdd593SJeykumar Sankaran } 29425fdd593SJeykumar Sankaran 295f449aa6eSSean Paul static void dpu_crtc_release_bw_unlocked(struct drm_crtc *crtc) 296f449aa6eSSean Paul { 297f449aa6eSSean Paul int ret = 0; 298f449aa6eSSean Paul struct drm_modeset_acquire_ctx ctx; 299f449aa6eSSean Paul 300f449aa6eSSean Paul DRM_MODESET_LOCK_ALL_BEGIN(crtc->dev, ctx, 0, ret); 301f449aa6eSSean Paul dpu_core_perf_crtc_release_bw(crtc); 302f449aa6eSSean Paul DRM_MODESET_LOCK_ALL_END(ctx, ret); 303f449aa6eSSean Paul if (ret) 304f449aa6eSSean Paul DRM_ERROR("Failed to acquire modeset locks to release bw, %d\n", 305f449aa6eSSean Paul ret); 306f449aa6eSSean Paul } 307f449aa6eSSean Paul 30825fdd593SJeykumar Sankaran static void dpu_crtc_frame_event_work(struct kthread_work *work) 30925fdd593SJeykumar Sankaran { 31004b96b63SBruce Wang struct dpu_crtc_frame_event *fevent = container_of(work, 31104b96b63SBruce Wang struct dpu_crtc_frame_event, work); 31204b96b63SBruce Wang struct drm_crtc *crtc = fevent->crtc; 31304b96b63SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 31425fdd593SJeykumar Sankaran unsigned long flags; 31525fdd593SJeykumar Sankaran bool frame_done = false; 31625fdd593SJeykumar Sankaran 31725fdd593SJeykumar Sankaran DPU_ATRACE_BEGIN("crtc_frame_event"); 31825fdd593SJeykumar Sankaran 31925fdd593SJeykumar Sankaran DRM_DEBUG_KMS("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event, 32025fdd593SJeykumar Sankaran ktime_to_ns(fevent->ts)); 32125fdd593SJeykumar Sankaran 32225fdd593SJeykumar Sankaran if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE 32325fdd593SJeykumar Sankaran | DPU_ENCODER_FRAME_EVENT_ERROR 32425fdd593SJeykumar Sankaran | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) { 32525fdd593SJeykumar Sankaran 32625fdd593SJeykumar Sankaran if (atomic_read(&dpu_crtc->frame_pending) < 1) { 32725fdd593SJeykumar Sankaran /* this should not happen */ 32825fdd593SJeykumar Sankaran DRM_ERROR("crtc%d ev:%u ts:%lld frame_pending:%d\n", 32925fdd593SJeykumar Sankaran crtc->base.id, 33025fdd593SJeykumar Sankaran fevent->event, 33125fdd593SJeykumar Sankaran ktime_to_ns(fevent->ts), 33225fdd593SJeykumar Sankaran atomic_read(&dpu_crtc->frame_pending)); 33325fdd593SJeykumar Sankaran } else if (atomic_dec_return(&dpu_crtc->frame_pending) == 0) { 33425fdd593SJeykumar Sankaran /* release bandwidth and other resources */ 33525fdd593SJeykumar Sankaran trace_dpu_crtc_frame_event_done(DRMID(crtc), 33625fdd593SJeykumar Sankaran fevent->event); 337f449aa6eSSean Paul dpu_crtc_release_bw_unlocked(crtc); 33825fdd593SJeykumar Sankaran } else { 33925fdd593SJeykumar Sankaran trace_dpu_crtc_frame_event_more_pending(DRMID(crtc), 34025fdd593SJeykumar Sankaran fevent->event); 34125fdd593SJeykumar Sankaran } 34225fdd593SJeykumar Sankaran 34325fdd593SJeykumar Sankaran if (fevent->event & DPU_ENCODER_FRAME_EVENT_DONE) 34425fdd593SJeykumar Sankaran dpu_core_perf_crtc_update(crtc, 0, false); 34525fdd593SJeykumar Sankaran 34625fdd593SJeykumar Sankaran if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE 34725fdd593SJeykumar Sankaran | DPU_ENCODER_FRAME_EVENT_ERROR)) 34825fdd593SJeykumar Sankaran frame_done = true; 34925fdd593SJeykumar Sankaran } 35025fdd593SJeykumar Sankaran 35125fdd593SJeykumar Sankaran if (fevent->event & DPU_ENCODER_FRAME_EVENT_PANEL_DEAD) 35225fdd593SJeykumar Sankaran DPU_ERROR("crtc%d ts:%lld received panel dead event\n", 35325fdd593SJeykumar Sankaran crtc->base.id, ktime_to_ns(fevent->ts)); 35425fdd593SJeykumar Sankaran 35525fdd593SJeykumar Sankaran if (frame_done) 35625fdd593SJeykumar Sankaran complete_all(&dpu_crtc->frame_done_comp); 35725fdd593SJeykumar Sankaran 35825fdd593SJeykumar Sankaran spin_lock_irqsave(&dpu_crtc->spin_lock, flags); 35925fdd593SJeykumar Sankaran list_add_tail(&fevent->list, &dpu_crtc->frame_event_list); 36025fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags); 36125fdd593SJeykumar Sankaran DPU_ATRACE_END("crtc_frame_event"); 36225fdd593SJeykumar Sankaran } 36325fdd593SJeykumar Sankaran 36425fdd593SJeykumar Sankaran /* 36525fdd593SJeykumar Sankaran * dpu_crtc_frame_event_cb - crtc frame event callback API. CRTC module 36625fdd593SJeykumar Sankaran * registers this API to encoder for all frame event callbacks like 36725fdd593SJeykumar Sankaran * frame_error, frame_done, idle_timeout, etc. Encoder may call different events 36825fdd593SJeykumar Sankaran * from different context - IRQ, user thread, commit_thread, etc. Each event 36925fdd593SJeykumar Sankaran * should be carefully reviewed and should be processed in proper task context 37025fdd593SJeykumar Sankaran * to avoid schedulin delay or properly manage the irq context's bottom half 37125fdd593SJeykumar Sankaran * processing. 37225fdd593SJeykumar Sankaran */ 37325fdd593SJeykumar Sankaran static void dpu_crtc_frame_event_cb(void *data, u32 event) 37425fdd593SJeykumar Sankaran { 37525fdd593SJeykumar Sankaran struct drm_crtc *crtc = (struct drm_crtc *)data; 37625fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 37725fdd593SJeykumar Sankaran struct msm_drm_private *priv; 37825fdd593SJeykumar Sankaran struct dpu_crtc_frame_event *fevent; 37925fdd593SJeykumar Sankaran unsigned long flags; 38025fdd593SJeykumar Sankaran u32 crtc_id; 38125fdd593SJeykumar Sankaran 38225fdd593SJeykumar Sankaran /* Nothing to do on idle event */ 38325fdd593SJeykumar Sankaran if (event & DPU_ENCODER_FRAME_EVENT_IDLE) 38425fdd593SJeykumar Sankaran return; 38525fdd593SJeykumar Sankaran 38625fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 38725fdd593SJeykumar Sankaran priv = crtc->dev->dev_private; 38825fdd593SJeykumar Sankaran crtc_id = drm_crtc_index(crtc); 38925fdd593SJeykumar Sankaran 39025fdd593SJeykumar Sankaran trace_dpu_crtc_frame_event_cb(DRMID(crtc), event); 39125fdd593SJeykumar Sankaran 39225fdd593SJeykumar Sankaran spin_lock_irqsave(&dpu_crtc->spin_lock, flags); 39325fdd593SJeykumar Sankaran fevent = list_first_entry_or_null(&dpu_crtc->frame_event_list, 39425fdd593SJeykumar Sankaran struct dpu_crtc_frame_event, list); 39525fdd593SJeykumar Sankaran if (fevent) 39625fdd593SJeykumar Sankaran list_del_init(&fevent->list); 39725fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags); 39825fdd593SJeykumar Sankaran 39925fdd593SJeykumar Sankaran if (!fevent) { 40025fdd593SJeykumar Sankaran DRM_ERROR("crtc%d event %d overflow\n", crtc->base.id, event); 40125fdd593SJeykumar Sankaran return; 40225fdd593SJeykumar Sankaran } 40325fdd593SJeykumar Sankaran 40425fdd593SJeykumar Sankaran fevent->event = event; 40525fdd593SJeykumar Sankaran fevent->crtc = crtc; 40625fdd593SJeykumar Sankaran fevent->ts = ktime_get(); 40725fdd593SJeykumar Sankaran kthread_queue_work(&priv->event_thread[crtc_id].worker, &fevent->work); 40825fdd593SJeykumar Sankaran } 40925fdd593SJeykumar Sankaran 41025fdd593SJeykumar Sankaran void dpu_crtc_complete_commit(struct drm_crtc *crtc, 41125fdd593SJeykumar Sankaran struct drm_crtc_state *old_state) 41225fdd593SJeykumar Sankaran { 41325fdd593SJeykumar Sankaran if (!crtc || !crtc->state) { 41425fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 41525fdd593SJeykumar Sankaran return; 41625fdd593SJeykumar Sankaran } 41725fdd593SJeykumar Sankaran trace_dpu_crtc_complete_commit(DRMID(crtc)); 41825fdd593SJeykumar Sankaran } 41925fdd593SJeykumar Sankaran 42025fdd593SJeykumar Sankaran static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc, 42125fdd593SJeykumar Sankaran struct drm_crtc_state *state) 42225fdd593SJeykumar Sankaran { 42304b96b63SBruce Wang struct dpu_crtc_state *cstate = to_dpu_crtc_state(state); 42404b96b63SBruce Wang struct drm_display_mode *adj_mode = &state->adjusted_mode; 4253804a982SJordan Crouse u32 crtc_split_width = adj_mode->hdisplay / cstate->num_mixers; 42625fdd593SJeykumar Sankaran int i; 42725fdd593SJeykumar Sankaran 4289222cdd2SJeykumar Sankaran for (i = 0; i < cstate->num_mixers; i++) { 42925fdd593SJeykumar Sankaran struct drm_rect *r = &cstate->lm_bounds[i]; 43025fdd593SJeykumar Sankaran r->x1 = crtc_split_width * i; 43125fdd593SJeykumar Sankaran r->y1 = 0; 43225fdd593SJeykumar Sankaran r->x2 = r->x1 + crtc_split_width; 43335d600ddSJordan Crouse r->y2 = adj_mode->vdisplay; 43425fdd593SJeykumar Sankaran 43525fdd593SJeykumar Sankaran trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i, r); 43625fdd593SJeykumar Sankaran } 43725fdd593SJeykumar Sankaran 43825fdd593SJeykumar Sankaran drm_mode_debug_printmodeline(adj_mode); 43925fdd593SJeykumar Sankaran } 44025fdd593SJeykumar Sankaran 44125fdd593SJeykumar Sankaran static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, 44225fdd593SJeykumar Sankaran struct drm_crtc_state *old_state) 44325fdd593SJeykumar Sankaran { 44425fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 4459222cdd2SJeykumar Sankaran struct dpu_crtc_state *cstate; 44625fdd593SJeykumar Sankaran struct drm_encoder *encoder; 44725fdd593SJeykumar Sankaran struct drm_device *dev; 44825fdd593SJeykumar Sankaran unsigned long flags; 44925fdd593SJeykumar Sankaran struct dpu_crtc_smmu_state_data *smmu_state; 45025fdd593SJeykumar Sankaran 45125fdd593SJeykumar Sankaran if (!crtc) { 45225fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 45325fdd593SJeykumar Sankaran return; 45425fdd593SJeykumar Sankaran } 45525fdd593SJeykumar Sankaran 45625fdd593SJeykumar Sankaran if (!crtc->state->enable) { 45725fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d -> enable %d, skip atomic_begin\n", 45825fdd593SJeykumar Sankaran crtc->base.id, crtc->state->enable); 45925fdd593SJeykumar Sankaran return; 46025fdd593SJeykumar Sankaran } 46125fdd593SJeykumar Sankaran 46225fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d\n", crtc->base.id); 46325fdd593SJeykumar Sankaran 46425fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 4659222cdd2SJeykumar Sankaran cstate = to_dpu_crtc_state(crtc->state); 46625fdd593SJeykumar Sankaran dev = crtc->dev; 46725fdd593SJeykumar Sankaran smmu_state = &dpu_crtc->smmu_state; 46825fdd593SJeykumar Sankaran 46925fdd593SJeykumar Sankaran _dpu_crtc_setup_lm_bounds(crtc, crtc->state); 47025fdd593SJeykumar Sankaran 47125fdd593SJeykumar Sankaran if (dpu_crtc->event) { 47225fdd593SJeykumar Sankaran WARN_ON(dpu_crtc->event); 47325fdd593SJeykumar Sankaran } else { 47425fdd593SJeykumar Sankaran spin_lock_irqsave(&dev->event_lock, flags); 47525fdd593SJeykumar Sankaran dpu_crtc->event = crtc->state->event; 47625fdd593SJeykumar Sankaran crtc->state->event = NULL; 47725fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dev->event_lock, flags); 47825fdd593SJeykumar Sankaran } 47925fdd593SJeykumar Sankaran 48025fdd593SJeykumar Sankaran /* encoder will trigger pending mask now */ 4814b8c6279SSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) 48225fdd593SJeykumar Sankaran dpu_encoder_trigger_kickoff_pending(encoder); 48325fdd593SJeykumar Sankaran 48425fdd593SJeykumar Sankaran /* 48525fdd593SJeykumar Sankaran * If no mixers have been allocated in dpu_crtc_atomic_check(), 48625fdd593SJeykumar Sankaran * it means we are trying to flush a CRTC whose state is disabled: 48725fdd593SJeykumar Sankaran * nothing else needs to be done. 48825fdd593SJeykumar Sankaran */ 4899222cdd2SJeykumar Sankaran if (unlikely(!cstate->num_mixers)) 49025fdd593SJeykumar Sankaran return; 49125fdd593SJeykumar Sankaran 49225fdd593SJeykumar Sankaran _dpu_crtc_blend_setup(crtc); 49325fdd593SJeykumar Sankaran 49425fdd593SJeykumar Sankaran /* 49525fdd593SJeykumar Sankaran * PP_DONE irq is only used by command mode for now. 49625fdd593SJeykumar Sankaran * It is better to request pending before FLUSH and START trigger 49725fdd593SJeykumar Sankaran * to make sure no pp_done irq missed. 49825fdd593SJeykumar Sankaran * This is safe because no pp_done will happen before SW trigger 49925fdd593SJeykumar Sankaran * in command mode. 50025fdd593SJeykumar Sankaran */ 50125fdd593SJeykumar Sankaran } 50225fdd593SJeykumar Sankaran 50325fdd593SJeykumar Sankaran static void dpu_crtc_atomic_flush(struct drm_crtc *crtc, 50425fdd593SJeykumar Sankaran struct drm_crtc_state *old_crtc_state) 50525fdd593SJeykumar Sankaran { 50625fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 50725fdd593SJeykumar Sankaran struct drm_device *dev; 50825fdd593SJeykumar Sankaran struct drm_plane *plane; 50925fdd593SJeykumar Sankaran struct msm_drm_private *priv; 51025fdd593SJeykumar Sankaran struct msm_drm_thread *event_thread; 51125fdd593SJeykumar Sankaran unsigned long flags; 51225fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 51325fdd593SJeykumar Sankaran 51425fdd593SJeykumar Sankaran if (!crtc->state->enable) { 51525fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d -> enable %d, skip atomic_flush\n", 51625fdd593SJeykumar Sankaran crtc->base.id, crtc->state->enable); 51725fdd593SJeykumar Sankaran return; 51825fdd593SJeykumar Sankaran } 51925fdd593SJeykumar Sankaran 52025fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d\n", crtc->base.id); 52125fdd593SJeykumar Sankaran 52225fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 52325fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(crtc->state); 52425fdd593SJeykumar Sankaran dev = crtc->dev; 52525fdd593SJeykumar Sankaran priv = dev->dev_private; 52625fdd593SJeykumar Sankaran 52725fdd593SJeykumar Sankaran if (crtc->index >= ARRAY_SIZE(priv->event_thread)) { 52825fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc index[%d]\n", crtc->index); 52925fdd593SJeykumar Sankaran return; 53025fdd593SJeykumar Sankaran } 53125fdd593SJeykumar Sankaran 53225fdd593SJeykumar Sankaran event_thread = &priv->event_thread[crtc->index]; 53325fdd593SJeykumar Sankaran 53425fdd593SJeykumar Sankaran if (dpu_crtc->event) { 53525fdd593SJeykumar Sankaran DPU_DEBUG("already received dpu_crtc->event\n"); 53625fdd593SJeykumar Sankaran } else { 53725fdd593SJeykumar Sankaran spin_lock_irqsave(&dev->event_lock, flags); 53825fdd593SJeykumar Sankaran dpu_crtc->event = crtc->state->event; 53925fdd593SJeykumar Sankaran crtc->state->event = NULL; 54025fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dev->event_lock, flags); 54125fdd593SJeykumar Sankaran } 54225fdd593SJeykumar Sankaran 54325fdd593SJeykumar Sankaran /* 54425fdd593SJeykumar Sankaran * If no mixers has been allocated in dpu_crtc_atomic_check(), 54525fdd593SJeykumar Sankaran * it means we are trying to flush a CRTC whose state is disabled: 54625fdd593SJeykumar Sankaran * nothing else needs to be done. 54725fdd593SJeykumar Sankaran */ 5489222cdd2SJeykumar Sankaran if (unlikely(!cstate->num_mixers)) 54925fdd593SJeykumar Sankaran return; 55025fdd593SJeykumar Sankaran 55125fdd593SJeykumar Sankaran /* 55225fdd593SJeykumar Sankaran * For planes without commit update, drm framework will not add 55325fdd593SJeykumar Sankaran * those planes to current state since hardware update is not 55425fdd593SJeykumar Sankaran * required. However, if those planes were power collapsed since 55525fdd593SJeykumar Sankaran * last commit cycle, driver has to restore the hardware state 55625fdd593SJeykumar Sankaran * of those planes explicitly here prior to plane flush. 55725fdd593SJeykumar Sankaran */ 55825fdd593SJeykumar Sankaran drm_atomic_crtc_for_each_plane(plane, crtc) 55925fdd593SJeykumar Sankaran dpu_plane_restore(plane); 56025fdd593SJeykumar Sankaran 56125fdd593SJeykumar Sankaran /* update performance setting before crtc kickoff */ 56225fdd593SJeykumar Sankaran dpu_core_perf_crtc_update(crtc, 1, false); 56325fdd593SJeykumar Sankaran 56425fdd593SJeykumar Sankaran /* 56525fdd593SJeykumar Sankaran * Final plane updates: Give each plane a chance to complete all 56625fdd593SJeykumar Sankaran * required writes/flushing before crtc's "flush 56725fdd593SJeykumar Sankaran * everything" call below. 56825fdd593SJeykumar Sankaran */ 56925fdd593SJeykumar Sankaran drm_atomic_crtc_for_each_plane(plane, crtc) { 57025fdd593SJeykumar Sankaran if (dpu_crtc->smmu_state.transition_error) 57125fdd593SJeykumar Sankaran dpu_plane_set_error(plane, true); 57225fdd593SJeykumar Sankaran dpu_plane_flush(plane); 57325fdd593SJeykumar Sankaran } 57425fdd593SJeykumar Sankaran 57525fdd593SJeykumar Sankaran /* Kickoff will be scheduled by outer layer */ 57625fdd593SJeykumar Sankaran } 57725fdd593SJeykumar Sankaran 57825fdd593SJeykumar Sankaran /** 57925fdd593SJeykumar Sankaran * dpu_crtc_destroy_state - state destroy hook 58025fdd593SJeykumar Sankaran * @crtc: drm CRTC 58125fdd593SJeykumar Sankaran * @state: CRTC state object to release 58225fdd593SJeykumar Sankaran */ 58325fdd593SJeykumar Sankaran static void dpu_crtc_destroy_state(struct drm_crtc *crtc, 58425fdd593SJeykumar Sankaran struct drm_crtc_state *state) 58525fdd593SJeykumar Sankaran { 58625fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 58725fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 58825fdd593SJeykumar Sankaran 58925fdd593SJeykumar Sankaran if (!crtc || !state) { 59025fdd593SJeykumar Sankaran DPU_ERROR("invalid argument(s)\n"); 59125fdd593SJeykumar Sankaran return; 59225fdd593SJeykumar Sankaran } 59325fdd593SJeykumar Sankaran 59425fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 59525fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(state); 59625fdd593SJeykumar Sankaran 59725fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d\n", crtc->base.id); 59825fdd593SJeykumar Sankaran 59925fdd593SJeykumar Sankaran __drm_atomic_helper_crtc_destroy_state(state); 60025fdd593SJeykumar Sankaran 60125fdd593SJeykumar Sankaran kfree(cstate); 60225fdd593SJeykumar Sankaran } 60325fdd593SJeykumar Sankaran 60425fdd593SJeykumar Sankaran static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc) 60525fdd593SJeykumar Sankaran { 60604b96b63SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 60725fdd593SJeykumar Sankaran int ret, rc = 0; 60825fdd593SJeykumar Sankaran 60925fdd593SJeykumar Sankaran if (!atomic_read(&dpu_crtc->frame_pending)) { 61025fdd593SJeykumar Sankaran DPU_DEBUG("no frames pending\n"); 61125fdd593SJeykumar Sankaran return 0; 61225fdd593SJeykumar Sankaran } 61325fdd593SJeykumar Sankaran 61425fdd593SJeykumar Sankaran DPU_ATRACE_BEGIN("frame done completion wait"); 61525fdd593SJeykumar Sankaran ret = wait_for_completion_timeout(&dpu_crtc->frame_done_comp, 61670df9610SSean Paul msecs_to_jiffies(DPU_CRTC_FRAME_DONE_TIMEOUT_MS)); 61725fdd593SJeykumar Sankaran if (!ret) { 61825fdd593SJeykumar Sankaran DRM_ERROR("frame done wait timed out, ret:%d\n", ret); 61925fdd593SJeykumar Sankaran rc = -ETIMEDOUT; 62025fdd593SJeykumar Sankaran } 62125fdd593SJeykumar Sankaran DPU_ATRACE_END("frame done completion wait"); 62225fdd593SJeykumar Sankaran 62325fdd593SJeykumar Sankaran return rc; 62425fdd593SJeykumar Sankaran } 62525fdd593SJeykumar Sankaran 62650bcc689SSean Paul void dpu_crtc_commit_kickoff(struct drm_crtc *crtc, bool async) 62725fdd593SJeykumar Sankaran { 62825fdd593SJeykumar Sankaran struct drm_encoder *encoder; 62904b96b63SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 63004b96b63SBruce Wang struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); 63104b96b63SBruce Wang struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 63225fdd593SJeykumar Sankaran int ret; 63325fdd593SJeykumar Sankaran 63425fdd593SJeykumar Sankaran /* 63525fdd593SJeykumar Sankaran * If no mixers has been allocated in dpu_crtc_atomic_check(), 63625fdd593SJeykumar Sankaran * it means we are trying to start a CRTC whose state is disabled: 63725fdd593SJeykumar Sankaran * nothing else needs to be done. 63825fdd593SJeykumar Sankaran */ 6399222cdd2SJeykumar Sankaran if (unlikely(!cstate->num_mixers)) 64025fdd593SJeykumar Sankaran return; 64125fdd593SJeykumar Sankaran 64225fdd593SJeykumar Sankaran DPU_ATRACE_BEGIN("crtc_commit"); 64325fdd593SJeykumar Sankaran 64425fdd593SJeykumar Sankaran /* 6454b8c6279SSean Paul * Encoder will flush/start now, unless it has a tx pending. If so, it 6464b8c6279SSean Paul * may delay and flush at an irq event (e.g. ppdone) 64725fdd593SJeykumar Sankaran */ 6484b8c6279SSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, 649d3db61caSBruce Wang crtc->state->encoder_mask) 650d3db61caSBruce Wang dpu_encoder_prepare_for_kickoff(encoder, async); 65150bcc689SSean Paul 65250bcc689SSean Paul if (!async) { 65325fdd593SJeykumar Sankaran /* wait for frame_event_done completion */ 65425fdd593SJeykumar Sankaran DPU_ATRACE_BEGIN("wait_for_frame_done_event"); 65525fdd593SJeykumar Sankaran ret = _dpu_crtc_wait_for_frame_done(crtc); 65625fdd593SJeykumar Sankaran DPU_ATRACE_END("wait_for_frame_done_event"); 65725fdd593SJeykumar Sankaran if (ret) { 65825fdd593SJeykumar Sankaran DPU_ERROR("crtc%d wait for frame done failed;frame_pending%d\n", 65925fdd593SJeykumar Sankaran crtc->base.id, 66025fdd593SJeykumar Sankaran atomic_read(&dpu_crtc->frame_pending)); 66125fdd593SJeykumar Sankaran goto end; 66225fdd593SJeykumar Sankaran } 66325fdd593SJeykumar Sankaran 66425fdd593SJeykumar Sankaran if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) { 66525fdd593SJeykumar Sankaran /* acquire bandwidth and other resources */ 66625fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d first commit\n", crtc->base.id); 66725fdd593SJeykumar Sankaran } else 66825fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d commit\n", crtc->base.id); 66925fdd593SJeykumar Sankaran 67025fdd593SJeykumar Sankaran dpu_crtc->play_count++; 67150bcc689SSean Paul } 67225fdd593SJeykumar Sankaran 67325fdd593SJeykumar Sankaran dpu_vbif_clear_errors(dpu_kms); 67425fdd593SJeykumar Sankaran 6754b8c6279SSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) 67650bcc689SSean Paul dpu_encoder_kickoff(encoder, async); 67725fdd593SJeykumar Sankaran 67825fdd593SJeykumar Sankaran end: 67950bcc689SSean Paul if (!async) 68025fdd593SJeykumar Sankaran reinit_completion(&dpu_crtc->frame_done_comp); 68125fdd593SJeykumar Sankaran DPU_ATRACE_END("crtc_commit"); 68225fdd593SJeykumar Sankaran } 68325fdd593SJeykumar Sankaran 684ff5952a7SSean Paul static void dpu_crtc_reset(struct drm_crtc *crtc) 68525fdd593SJeykumar Sankaran { 686ff5952a7SSean Paul struct dpu_crtc_state *cstate; 68725fdd593SJeykumar Sankaran 688ff5952a7SSean Paul if (crtc->state) 689ff5952a7SSean Paul dpu_crtc_destroy_state(crtc, crtc->state); 69025fdd593SJeykumar Sankaran 691ff5952a7SSean Paul crtc->state = kzalloc(sizeof(*cstate), GFP_KERNEL); 692ff5952a7SSean Paul if (crtc->state) 693ff5952a7SSean Paul crtc->state->crtc = crtc; 69425fdd593SJeykumar Sankaran } 69525fdd593SJeykumar Sankaran 69625fdd593SJeykumar Sankaran /** 69725fdd593SJeykumar Sankaran * dpu_crtc_duplicate_state - state duplicate hook 69825fdd593SJeykumar Sankaran * @crtc: Pointer to drm crtc structure 69925fdd593SJeykumar Sankaran * @Returns: Pointer to new drm_crtc_state structure 70025fdd593SJeykumar Sankaran */ 70125fdd593SJeykumar Sankaran static struct drm_crtc_state *dpu_crtc_duplicate_state(struct drm_crtc *crtc) 70225fdd593SJeykumar Sankaran { 70325fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 70425fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate, *old_cstate; 70525fdd593SJeykumar Sankaran 70625fdd593SJeykumar Sankaran if (!crtc || !crtc->state) { 70725fdd593SJeykumar Sankaran DPU_ERROR("invalid argument(s)\n"); 70825fdd593SJeykumar Sankaran return NULL; 70925fdd593SJeykumar Sankaran } 71025fdd593SJeykumar Sankaran 71125fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 71225fdd593SJeykumar Sankaran old_cstate = to_dpu_crtc_state(crtc->state); 71325fdd593SJeykumar Sankaran cstate = kmemdup(old_cstate, sizeof(*old_cstate), GFP_KERNEL); 71425fdd593SJeykumar Sankaran if (!cstate) { 71525fdd593SJeykumar Sankaran DPU_ERROR("failed to allocate state\n"); 71625fdd593SJeykumar Sankaran return NULL; 71725fdd593SJeykumar Sankaran } 71825fdd593SJeykumar Sankaran 71925fdd593SJeykumar Sankaran /* duplicate base helper */ 72025fdd593SJeykumar Sankaran __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base); 72125fdd593SJeykumar Sankaran 72225fdd593SJeykumar Sankaran return &cstate->base; 72325fdd593SJeykumar Sankaran } 72425fdd593SJeykumar Sankaran 725f7aafc8dSSean Paul static void dpu_crtc_disable(struct drm_crtc *crtc, 726f7aafc8dSSean Paul struct drm_crtc_state *old_crtc_state) 72725fdd593SJeykumar Sankaran { 72825fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 72925fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 73025fdd593SJeykumar Sankaran struct drm_display_mode *mode; 73125fdd593SJeykumar Sankaran struct drm_encoder *encoder; 73225fdd593SJeykumar Sankaran struct msm_drm_private *priv; 7332f2eb723SRajesh Yadav unsigned long flags; 73425fdd593SJeykumar Sankaran 73525fdd593SJeykumar Sankaran if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) { 73625fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 73725fdd593SJeykumar Sankaran return; 73825fdd593SJeykumar Sankaran } 73925fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 74025fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(crtc->state); 74125fdd593SJeykumar Sankaran mode = &cstate->base.adjusted_mode; 74225fdd593SJeykumar Sankaran priv = crtc->dev->dev_private; 74325fdd593SJeykumar Sankaran 74425fdd593SJeykumar Sankaran DRM_DEBUG_KMS("crtc%d\n", crtc->base.id); 74525fdd593SJeykumar Sankaran 7462f2eb723SRajesh Yadav /* Disable/save vblank irq handling */ 7472f2eb723SRajesh Yadav drm_crtc_vblank_off(crtc); 7482f2eb723SRajesh Yadav 749a796ba2cSSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, 750a796ba2cSSean Paul old_crtc_state->encoder_mask) 751a796ba2cSSean Paul dpu_encoder_assign_crtc(encoder, NULL); 75225fdd593SJeykumar Sankaran 75325fdd593SJeykumar Sankaran /* wait for frame_event_done completion */ 75425fdd593SJeykumar Sankaran if (_dpu_crtc_wait_for_frame_done(crtc)) 75525fdd593SJeykumar Sankaran DPU_ERROR("crtc%d wait for frame done failed;frame_pending%d\n", 75625fdd593SJeykumar Sankaran crtc->base.id, 75725fdd593SJeykumar Sankaran atomic_read(&dpu_crtc->frame_pending)); 75825fdd593SJeykumar Sankaran 75925fdd593SJeykumar Sankaran trace_dpu_crtc_disable(DRMID(crtc), false, dpu_crtc); 76025fdd593SJeykumar Sankaran dpu_crtc->enabled = false; 76125fdd593SJeykumar Sankaran 76225fdd593SJeykumar Sankaran if (atomic_read(&dpu_crtc->frame_pending)) { 76325fdd593SJeykumar Sankaran trace_dpu_crtc_disable_frame_pending(DRMID(crtc), 76425fdd593SJeykumar Sankaran atomic_read(&dpu_crtc->frame_pending)); 76525fdd593SJeykumar Sankaran dpu_core_perf_crtc_release_bw(crtc); 76625fdd593SJeykumar Sankaran atomic_set(&dpu_crtc->frame_pending, 0); 76725fdd593SJeykumar Sankaran } 76825fdd593SJeykumar Sankaran 76925fdd593SJeykumar Sankaran dpu_core_perf_crtc_update(crtc, 0, true); 77025fdd593SJeykumar Sankaran 7714b8c6279SSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) 77225fdd593SJeykumar Sankaran dpu_encoder_register_frame_event_callback(encoder, NULL, NULL); 77325fdd593SJeykumar Sankaran 7749222cdd2SJeykumar Sankaran memset(cstate->mixers, 0, sizeof(cstate->mixers)); 7759222cdd2SJeykumar Sankaran cstate->num_mixers = 0; 77625fdd593SJeykumar Sankaran 77725fdd593SJeykumar Sankaran /* disable clk & bw control until clk & bw properties are set */ 77825fdd593SJeykumar Sankaran cstate->bw_control = false; 77925fdd593SJeykumar Sankaran cstate->bw_split_vote = false; 78025fdd593SJeykumar Sankaran 7812f2eb723SRajesh Yadav if (crtc->state->event && !crtc->state->active) { 7822f2eb723SRajesh Yadav spin_lock_irqsave(&crtc->dev->event_lock, flags); 7832f2eb723SRajesh Yadav drm_crtc_send_vblank_event(crtc, crtc->state->event); 7842f2eb723SRajesh Yadav crtc->state->event = NULL; 7852f2eb723SRajesh Yadav spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 7862f2eb723SRajesh Yadav } 787b77d0f0dSSean Paul 788b77d0f0dSSean Paul pm_runtime_put_sync(crtc->dev->dev); 78925fdd593SJeykumar Sankaran } 79025fdd593SJeykumar Sankaran 79125fdd593SJeykumar Sankaran static void dpu_crtc_enable(struct drm_crtc *crtc, 79225fdd593SJeykumar Sankaran struct drm_crtc_state *old_crtc_state) 79325fdd593SJeykumar Sankaran { 79425fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 79525fdd593SJeykumar Sankaran struct drm_encoder *encoder; 79625fdd593SJeykumar Sankaran struct msm_drm_private *priv; 79725fdd593SJeykumar Sankaran 79825fdd593SJeykumar Sankaran if (!crtc || !crtc->dev || !crtc->dev->dev_private) { 79925fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 80025fdd593SJeykumar Sankaran return; 80125fdd593SJeykumar Sankaran } 80225fdd593SJeykumar Sankaran priv = crtc->dev->dev_private; 80325fdd593SJeykumar Sankaran 804b77d0f0dSSean Paul pm_runtime_get_sync(crtc->dev->dev); 805b77d0f0dSSean Paul 80625fdd593SJeykumar Sankaran DRM_DEBUG_KMS("crtc%d\n", crtc->base.id); 80725fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 80825fdd593SJeykumar Sankaran 8094b8c6279SSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) 81025fdd593SJeykumar Sankaran dpu_encoder_register_frame_event_callback(encoder, 81125fdd593SJeykumar Sankaran dpu_crtc_frame_event_cb, (void *)crtc); 81225fdd593SJeykumar Sankaran 81325fdd593SJeykumar Sankaran trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc); 81425fdd593SJeykumar Sankaran dpu_crtc->enabled = true; 81525fdd593SJeykumar Sankaran 816a796ba2cSSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) 817a796ba2cSSean Paul dpu_encoder_assign_crtc(encoder, crtc); 81825fdd593SJeykumar Sankaran 8192f2eb723SRajesh Yadav /* Enable/restore vblank irq handling */ 8202f2eb723SRajesh Yadav drm_crtc_vblank_on(crtc); 82125fdd593SJeykumar Sankaran } 82225fdd593SJeykumar Sankaran 82325fdd593SJeykumar Sankaran struct plane_state { 82425fdd593SJeykumar Sankaran struct dpu_plane_state *dpu_pstate; 82525fdd593SJeykumar Sankaran const struct drm_plane_state *drm_pstate; 82625fdd593SJeykumar Sankaran int stage; 82725fdd593SJeykumar Sankaran u32 pipe_id; 82825fdd593SJeykumar Sankaran }; 82925fdd593SJeykumar Sankaran 83025fdd593SJeykumar Sankaran static int dpu_crtc_atomic_check(struct drm_crtc *crtc, 83125fdd593SJeykumar Sankaran struct drm_crtc_state *state) 83225fdd593SJeykumar Sankaran { 83325fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 83425fdd593SJeykumar Sankaran struct plane_state *pstates; 83525fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 83625fdd593SJeykumar Sankaran 83725fdd593SJeykumar Sankaran const struct drm_plane_state *pstate; 83825fdd593SJeykumar Sankaran struct drm_plane *plane; 83925fdd593SJeykumar Sankaran struct drm_display_mode *mode; 84025fdd593SJeykumar Sankaran 84125fdd593SJeykumar Sankaran int cnt = 0, rc = 0, mixer_width, i, z_pos; 84225fdd593SJeykumar Sankaran 84325fdd593SJeykumar Sankaran struct dpu_multirect_plane_states multirect_plane[DPU_STAGE_MAX * 2]; 84425fdd593SJeykumar Sankaran int multirect_count = 0; 84525fdd593SJeykumar Sankaran const struct drm_plane_state *pipe_staged[SSPP_MAX]; 84625fdd593SJeykumar Sankaran int left_zpos_cnt = 0, right_zpos_cnt = 0; 84725fdd593SJeykumar Sankaran struct drm_rect crtc_rect = { 0 }; 84825fdd593SJeykumar Sankaran 84925fdd593SJeykumar Sankaran if (!crtc) { 85025fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 85125fdd593SJeykumar Sankaran return -EINVAL; 85225fdd593SJeykumar Sankaran } 85325fdd593SJeykumar Sankaran 85425fdd593SJeykumar Sankaran pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL); 85525fdd593SJeykumar Sankaran 85625fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 85725fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(state); 85825fdd593SJeykumar Sankaran 85925fdd593SJeykumar Sankaran if (!state->enable || !state->active) { 86025fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n", 86125fdd593SJeykumar Sankaran crtc->base.id, state->enable, state->active); 86225fdd593SJeykumar Sankaran goto end; 86325fdd593SJeykumar Sankaran } 86425fdd593SJeykumar Sankaran 86525fdd593SJeykumar Sankaran mode = &state->adjusted_mode; 86625fdd593SJeykumar Sankaran DPU_DEBUG("%s: check", dpu_crtc->name); 86725fdd593SJeykumar Sankaran 86825fdd593SJeykumar Sankaran /* force a full mode set if active state changed */ 86925fdd593SJeykumar Sankaran if (state->active_changed) 87025fdd593SJeykumar Sankaran state->mode_changed = true; 87125fdd593SJeykumar Sankaran 87225fdd593SJeykumar Sankaran memset(pipe_staged, 0, sizeof(pipe_staged)); 87325fdd593SJeykumar Sankaran 8743804a982SJordan Crouse mixer_width = mode->hdisplay / cstate->num_mixers; 87525fdd593SJeykumar Sankaran 87625fdd593SJeykumar Sankaran _dpu_crtc_setup_lm_bounds(crtc, state); 87725fdd593SJeykumar Sankaran 87825fdd593SJeykumar Sankaran crtc_rect.x2 = mode->hdisplay; 87925fdd593SJeykumar Sankaran crtc_rect.y2 = mode->vdisplay; 88025fdd593SJeykumar Sankaran 88125fdd593SJeykumar Sankaran /* get plane state for all drm planes associated with crtc state */ 88225fdd593SJeykumar Sankaran drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { 88325fdd593SJeykumar Sankaran struct drm_rect dst, clip = crtc_rect; 88425fdd593SJeykumar Sankaran 88525fdd593SJeykumar Sankaran if (IS_ERR_OR_NULL(pstate)) { 88625fdd593SJeykumar Sankaran rc = PTR_ERR(pstate); 88725fdd593SJeykumar Sankaran DPU_ERROR("%s: failed to get plane%d state, %d\n", 88825fdd593SJeykumar Sankaran dpu_crtc->name, plane->base.id, rc); 88925fdd593SJeykumar Sankaran goto end; 89025fdd593SJeykumar Sankaran } 89125fdd593SJeykumar Sankaran if (cnt >= DPU_STAGE_MAX * 4) 89225fdd593SJeykumar Sankaran continue; 89325fdd593SJeykumar Sankaran 89425fdd593SJeykumar Sankaran pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate); 89525fdd593SJeykumar Sankaran pstates[cnt].drm_pstate = pstate; 89625fdd593SJeykumar Sankaran pstates[cnt].stage = pstate->normalized_zpos; 89725fdd593SJeykumar Sankaran pstates[cnt].pipe_id = dpu_plane_pipe(plane); 89825fdd593SJeykumar Sankaran 89925fdd593SJeykumar Sankaran if (pipe_staged[pstates[cnt].pipe_id]) { 90025fdd593SJeykumar Sankaran multirect_plane[multirect_count].r0 = 90125fdd593SJeykumar Sankaran pipe_staged[pstates[cnt].pipe_id]; 90225fdd593SJeykumar Sankaran multirect_plane[multirect_count].r1 = pstate; 90325fdd593SJeykumar Sankaran multirect_count++; 90425fdd593SJeykumar Sankaran 90525fdd593SJeykumar Sankaran pipe_staged[pstates[cnt].pipe_id] = NULL; 90625fdd593SJeykumar Sankaran } else { 90725fdd593SJeykumar Sankaran pipe_staged[pstates[cnt].pipe_id] = pstate; 90825fdd593SJeykumar Sankaran } 90925fdd593SJeykumar Sankaran 91025fdd593SJeykumar Sankaran cnt++; 91125fdd593SJeykumar Sankaran 91225fdd593SJeykumar Sankaran dst = drm_plane_state_dest(pstate); 91396fc56a7SSean Paul if (!drm_rect_intersect(&clip, &dst)) { 91425fdd593SJeykumar Sankaran DPU_ERROR("invalid vertical/horizontal destination\n"); 91525fdd593SJeykumar Sankaran DPU_ERROR("display: " DRM_RECT_FMT " plane: " 91625fdd593SJeykumar Sankaran DRM_RECT_FMT "\n", DRM_RECT_ARG(&crtc_rect), 91725fdd593SJeykumar Sankaran DRM_RECT_ARG(&dst)); 91825fdd593SJeykumar Sankaran rc = -E2BIG; 91925fdd593SJeykumar Sankaran goto end; 92025fdd593SJeykumar Sankaran } 92125fdd593SJeykumar Sankaran } 92225fdd593SJeykumar Sankaran 92325fdd593SJeykumar Sankaran for (i = 1; i < SSPP_MAX; i++) { 92425fdd593SJeykumar Sankaran if (pipe_staged[i]) { 92525fdd593SJeykumar Sankaran dpu_plane_clear_multirect(pipe_staged[i]); 92625fdd593SJeykumar Sankaran 92725fdd593SJeykumar Sankaran if (is_dpu_plane_virtual(pipe_staged[i]->plane)) { 92825fdd593SJeykumar Sankaran DPU_ERROR( 92925fdd593SJeykumar Sankaran "r1 only virt plane:%d not supported\n", 93025fdd593SJeykumar Sankaran pipe_staged[i]->plane->base.id); 93125fdd593SJeykumar Sankaran rc = -EINVAL; 93225fdd593SJeykumar Sankaran goto end; 93325fdd593SJeykumar Sankaran } 93425fdd593SJeykumar Sankaran } 93525fdd593SJeykumar Sankaran } 93625fdd593SJeykumar Sankaran 93725fdd593SJeykumar Sankaran z_pos = -1; 93825fdd593SJeykumar Sankaran for (i = 0; i < cnt; i++) { 93925fdd593SJeykumar Sankaran /* reset counts at every new blend stage */ 94025fdd593SJeykumar Sankaran if (pstates[i].stage != z_pos) { 94125fdd593SJeykumar Sankaran left_zpos_cnt = 0; 94225fdd593SJeykumar Sankaran right_zpos_cnt = 0; 94325fdd593SJeykumar Sankaran z_pos = pstates[i].stage; 94425fdd593SJeykumar Sankaran } 94525fdd593SJeykumar Sankaran 94625fdd593SJeykumar Sankaran /* verify z_pos setting before using it */ 94725fdd593SJeykumar Sankaran if (z_pos >= DPU_STAGE_MAX - DPU_STAGE_0) { 94825fdd593SJeykumar Sankaran DPU_ERROR("> %d plane stages assigned\n", 94925fdd593SJeykumar Sankaran DPU_STAGE_MAX - DPU_STAGE_0); 95025fdd593SJeykumar Sankaran rc = -EINVAL; 95125fdd593SJeykumar Sankaran goto end; 95225fdd593SJeykumar Sankaran } else if (pstates[i].drm_pstate->crtc_x < mixer_width) { 95325fdd593SJeykumar Sankaran if (left_zpos_cnt == 2) { 95425fdd593SJeykumar Sankaran DPU_ERROR("> 2 planes @ stage %d on left\n", 95525fdd593SJeykumar Sankaran z_pos); 95625fdd593SJeykumar Sankaran rc = -EINVAL; 95725fdd593SJeykumar Sankaran goto end; 95825fdd593SJeykumar Sankaran } 95925fdd593SJeykumar Sankaran left_zpos_cnt++; 96025fdd593SJeykumar Sankaran 96125fdd593SJeykumar Sankaran } else { 96225fdd593SJeykumar Sankaran if (right_zpos_cnt == 2) { 96325fdd593SJeykumar Sankaran DPU_ERROR("> 2 planes @ stage %d on right\n", 96425fdd593SJeykumar Sankaran z_pos); 96525fdd593SJeykumar Sankaran rc = -EINVAL; 96625fdd593SJeykumar Sankaran goto end; 96725fdd593SJeykumar Sankaran } 96825fdd593SJeykumar Sankaran right_zpos_cnt++; 96925fdd593SJeykumar Sankaran } 97025fdd593SJeykumar Sankaran 97125fdd593SJeykumar Sankaran pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0; 97225fdd593SJeykumar Sankaran DPU_DEBUG("%s: zpos %d", dpu_crtc->name, z_pos); 97325fdd593SJeykumar Sankaran } 97425fdd593SJeykumar Sankaran 97525fdd593SJeykumar Sankaran for (i = 0; i < multirect_count; i++) { 97625fdd593SJeykumar Sankaran if (dpu_plane_validate_multirect_v2(&multirect_plane[i])) { 97725fdd593SJeykumar Sankaran DPU_ERROR( 97825fdd593SJeykumar Sankaran "multirect validation failed for planes (%d - %d)\n", 97925fdd593SJeykumar Sankaran multirect_plane[i].r0->plane->base.id, 98025fdd593SJeykumar Sankaran multirect_plane[i].r1->plane->base.id); 98125fdd593SJeykumar Sankaran rc = -EINVAL; 98225fdd593SJeykumar Sankaran goto end; 98325fdd593SJeykumar Sankaran } 98425fdd593SJeykumar Sankaran } 98525fdd593SJeykumar Sankaran 98625fdd593SJeykumar Sankaran rc = dpu_core_perf_crtc_check(crtc, state); 98725fdd593SJeykumar Sankaran if (rc) { 98825fdd593SJeykumar Sankaran DPU_ERROR("crtc%d failed performance check %d\n", 98925fdd593SJeykumar Sankaran crtc->base.id, rc); 99025fdd593SJeykumar Sankaran goto end; 99125fdd593SJeykumar Sankaran } 99225fdd593SJeykumar Sankaran 99325fdd593SJeykumar Sankaran /* validate source split: 99425fdd593SJeykumar Sankaran * use pstates sorted by stage to check planes on same stage 99525fdd593SJeykumar Sankaran * we assume that all pipes are in source split so its valid to compare 99625fdd593SJeykumar Sankaran * without taking into account left/right mixer placement 99725fdd593SJeykumar Sankaran */ 99825fdd593SJeykumar Sankaran for (i = 1; i < cnt; i++) { 99925fdd593SJeykumar Sankaran struct plane_state *prv_pstate, *cur_pstate; 100025fdd593SJeykumar Sankaran struct drm_rect left_rect, right_rect; 100125fdd593SJeykumar Sankaran int32_t left_pid, right_pid; 100225fdd593SJeykumar Sankaran int32_t stage; 100325fdd593SJeykumar Sankaran 100425fdd593SJeykumar Sankaran prv_pstate = &pstates[i - 1]; 100525fdd593SJeykumar Sankaran cur_pstate = &pstates[i]; 100625fdd593SJeykumar Sankaran if (prv_pstate->stage != cur_pstate->stage) 100725fdd593SJeykumar Sankaran continue; 100825fdd593SJeykumar Sankaran 100925fdd593SJeykumar Sankaran stage = cur_pstate->stage; 101025fdd593SJeykumar Sankaran 101125fdd593SJeykumar Sankaran left_pid = prv_pstate->dpu_pstate->base.plane->base.id; 101225fdd593SJeykumar Sankaran left_rect = drm_plane_state_dest(prv_pstate->drm_pstate); 101325fdd593SJeykumar Sankaran 101425fdd593SJeykumar Sankaran right_pid = cur_pstate->dpu_pstate->base.plane->base.id; 101525fdd593SJeykumar Sankaran right_rect = drm_plane_state_dest(cur_pstate->drm_pstate); 101625fdd593SJeykumar Sankaran 101725fdd593SJeykumar Sankaran if (right_rect.x1 < left_rect.x1) { 101825fdd593SJeykumar Sankaran swap(left_pid, right_pid); 101925fdd593SJeykumar Sankaran swap(left_rect, right_rect); 102025fdd593SJeykumar Sankaran } 102125fdd593SJeykumar Sankaran 102225fdd593SJeykumar Sankaran /** 102325fdd593SJeykumar Sankaran * - planes are enumerated in pipe-priority order such that 102425fdd593SJeykumar Sankaran * planes with lower drm_id must be left-most in a shared 102525fdd593SJeykumar Sankaran * blend-stage when using source split. 102625fdd593SJeykumar Sankaran * - planes in source split must be contiguous in width 102725fdd593SJeykumar Sankaran * - planes in source split must have same dest yoff and height 102825fdd593SJeykumar Sankaran */ 102925fdd593SJeykumar Sankaran if (right_pid < left_pid) { 103025fdd593SJeykumar Sankaran DPU_ERROR( 103125fdd593SJeykumar Sankaran "invalid src split cfg. priority mismatch. stage: %d left: %d right: %d\n", 103225fdd593SJeykumar Sankaran stage, left_pid, right_pid); 103325fdd593SJeykumar Sankaran rc = -EINVAL; 103425fdd593SJeykumar Sankaran goto end; 103525fdd593SJeykumar Sankaran } else if (right_rect.x1 != drm_rect_width(&left_rect)) { 103625fdd593SJeykumar Sankaran DPU_ERROR("non-contiguous coordinates for src split. " 103725fdd593SJeykumar Sankaran "stage: %d left: " DRM_RECT_FMT " right: " 103825fdd593SJeykumar Sankaran DRM_RECT_FMT "\n", stage, 103925fdd593SJeykumar Sankaran DRM_RECT_ARG(&left_rect), 104025fdd593SJeykumar Sankaran DRM_RECT_ARG(&right_rect)); 104125fdd593SJeykumar Sankaran rc = -EINVAL; 104225fdd593SJeykumar Sankaran goto end; 104325fdd593SJeykumar Sankaran } else if (left_rect.y1 != right_rect.y1 || 104425fdd593SJeykumar Sankaran drm_rect_height(&left_rect) != drm_rect_height(&right_rect)) { 104525fdd593SJeykumar Sankaran DPU_ERROR("source split at stage: %d. invalid " 104625fdd593SJeykumar Sankaran "yoff/height: left: " DRM_RECT_FMT " right: " 104725fdd593SJeykumar Sankaran DRM_RECT_FMT "\n", stage, 104825fdd593SJeykumar Sankaran DRM_RECT_ARG(&left_rect), 104925fdd593SJeykumar Sankaran DRM_RECT_ARG(&right_rect)); 105025fdd593SJeykumar Sankaran rc = -EINVAL; 105125fdd593SJeykumar Sankaran goto end; 105225fdd593SJeykumar Sankaran } 105325fdd593SJeykumar Sankaran } 105425fdd593SJeykumar Sankaran 105525fdd593SJeykumar Sankaran end: 105625fdd593SJeykumar Sankaran kfree(pstates); 105725fdd593SJeykumar Sankaran return rc; 105825fdd593SJeykumar Sankaran } 105925fdd593SJeykumar Sankaran 106025fdd593SJeykumar Sankaran int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) 106125fdd593SJeykumar Sankaran { 10627a007a12SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 1063a796ba2cSSean Paul struct drm_encoder *enc; 106425fdd593SJeykumar Sankaran 106525fdd593SJeykumar Sankaran trace_dpu_crtc_vblank(DRMID(&dpu_crtc->base), en, dpu_crtc); 1066a796ba2cSSean Paul 1067a796ba2cSSean Paul /* 1068a796ba2cSSean Paul * Normally we would iterate through encoder_mask in crtc state to find 1069a796ba2cSSean Paul * attached encoders. In this case, we might be disabling vblank _after_ 1070a796ba2cSSean Paul * encoder_mask has been cleared. 1071a796ba2cSSean Paul * 1072a796ba2cSSean Paul * Instead, we "assign" a crtc to the encoder in enable and clear it in 1073a796ba2cSSean Paul * disable (which is also after encoder_mask is cleared). So instead of 1074a796ba2cSSean Paul * using encoder mask, we'll ask the encoder to toggle itself iff it's 1075a796ba2cSSean Paul * currently assigned to our crtc. 1076a796ba2cSSean Paul * 1077a796ba2cSSean Paul * Note also that this function cannot be called while crtc is disabled 1078a796ba2cSSean Paul * since we use drm_crtc_vblank_on/off. So we don't need to worry 1079a796ba2cSSean Paul * about the assigned crtcs being inconsistent with the current state 1080a796ba2cSSean Paul * (which means no need to worry about modeset locks). 1081a796ba2cSSean Paul */ 1082a796ba2cSSean Paul list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) { 1083a796ba2cSSean Paul trace_dpu_crtc_vblank_enable(DRMID(crtc), DRMID(enc), en, 1084a796ba2cSSean Paul dpu_crtc); 1085a796ba2cSSean Paul 1086a796ba2cSSean Paul dpu_encoder_toggle_vblank_for_crtc(enc, crtc, en); 108725fdd593SJeykumar Sankaran } 108825fdd593SJeykumar Sankaran 108925fdd593SJeykumar Sankaran return 0; 109025fdd593SJeykumar Sankaran } 109125fdd593SJeykumar Sankaran 109225fdd593SJeykumar Sankaran #ifdef CONFIG_DEBUG_FS 109325fdd593SJeykumar Sankaran static int _dpu_debugfs_status_show(struct seq_file *s, void *data) 109425fdd593SJeykumar Sankaran { 109525fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 109625fdd593SJeykumar Sankaran struct dpu_plane_state *pstate = NULL; 109725fdd593SJeykumar Sankaran struct dpu_crtc_mixer *m; 109825fdd593SJeykumar Sankaran 109925fdd593SJeykumar Sankaran struct drm_crtc *crtc; 110025fdd593SJeykumar Sankaran struct drm_plane *plane; 110125fdd593SJeykumar Sankaran struct drm_display_mode *mode; 110225fdd593SJeykumar Sankaran struct drm_framebuffer *fb; 110325fdd593SJeykumar Sankaran struct drm_plane_state *state; 110425fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 110525fdd593SJeykumar Sankaran 110625fdd593SJeykumar Sankaran int i, out_width; 110725fdd593SJeykumar Sankaran 110825fdd593SJeykumar Sankaran dpu_crtc = s->private; 110925fdd593SJeykumar Sankaran crtc = &dpu_crtc->base; 11109222cdd2SJeykumar Sankaran 11119222cdd2SJeykumar Sankaran drm_modeset_lock_all(crtc->dev); 111225fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(crtc->state); 111325fdd593SJeykumar Sankaran 111425fdd593SJeykumar Sankaran mode = &crtc->state->adjusted_mode; 11153804a982SJordan Crouse out_width = mode->hdisplay / cstate->num_mixers; 111625fdd593SJeykumar Sankaran 111725fdd593SJeykumar Sankaran seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id, 111825fdd593SJeykumar Sankaran mode->hdisplay, mode->vdisplay); 111925fdd593SJeykumar Sankaran 112025fdd593SJeykumar Sankaran seq_puts(s, "\n"); 112125fdd593SJeykumar Sankaran 11229222cdd2SJeykumar Sankaran for (i = 0; i < cstate->num_mixers; ++i) { 11239222cdd2SJeykumar Sankaran m = &cstate->mixers[i]; 112425fdd593SJeykumar Sankaran if (!m->hw_lm) 112525fdd593SJeykumar Sankaran seq_printf(s, "\tmixer[%d] has no lm\n", i); 1126cf6916f4SJeykumar Sankaran else if (!m->lm_ctl) 112725fdd593SJeykumar Sankaran seq_printf(s, "\tmixer[%d] has no ctl\n", i); 112825fdd593SJeykumar Sankaran else 112925fdd593SJeykumar Sankaran seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n", 1130cf6916f4SJeykumar Sankaran m->hw_lm->idx - LM_0, m->lm_ctl->idx - CTL_0, 113125fdd593SJeykumar Sankaran out_width, mode->vdisplay); 113225fdd593SJeykumar Sankaran } 113325fdd593SJeykumar Sankaran 113425fdd593SJeykumar Sankaran seq_puts(s, "\n"); 113525fdd593SJeykumar Sankaran 113625fdd593SJeykumar Sankaran drm_atomic_crtc_for_each_plane(plane, crtc) { 113725fdd593SJeykumar Sankaran pstate = to_dpu_plane_state(plane->state); 113825fdd593SJeykumar Sankaran state = plane->state; 113925fdd593SJeykumar Sankaran 114025fdd593SJeykumar Sankaran if (!pstate || !state) 114125fdd593SJeykumar Sankaran continue; 114225fdd593SJeykumar Sankaran 114325fdd593SJeykumar Sankaran seq_printf(s, "\tplane:%u stage:%d\n", plane->base.id, 114425fdd593SJeykumar Sankaran pstate->stage); 114525fdd593SJeykumar Sankaran 114625fdd593SJeykumar Sankaran if (plane->state->fb) { 114725fdd593SJeykumar Sankaran fb = plane->state->fb; 114825fdd593SJeykumar Sankaran 114925fdd593SJeykumar Sankaran seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u ", 115025fdd593SJeykumar Sankaran fb->base.id, (char *) &fb->format->format, 115125fdd593SJeykumar Sankaran fb->width, fb->height); 115225fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(fb->format->cpp); ++i) 115325fdd593SJeykumar Sankaran seq_printf(s, "cpp[%d]:%u ", 115425fdd593SJeykumar Sankaran i, fb->format->cpp[i]); 115525fdd593SJeykumar Sankaran seq_puts(s, "\n\t"); 115625fdd593SJeykumar Sankaran 115725fdd593SJeykumar Sankaran seq_printf(s, "modifier:%8llu ", fb->modifier); 115825fdd593SJeykumar Sankaran seq_puts(s, "\n"); 115925fdd593SJeykumar Sankaran 116025fdd593SJeykumar Sankaran seq_puts(s, "\t"); 116125fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) 116225fdd593SJeykumar Sankaran seq_printf(s, "pitches[%d]:%8u ", i, 116325fdd593SJeykumar Sankaran fb->pitches[i]); 116425fdd593SJeykumar Sankaran seq_puts(s, "\n"); 116525fdd593SJeykumar Sankaran 116625fdd593SJeykumar Sankaran seq_puts(s, "\t"); 116725fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) 116825fdd593SJeykumar Sankaran seq_printf(s, "offsets[%d]:%8u ", i, 116925fdd593SJeykumar Sankaran fb->offsets[i]); 117025fdd593SJeykumar Sankaran seq_puts(s, "\n"); 117125fdd593SJeykumar Sankaran } 117225fdd593SJeykumar Sankaran 117325fdd593SJeykumar Sankaran seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n", 117425fdd593SJeykumar Sankaran state->src_x, state->src_y, state->src_w, state->src_h); 117525fdd593SJeykumar Sankaran 117625fdd593SJeykumar Sankaran seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", 117725fdd593SJeykumar Sankaran state->crtc_x, state->crtc_y, state->crtc_w, 117825fdd593SJeykumar Sankaran state->crtc_h); 117925fdd593SJeykumar Sankaran seq_printf(s, "\tmultirect: mode: %d index: %d\n", 118025fdd593SJeykumar Sankaran pstate->multirect_mode, pstate->multirect_index); 118125fdd593SJeykumar Sankaran 118225fdd593SJeykumar Sankaran seq_puts(s, "\n"); 118325fdd593SJeykumar Sankaran } 118425fdd593SJeykumar Sankaran if (dpu_crtc->vblank_cb_count) { 118525fdd593SJeykumar Sankaran ktime_t diff = ktime_sub(ktime_get(), dpu_crtc->vblank_cb_time); 118625fdd593SJeykumar Sankaran s64 diff_ms = ktime_to_ms(diff); 118725fdd593SJeykumar Sankaran s64 fps = diff_ms ? div_s64( 118825fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_count * 1000, diff_ms) : 0; 118925fdd593SJeykumar Sankaran 119025fdd593SJeykumar Sankaran seq_printf(s, 119125fdd593SJeykumar Sankaran "vblank fps:%lld count:%u total:%llums total_framecount:%llu\n", 119225fdd593SJeykumar Sankaran fps, dpu_crtc->vblank_cb_count, 119325fdd593SJeykumar Sankaran ktime_to_ms(diff), dpu_crtc->play_count); 119425fdd593SJeykumar Sankaran 119525fdd593SJeykumar Sankaran /* reset time & count for next measurement */ 119625fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_count = 0; 119725fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_time = ktime_set(0, 0); 119825fdd593SJeykumar Sankaran } 119925fdd593SJeykumar Sankaran 12009222cdd2SJeykumar Sankaran drm_modeset_unlock_all(crtc->dev); 120125fdd593SJeykumar Sankaran 120225fdd593SJeykumar Sankaran return 0; 120325fdd593SJeykumar Sankaran } 120425fdd593SJeykumar Sankaran 120525fdd593SJeykumar Sankaran static int _dpu_debugfs_status_open(struct inode *inode, struct file *file) 120625fdd593SJeykumar Sankaran { 120725fdd593SJeykumar Sankaran return single_open(file, _dpu_debugfs_status_show, inode->i_private); 120825fdd593SJeykumar Sankaran } 120925fdd593SJeykumar Sankaran 121025fdd593SJeykumar Sankaran #define DEFINE_DPU_DEBUGFS_SEQ_FOPS(__prefix) \ 121125fdd593SJeykumar Sankaran static int __prefix ## _open(struct inode *inode, struct file *file) \ 121225fdd593SJeykumar Sankaran { \ 121325fdd593SJeykumar Sankaran return single_open(file, __prefix ## _show, inode->i_private); \ 121425fdd593SJeykumar Sankaran } \ 121525fdd593SJeykumar Sankaran static const struct file_operations __prefix ## _fops = { \ 121625fdd593SJeykumar Sankaran .owner = THIS_MODULE, \ 121725fdd593SJeykumar Sankaran .open = __prefix ## _open, \ 121825fdd593SJeykumar Sankaran .release = single_release, \ 121925fdd593SJeykumar Sankaran .read = seq_read, \ 122025fdd593SJeykumar Sankaran .llseek = seq_lseek, \ 122125fdd593SJeykumar Sankaran } 122225fdd593SJeykumar Sankaran 122325fdd593SJeykumar Sankaran static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v) 122425fdd593SJeykumar Sankaran { 122525fdd593SJeykumar Sankaran struct drm_crtc *crtc = (struct drm_crtc *) s->private; 122625fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 122725fdd593SJeykumar Sankaran int i; 122825fdd593SJeykumar Sankaran 122925fdd593SJeykumar Sankaran seq_printf(s, "client type: %d\n", dpu_crtc_get_client_type(crtc)); 123025fdd593SJeykumar Sankaran seq_printf(s, "intf_mode: %d\n", dpu_crtc_get_intf_mode(crtc)); 123125fdd593SJeykumar Sankaran seq_printf(s, "core_clk_rate: %llu\n", 123225fdd593SJeykumar Sankaran dpu_crtc->cur_perf.core_clk_rate); 1233aeb7b49aSSean Paul for (i = DPU_CORE_PERF_DATA_BUS_ID_MNOC; 1234aeb7b49aSSean Paul i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { 12355e1228d7SSean Paul seq_printf(s, "bw_ctl[%d]: %llu\n", i, 123625fdd593SJeykumar Sankaran dpu_crtc->cur_perf.bw_ctl[i]); 12375e1228d7SSean Paul seq_printf(s, "max_per_pipe_ib[%d]: %llu\n", i, 123825fdd593SJeykumar Sankaran dpu_crtc->cur_perf.max_per_pipe_ib[i]); 123925fdd593SJeykumar Sankaran } 124025fdd593SJeykumar Sankaran 124125fdd593SJeykumar Sankaran return 0; 124225fdd593SJeykumar Sankaran } 124325fdd593SJeykumar Sankaran DEFINE_DPU_DEBUGFS_SEQ_FOPS(dpu_crtc_debugfs_state); 124425fdd593SJeykumar Sankaran 124525fdd593SJeykumar Sankaran static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc) 124625fdd593SJeykumar Sankaran { 12473d688410SJordan Crouse struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 124825fdd593SJeykumar Sankaran 124925fdd593SJeykumar Sankaran static const struct file_operations debugfs_status_fops = { 125025fdd593SJeykumar Sankaran .open = _dpu_debugfs_status_open, 125125fdd593SJeykumar Sankaran .read = seq_read, 125225fdd593SJeykumar Sankaran .llseek = seq_lseek, 125325fdd593SJeykumar Sankaran .release = single_release, 125425fdd593SJeykumar Sankaran }; 125525fdd593SJeykumar Sankaran 125625fdd593SJeykumar Sankaran dpu_crtc->debugfs_root = debugfs_create_dir(dpu_crtc->name, 125725fdd593SJeykumar Sankaran crtc->dev->primary->debugfs_root); 125825fdd593SJeykumar Sankaran if (!dpu_crtc->debugfs_root) 125925fdd593SJeykumar Sankaran return -ENOMEM; 126025fdd593SJeykumar Sankaran 126125fdd593SJeykumar Sankaran /* don't error check these */ 126225fdd593SJeykumar Sankaran debugfs_create_file("status", 0400, 126325fdd593SJeykumar Sankaran dpu_crtc->debugfs_root, 126425fdd593SJeykumar Sankaran dpu_crtc, &debugfs_status_fops); 126525fdd593SJeykumar Sankaran debugfs_create_file("state", 0600, 126625fdd593SJeykumar Sankaran dpu_crtc->debugfs_root, 126725fdd593SJeykumar Sankaran &dpu_crtc->base, 126825fdd593SJeykumar Sankaran &dpu_crtc_debugfs_state_fops); 126925fdd593SJeykumar Sankaran 127025fdd593SJeykumar Sankaran return 0; 127125fdd593SJeykumar Sankaran } 127225fdd593SJeykumar Sankaran #else 127325fdd593SJeykumar Sankaran static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc) 127425fdd593SJeykumar Sankaran { 127525fdd593SJeykumar Sankaran return 0; 127625fdd593SJeykumar Sankaran } 127725fdd593SJeykumar Sankaran #endif /* CONFIG_DEBUG_FS */ 127825fdd593SJeykumar Sankaran 127925fdd593SJeykumar Sankaran static int dpu_crtc_late_register(struct drm_crtc *crtc) 128025fdd593SJeykumar Sankaran { 128125fdd593SJeykumar Sankaran return _dpu_crtc_init_debugfs(crtc); 128225fdd593SJeykumar Sankaran } 128325fdd593SJeykumar Sankaran 128425fdd593SJeykumar Sankaran static void dpu_crtc_early_unregister(struct drm_crtc *crtc) 128525fdd593SJeykumar Sankaran { 12863d688410SJordan Crouse struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 12873d688410SJordan Crouse 12883d688410SJordan Crouse debugfs_remove_recursive(dpu_crtc->debugfs_root); 128925fdd593SJeykumar Sankaran } 129025fdd593SJeykumar Sankaran 129125fdd593SJeykumar Sankaran static const struct drm_crtc_funcs dpu_crtc_funcs = { 129225fdd593SJeykumar Sankaran .set_config = drm_atomic_helper_set_config, 129325fdd593SJeykumar Sankaran .destroy = dpu_crtc_destroy, 129425fdd593SJeykumar Sankaran .page_flip = drm_atomic_helper_page_flip, 129525fdd593SJeykumar Sankaran .reset = dpu_crtc_reset, 129625fdd593SJeykumar Sankaran .atomic_duplicate_state = dpu_crtc_duplicate_state, 129725fdd593SJeykumar Sankaran .atomic_destroy_state = dpu_crtc_destroy_state, 129825fdd593SJeykumar Sankaran .late_register = dpu_crtc_late_register, 129925fdd593SJeykumar Sankaran .early_unregister = dpu_crtc_early_unregister, 130025fdd593SJeykumar Sankaran }; 130125fdd593SJeykumar Sankaran 130225fdd593SJeykumar Sankaran static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = { 1303f7aafc8dSSean Paul .atomic_disable = dpu_crtc_disable, 130425fdd593SJeykumar Sankaran .atomic_enable = dpu_crtc_enable, 130525fdd593SJeykumar Sankaran .atomic_check = dpu_crtc_atomic_check, 130625fdd593SJeykumar Sankaran .atomic_begin = dpu_crtc_atomic_begin, 130725fdd593SJeykumar Sankaran .atomic_flush = dpu_crtc_atomic_flush, 130825fdd593SJeykumar Sankaran }; 130925fdd593SJeykumar Sankaran 131025fdd593SJeykumar Sankaran /* initialize crtc */ 131107ca1fc0SSravanthi Kollukuduru struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, 131207ca1fc0SSravanthi Kollukuduru struct drm_plane *cursor) 131325fdd593SJeykumar Sankaran { 131425fdd593SJeykumar Sankaran struct drm_crtc *crtc = NULL; 131525fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = NULL; 131625fdd593SJeykumar Sankaran struct msm_drm_private *priv = NULL; 131725fdd593SJeykumar Sankaran struct dpu_kms *kms = NULL; 1318c17aeda0SJordan Crouse int i; 131925fdd593SJeykumar Sankaran 132025fdd593SJeykumar Sankaran priv = dev->dev_private; 132125fdd593SJeykumar Sankaran kms = to_dpu_kms(priv->kms); 132225fdd593SJeykumar Sankaran 132325fdd593SJeykumar Sankaran dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL); 132425fdd593SJeykumar Sankaran if (!dpu_crtc) 132525fdd593SJeykumar Sankaran return ERR_PTR(-ENOMEM); 132625fdd593SJeykumar Sankaran 132725fdd593SJeykumar Sankaran crtc = &dpu_crtc->base; 132825fdd593SJeykumar Sankaran crtc->dev = dev; 132925fdd593SJeykumar Sankaran 133025fdd593SJeykumar Sankaran spin_lock_init(&dpu_crtc->spin_lock); 133125fdd593SJeykumar Sankaran atomic_set(&dpu_crtc->frame_pending, 0); 133225fdd593SJeykumar Sankaran 133325fdd593SJeykumar Sankaran init_completion(&dpu_crtc->frame_done_comp); 133425fdd593SJeykumar Sankaran 133525fdd593SJeykumar Sankaran INIT_LIST_HEAD(&dpu_crtc->frame_event_list); 133625fdd593SJeykumar Sankaran 133725fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(dpu_crtc->frame_events); i++) { 133825fdd593SJeykumar Sankaran INIT_LIST_HEAD(&dpu_crtc->frame_events[i].list); 133925fdd593SJeykumar Sankaran list_add(&dpu_crtc->frame_events[i].list, 134025fdd593SJeykumar Sankaran &dpu_crtc->frame_event_list); 134125fdd593SJeykumar Sankaran kthread_init_work(&dpu_crtc->frame_events[i].work, 134225fdd593SJeykumar Sankaran dpu_crtc_frame_event_work); 134325fdd593SJeykumar Sankaran } 134425fdd593SJeykumar Sankaran 134507ca1fc0SSravanthi Kollukuduru drm_crtc_init_with_planes(dev, crtc, plane, cursor, &dpu_crtc_funcs, 134625fdd593SJeykumar Sankaran NULL); 134725fdd593SJeykumar Sankaran 134825fdd593SJeykumar Sankaran drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs); 134925fdd593SJeykumar Sankaran 135025fdd593SJeykumar Sankaran /* save user friendly CRTC name for later */ 135125fdd593SJeykumar Sankaran snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id); 135225fdd593SJeykumar Sankaran 135325fdd593SJeykumar Sankaran /* initialize event handling */ 1354c17aeda0SJordan Crouse spin_lock_init(&dpu_crtc->event_lock); 135525fdd593SJeykumar Sankaran 135625fdd593SJeykumar Sankaran DPU_DEBUG("%s: successfully initialized crtc\n", dpu_crtc->name); 135725fdd593SJeykumar Sankaran return crtc; 135825fdd593SJeykumar Sankaran } 1359