125fdd593SJeykumar Sankaran /* 225fdd593SJeykumar Sankaran * Copyright (c) 2014-2018 The Linux Foundation. All rights reserved. 325fdd593SJeykumar Sankaran * Copyright (C) 2013 Red Hat 425fdd593SJeykumar Sankaran * Author: Rob Clark <robdclark@gmail.com> 525fdd593SJeykumar Sankaran * 625fdd593SJeykumar Sankaran * This program is free software; you can redistribute it and/or modify it 725fdd593SJeykumar Sankaran * under the terms of the GNU General Public License version 2 as published by 825fdd593SJeykumar Sankaran * the Free Software Foundation. 925fdd593SJeykumar Sankaran * 1025fdd593SJeykumar Sankaran * This program is distributed in the hope that it will be useful, but WITHOUT 1125fdd593SJeykumar Sankaran * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1225fdd593SJeykumar Sankaran * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1325fdd593SJeykumar Sankaran * more details. 1425fdd593SJeykumar Sankaran * 1525fdd593SJeykumar Sankaran * You should have received a copy of the GNU General Public License along with 1625fdd593SJeykumar Sankaran * this program. If not, see <http://www.gnu.org/licenses/>. 1725fdd593SJeykumar Sankaran */ 1825fdd593SJeykumar Sankaran 1925fdd593SJeykumar Sankaran #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 2025fdd593SJeykumar Sankaran #include <linux/sort.h> 2125fdd593SJeykumar Sankaran #include <linux/debugfs.h> 2225fdd593SJeykumar Sankaran #include <linux/ktime.h> 2325fdd593SJeykumar Sankaran #include <drm/drm_mode.h> 2425fdd593SJeykumar Sankaran #include <drm/drm_crtc.h> 2525fdd593SJeykumar Sankaran #include <drm/drm_crtc_helper.h> 2625fdd593SJeykumar Sankaran #include <drm/drm_flip_work.h> 2725fdd593SJeykumar Sankaran #include <drm/drm_rect.h> 2825fdd593SJeykumar Sankaran 2925fdd593SJeykumar Sankaran #include "dpu_kms.h" 3025fdd593SJeykumar Sankaran #include "dpu_hw_lm.h" 3125fdd593SJeykumar Sankaran #include "dpu_hw_ctl.h" 3225fdd593SJeykumar Sankaran #include "dpu_crtc.h" 3325fdd593SJeykumar Sankaran #include "dpu_plane.h" 3425fdd593SJeykumar Sankaran #include "dpu_encoder.h" 3525fdd593SJeykumar Sankaran #include "dpu_vbif.h" 3625fdd593SJeykumar Sankaran #include "dpu_core_perf.h" 3725fdd593SJeykumar Sankaran #include "dpu_trace.h" 3825fdd593SJeykumar Sankaran 3925fdd593SJeykumar Sankaran #define DPU_DRM_BLEND_OP_NOT_DEFINED 0 4025fdd593SJeykumar Sankaran #define DPU_DRM_BLEND_OP_OPAQUE 1 4125fdd593SJeykumar Sankaran #define DPU_DRM_BLEND_OP_PREMULTIPLIED 2 4225fdd593SJeykumar Sankaran #define DPU_DRM_BLEND_OP_COVERAGE 3 4325fdd593SJeykumar Sankaran #define DPU_DRM_BLEND_OP_MAX 4 4425fdd593SJeykumar Sankaran 4525fdd593SJeykumar Sankaran /* layer mixer index on dpu_crtc */ 4625fdd593SJeykumar Sankaran #define LEFT_MIXER 0 4725fdd593SJeykumar Sankaran #define RIGHT_MIXER 1 4825fdd593SJeykumar Sankaran 4942331668SJeykumar Sankaran static inline int _dpu_crtc_get_mixer_width(struct dpu_crtc_state *cstate, 5042331668SJeykumar Sankaran struct drm_display_mode *mode) 5142331668SJeykumar Sankaran { 5242331668SJeykumar Sankaran return mode->hdisplay / cstate->num_mixers; 5342331668SJeykumar Sankaran } 5442331668SJeykumar Sankaran 5558fba464SSean Paul static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc) 5625fdd593SJeykumar Sankaran { 5704b96b63SBruce Wang struct msm_drm_private *priv = crtc->dev->dev_private; 5825fdd593SJeykumar Sankaran 5925fdd593SJeykumar Sankaran return to_dpu_kms(priv->kms); 6025fdd593SJeykumar Sankaran } 6125fdd593SJeykumar Sankaran 6225fdd593SJeykumar Sankaran static void dpu_crtc_destroy(struct drm_crtc *crtc) 6325fdd593SJeykumar Sankaran { 6425fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 6525fdd593SJeykumar Sankaran 6625fdd593SJeykumar Sankaran DPU_DEBUG("\n"); 6725fdd593SJeykumar Sankaran 6825fdd593SJeykumar Sankaran if (!crtc) 6925fdd593SJeykumar Sankaran return; 7025fdd593SJeykumar Sankaran 7125fdd593SJeykumar Sankaran drm_crtc_cleanup(crtc); 7225fdd593SJeykumar Sankaran mutex_destroy(&dpu_crtc->crtc_lock); 7325fdd593SJeykumar Sankaran kfree(dpu_crtc); 7425fdd593SJeykumar Sankaran } 7525fdd593SJeykumar Sankaran 7625fdd593SJeykumar Sankaran static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, 7774593a28SSravanthi Kollukuduru struct dpu_plane_state *pstate, struct dpu_format *format) 7825fdd593SJeykumar Sankaran { 7925fdd593SJeykumar Sankaran struct dpu_hw_mixer *lm = mixer->hw_lm; 8074593a28SSravanthi Kollukuduru uint32_t blend_op; 8174593a28SSravanthi Kollukuduru struct drm_format_name_buf format_name; 8225fdd593SJeykumar Sankaran 8325fdd593SJeykumar Sankaran /* default to opaque blending */ 8474593a28SSravanthi Kollukuduru blend_op = DPU_BLEND_FG_ALPHA_FG_CONST | 8574593a28SSravanthi Kollukuduru DPU_BLEND_BG_ALPHA_BG_CONST; 8674593a28SSravanthi Kollukuduru 8774593a28SSravanthi Kollukuduru if (format->alpha_enable) { 8874593a28SSravanthi Kollukuduru /* coverage blending */ 8974593a28SSravanthi Kollukuduru blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL | 9074593a28SSravanthi Kollukuduru DPU_BLEND_BG_ALPHA_FG_PIXEL | 9174593a28SSravanthi Kollukuduru DPU_BLEND_BG_INV_ALPHA; 9274593a28SSravanthi Kollukuduru } 9374593a28SSravanthi Kollukuduru 9474593a28SSravanthi Kollukuduru lm->ops.setup_blend_config(lm, pstate->stage, 9574593a28SSravanthi Kollukuduru 0xFF, 0, blend_op); 9674593a28SSravanthi Kollukuduru 9774593a28SSravanthi Kollukuduru DPU_DEBUG("format:%s, alpha_en:%u blend_op:0x%x\n", 9874593a28SSravanthi Kollukuduru drm_get_format_name(format->base.pixel_format, &format_name), 9974593a28SSravanthi Kollukuduru format->alpha_enable, blend_op); 10025fdd593SJeykumar Sankaran } 10125fdd593SJeykumar Sankaran 10225fdd593SJeykumar Sankaran static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) 10325fdd593SJeykumar Sankaran { 10425fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 10525fdd593SJeykumar Sankaran struct dpu_crtc_state *crtc_state; 10625fdd593SJeykumar Sankaran int lm_idx, lm_horiz_position; 10725fdd593SJeykumar Sankaran 10825fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 10925fdd593SJeykumar Sankaran crtc_state = to_dpu_crtc_state(crtc->state); 11025fdd593SJeykumar Sankaran 11125fdd593SJeykumar Sankaran lm_horiz_position = 0; 1129222cdd2SJeykumar Sankaran for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) { 11325fdd593SJeykumar Sankaran const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx]; 1149222cdd2SJeykumar Sankaran struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm; 11525fdd593SJeykumar Sankaran struct dpu_hw_mixer_cfg cfg; 11625fdd593SJeykumar Sankaran 11725fdd593SJeykumar Sankaran if (!lm_roi || !drm_rect_visible(lm_roi)) 11825fdd593SJeykumar Sankaran continue; 11925fdd593SJeykumar Sankaran 12025fdd593SJeykumar Sankaran cfg.out_width = drm_rect_width(lm_roi); 12125fdd593SJeykumar Sankaran cfg.out_height = drm_rect_height(lm_roi); 12225fdd593SJeykumar Sankaran cfg.right_mixer = lm_horiz_position++; 12325fdd593SJeykumar Sankaran cfg.flags = 0; 12425fdd593SJeykumar Sankaran hw_lm->ops.setup_mixer_out(hw_lm, &cfg); 12525fdd593SJeykumar Sankaran } 12625fdd593SJeykumar Sankaran } 12725fdd593SJeykumar Sankaran 12825fdd593SJeykumar Sankaran static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, 12925fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer) 13025fdd593SJeykumar Sankaran { 13125fdd593SJeykumar Sankaran struct drm_plane *plane; 13225fdd593SJeykumar Sankaran struct drm_framebuffer *fb; 13325fdd593SJeykumar Sankaran struct drm_plane_state *state; 13404b96b63SBruce Wang struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 13525fdd593SJeykumar Sankaran struct dpu_plane_state *pstate = NULL; 13625fdd593SJeykumar Sankaran struct dpu_format *format; 13704b96b63SBruce Wang struct dpu_hw_ctl *ctl = mixer->lm_ctl; 13804b96b63SBruce Wang struct dpu_hw_stage_cfg *stage_cfg = &dpu_crtc->stage_cfg; 13925fdd593SJeykumar Sankaran 14025fdd593SJeykumar Sankaran u32 flush_mask; 14125fdd593SJeykumar Sankaran uint32_t stage_idx, lm_idx; 14225fdd593SJeykumar Sankaran int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 }; 14325fdd593SJeykumar Sankaran bool bg_alpha_enable = false; 14425fdd593SJeykumar Sankaran 14525fdd593SJeykumar Sankaran drm_atomic_crtc_for_each_plane(plane, crtc) { 14625fdd593SJeykumar Sankaran state = plane->state; 14725fdd593SJeykumar Sankaran if (!state) 14825fdd593SJeykumar Sankaran continue; 14925fdd593SJeykumar Sankaran 15025fdd593SJeykumar Sankaran pstate = to_dpu_plane_state(state); 15125fdd593SJeykumar Sankaran fb = state->fb; 15225fdd593SJeykumar Sankaran 15325fdd593SJeykumar Sankaran dpu_plane_get_ctl_flush(plane, ctl, &flush_mask); 15425fdd593SJeykumar Sankaran 15525fdd593SJeykumar Sankaran DPU_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n", 15625fdd593SJeykumar Sankaran crtc->base.id, 15725fdd593SJeykumar Sankaran pstate->stage, 15825fdd593SJeykumar Sankaran plane->base.id, 15925fdd593SJeykumar Sankaran dpu_plane_pipe(plane) - SSPP_VIG0, 16025fdd593SJeykumar Sankaran state->fb ? state->fb->base.id : -1); 16125fdd593SJeykumar Sankaran 16225fdd593SJeykumar Sankaran format = to_dpu_format(msm_framebuffer_format(pstate->base.fb)); 16325fdd593SJeykumar Sankaran 16425fdd593SJeykumar Sankaran if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) 16525fdd593SJeykumar Sankaran bg_alpha_enable = true; 16625fdd593SJeykumar Sankaran 16725fdd593SJeykumar Sankaran stage_idx = zpos_cnt[pstate->stage]++; 16825fdd593SJeykumar Sankaran stage_cfg->stage[pstate->stage][stage_idx] = 16925fdd593SJeykumar Sankaran dpu_plane_pipe(plane); 17025fdd593SJeykumar Sankaran stage_cfg->multirect_index[pstate->stage][stage_idx] = 17125fdd593SJeykumar Sankaran pstate->multirect_index; 17225fdd593SJeykumar Sankaran 17325fdd593SJeykumar Sankaran trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), 17425fdd593SJeykumar Sankaran state, pstate, stage_idx, 17525fdd593SJeykumar Sankaran dpu_plane_pipe(plane) - SSPP_VIG0, 17625fdd593SJeykumar Sankaran format->base.pixel_format, 17725fdd593SJeykumar Sankaran fb ? fb->modifier : 0); 17825fdd593SJeykumar Sankaran 17925fdd593SJeykumar Sankaran /* blend config update */ 1809222cdd2SJeykumar Sankaran for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) { 18174593a28SSravanthi Kollukuduru _dpu_crtc_setup_blend_cfg(mixer + lm_idx, 18274593a28SSravanthi Kollukuduru pstate, format); 18325fdd593SJeykumar Sankaran 18425fdd593SJeykumar Sankaran mixer[lm_idx].flush_mask |= flush_mask; 18525fdd593SJeykumar Sankaran 18625fdd593SJeykumar Sankaran if (bg_alpha_enable && !format->alpha_enable) 18725fdd593SJeykumar Sankaran mixer[lm_idx].mixer_op_mode = 0; 18825fdd593SJeykumar Sankaran else 18925fdd593SJeykumar Sankaran mixer[lm_idx].mixer_op_mode |= 19025fdd593SJeykumar Sankaran 1 << pstate->stage; 19125fdd593SJeykumar Sankaran } 19225fdd593SJeykumar Sankaran } 19325fdd593SJeykumar Sankaran 19425fdd593SJeykumar Sankaran _dpu_crtc_program_lm_output_roi(crtc); 19525fdd593SJeykumar Sankaran } 19625fdd593SJeykumar Sankaran 19725fdd593SJeykumar Sankaran /** 19825fdd593SJeykumar Sankaran * _dpu_crtc_blend_setup - configure crtc mixers 19925fdd593SJeykumar Sankaran * @crtc: Pointer to drm crtc structure 20025fdd593SJeykumar Sankaran */ 20125fdd593SJeykumar Sankaran static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) 20225fdd593SJeykumar Sankaran { 20304b96b63SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 20404b96b63SBruce Wang struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 20504b96b63SBruce Wang struct dpu_crtc_mixer *mixer = cstate->mixers; 20625fdd593SJeykumar Sankaran struct dpu_hw_ctl *ctl; 20725fdd593SJeykumar Sankaran struct dpu_hw_mixer *lm; 20825fdd593SJeykumar Sankaran int i; 20925fdd593SJeykumar Sankaran 21025fdd593SJeykumar Sankaran DPU_DEBUG("%s\n", dpu_crtc->name); 21125fdd593SJeykumar Sankaran 2129222cdd2SJeykumar Sankaran for (i = 0; i < cstate->num_mixers; i++) { 213cf6916f4SJeykumar Sankaran if (!mixer[i].hw_lm || !mixer[i].lm_ctl) { 21425fdd593SJeykumar Sankaran DPU_ERROR("invalid lm or ctl assigned to mixer\n"); 21525fdd593SJeykumar Sankaran return; 21625fdd593SJeykumar Sankaran } 21725fdd593SJeykumar Sankaran mixer[i].mixer_op_mode = 0; 21825fdd593SJeykumar Sankaran mixer[i].flush_mask = 0; 219cf6916f4SJeykumar Sankaran if (mixer[i].lm_ctl->ops.clear_all_blendstages) 220cf6916f4SJeykumar Sankaran mixer[i].lm_ctl->ops.clear_all_blendstages( 221cf6916f4SJeykumar Sankaran mixer[i].lm_ctl); 22225fdd593SJeykumar Sankaran } 22325fdd593SJeykumar Sankaran 22425fdd593SJeykumar Sankaran /* initialize stage cfg */ 22525fdd593SJeykumar Sankaran memset(&dpu_crtc->stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg)); 22625fdd593SJeykumar Sankaran 22725fdd593SJeykumar Sankaran _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer); 22825fdd593SJeykumar Sankaran 2299222cdd2SJeykumar Sankaran for (i = 0; i < cstate->num_mixers; i++) { 230cf6916f4SJeykumar Sankaran ctl = mixer[i].lm_ctl; 23125fdd593SJeykumar Sankaran lm = mixer[i].hw_lm; 23225fdd593SJeykumar Sankaran 23325fdd593SJeykumar Sankaran lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode); 23425fdd593SJeykumar Sankaran 23525fdd593SJeykumar Sankaran mixer[i].flush_mask |= ctl->ops.get_bitmask_mixer(ctl, 23625fdd593SJeykumar Sankaran mixer[i].hw_lm->idx); 23725fdd593SJeykumar Sankaran 23825fdd593SJeykumar Sankaran /* stage config flush mask */ 23925fdd593SJeykumar Sankaran ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); 24025fdd593SJeykumar Sankaran 24125fdd593SJeykumar Sankaran DPU_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n", 24225fdd593SJeykumar Sankaran mixer[i].hw_lm->idx - LM_0, 24325fdd593SJeykumar Sankaran mixer[i].mixer_op_mode, 24425fdd593SJeykumar Sankaran ctl->idx - CTL_0, 24525fdd593SJeykumar Sankaran mixer[i].flush_mask); 24625fdd593SJeykumar Sankaran 24725fdd593SJeykumar Sankaran ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, 24825fdd593SJeykumar Sankaran &dpu_crtc->stage_cfg); 24925fdd593SJeykumar Sankaran } 25025fdd593SJeykumar Sankaran } 25125fdd593SJeykumar Sankaran 25225fdd593SJeykumar Sankaran /** 25325fdd593SJeykumar Sankaran * _dpu_crtc_complete_flip - signal pending page_flip events 25425fdd593SJeykumar Sankaran * Any pending vblank events are added to the vblank_event_list 25525fdd593SJeykumar Sankaran * so that the next vblank interrupt shall signal them. 25625fdd593SJeykumar Sankaran * However PAGE_FLIP events are not handled through the vblank_event_list. 25725fdd593SJeykumar Sankaran * This API signals any pending PAGE_FLIP events requested through 25825fdd593SJeykumar Sankaran * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the dpu_crtc->event. 25925fdd593SJeykumar Sankaran * @crtc: Pointer to drm crtc structure 26025fdd593SJeykumar Sankaran */ 26125fdd593SJeykumar Sankaran static void _dpu_crtc_complete_flip(struct drm_crtc *crtc) 26225fdd593SJeykumar Sankaran { 26325fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 26425fdd593SJeykumar Sankaran struct drm_device *dev = crtc->dev; 26525fdd593SJeykumar Sankaran unsigned long flags; 26625fdd593SJeykumar Sankaran 26725fdd593SJeykumar Sankaran spin_lock_irqsave(&dev->event_lock, flags); 26825fdd593SJeykumar Sankaran if (dpu_crtc->event) { 26925fdd593SJeykumar Sankaran DRM_DEBUG_VBL("%s: send event: %pK\n", dpu_crtc->name, 27025fdd593SJeykumar Sankaran dpu_crtc->event); 27125fdd593SJeykumar Sankaran trace_dpu_crtc_complete_flip(DRMID(crtc)); 27225fdd593SJeykumar Sankaran drm_crtc_send_vblank_event(crtc, dpu_crtc->event); 27325fdd593SJeykumar Sankaran dpu_crtc->event = NULL; 27425fdd593SJeykumar Sankaran } 27525fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dev->event_lock, flags); 27625fdd593SJeykumar Sankaran } 27725fdd593SJeykumar Sankaran 27825fdd593SJeykumar Sankaran enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc) 27925fdd593SJeykumar Sankaran { 28025fdd593SJeykumar Sankaran struct drm_encoder *encoder; 28125fdd593SJeykumar Sankaran 28225fdd593SJeykumar Sankaran if (!crtc || !crtc->dev) { 28325fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 28425fdd593SJeykumar Sankaran return INTF_MODE_NONE; 28525fdd593SJeykumar Sankaran } 28625fdd593SJeykumar Sankaran 28725fdd593SJeykumar Sankaran drm_for_each_encoder(encoder, crtc->dev) 28825fdd593SJeykumar Sankaran if (encoder->crtc == crtc) 28925fdd593SJeykumar Sankaran return dpu_encoder_get_intf_mode(encoder); 29025fdd593SJeykumar Sankaran 29125fdd593SJeykumar Sankaran return INTF_MODE_NONE; 29225fdd593SJeykumar Sankaran } 29325fdd593SJeykumar Sankaran 29425fdd593SJeykumar Sankaran static void dpu_crtc_vblank_cb(void *data) 29525fdd593SJeykumar Sankaran { 29625fdd593SJeykumar Sankaran struct drm_crtc *crtc = (struct drm_crtc *)data; 29725fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 29825fdd593SJeykumar Sankaran 29925fdd593SJeykumar Sankaran /* keep statistics on vblank callback - with auto reset via debugfs */ 30025fdd593SJeykumar Sankaran if (ktime_compare(dpu_crtc->vblank_cb_time, ktime_set(0, 0)) == 0) 30125fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_time = ktime_get(); 30225fdd593SJeykumar Sankaran else 30325fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_count++; 30425fdd593SJeykumar Sankaran _dpu_crtc_complete_flip(crtc); 30525fdd593SJeykumar Sankaran drm_crtc_handle_vblank(crtc); 30625fdd593SJeykumar Sankaran trace_dpu_crtc_vblank_cb(DRMID(crtc)); 30725fdd593SJeykumar Sankaran } 30825fdd593SJeykumar Sankaran 30925fdd593SJeykumar Sankaran static void dpu_crtc_frame_event_work(struct kthread_work *work) 31025fdd593SJeykumar Sankaran { 31104b96b63SBruce Wang struct dpu_crtc_frame_event *fevent = container_of(work, 31204b96b63SBruce Wang struct dpu_crtc_frame_event, work); 31304b96b63SBruce Wang struct drm_crtc *crtc = fevent->crtc; 31404b96b63SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 31525fdd593SJeykumar Sankaran unsigned long flags; 31625fdd593SJeykumar Sankaran bool frame_done = false; 31725fdd593SJeykumar Sankaran 31825fdd593SJeykumar Sankaran DPU_ATRACE_BEGIN("crtc_frame_event"); 31925fdd593SJeykumar Sankaran 32025fdd593SJeykumar Sankaran DRM_DEBUG_KMS("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event, 32125fdd593SJeykumar Sankaran ktime_to_ns(fevent->ts)); 32225fdd593SJeykumar Sankaran 32325fdd593SJeykumar Sankaran if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE 32425fdd593SJeykumar Sankaran | DPU_ENCODER_FRAME_EVENT_ERROR 32525fdd593SJeykumar Sankaran | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) { 32625fdd593SJeykumar Sankaran 32725fdd593SJeykumar Sankaran if (atomic_read(&dpu_crtc->frame_pending) < 1) { 32825fdd593SJeykumar Sankaran /* this should not happen */ 32925fdd593SJeykumar Sankaran DRM_ERROR("crtc%d ev:%u ts:%lld frame_pending:%d\n", 33025fdd593SJeykumar Sankaran crtc->base.id, 33125fdd593SJeykumar Sankaran fevent->event, 33225fdd593SJeykumar Sankaran ktime_to_ns(fevent->ts), 33325fdd593SJeykumar Sankaran atomic_read(&dpu_crtc->frame_pending)); 33425fdd593SJeykumar Sankaran } else if (atomic_dec_return(&dpu_crtc->frame_pending) == 0) { 33525fdd593SJeykumar Sankaran /* release bandwidth and other resources */ 33625fdd593SJeykumar Sankaran trace_dpu_crtc_frame_event_done(DRMID(crtc), 33725fdd593SJeykumar Sankaran fevent->event); 33825fdd593SJeykumar Sankaran dpu_core_perf_crtc_release_bw(crtc); 33925fdd593SJeykumar Sankaran } else { 34025fdd593SJeykumar Sankaran trace_dpu_crtc_frame_event_more_pending(DRMID(crtc), 34125fdd593SJeykumar Sankaran fevent->event); 34225fdd593SJeykumar Sankaran } 34325fdd593SJeykumar Sankaran 34425fdd593SJeykumar Sankaran if (fevent->event & DPU_ENCODER_FRAME_EVENT_DONE) 34525fdd593SJeykumar Sankaran dpu_core_perf_crtc_update(crtc, 0, false); 34625fdd593SJeykumar Sankaran 34725fdd593SJeykumar Sankaran if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE 34825fdd593SJeykumar Sankaran | DPU_ENCODER_FRAME_EVENT_ERROR)) 34925fdd593SJeykumar Sankaran frame_done = true; 35025fdd593SJeykumar Sankaran } 35125fdd593SJeykumar Sankaran 35225fdd593SJeykumar Sankaran if (fevent->event & DPU_ENCODER_FRAME_EVENT_PANEL_DEAD) 35325fdd593SJeykumar Sankaran DPU_ERROR("crtc%d ts:%lld received panel dead event\n", 35425fdd593SJeykumar Sankaran crtc->base.id, ktime_to_ns(fevent->ts)); 35525fdd593SJeykumar Sankaran 35625fdd593SJeykumar Sankaran if (frame_done) 35725fdd593SJeykumar Sankaran complete_all(&dpu_crtc->frame_done_comp); 35825fdd593SJeykumar Sankaran 35925fdd593SJeykumar Sankaran spin_lock_irqsave(&dpu_crtc->spin_lock, flags); 36025fdd593SJeykumar Sankaran list_add_tail(&fevent->list, &dpu_crtc->frame_event_list); 36125fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags); 36225fdd593SJeykumar Sankaran DPU_ATRACE_END("crtc_frame_event"); 36325fdd593SJeykumar Sankaran } 36425fdd593SJeykumar Sankaran 36525fdd593SJeykumar Sankaran /* 36625fdd593SJeykumar Sankaran * dpu_crtc_frame_event_cb - crtc frame event callback API. CRTC module 36725fdd593SJeykumar Sankaran * registers this API to encoder for all frame event callbacks like 36825fdd593SJeykumar Sankaran * frame_error, frame_done, idle_timeout, etc. Encoder may call different events 36925fdd593SJeykumar Sankaran * from different context - IRQ, user thread, commit_thread, etc. Each event 37025fdd593SJeykumar Sankaran * should be carefully reviewed and should be processed in proper task context 37125fdd593SJeykumar Sankaran * to avoid schedulin delay or properly manage the irq context's bottom half 37225fdd593SJeykumar Sankaran * processing. 37325fdd593SJeykumar Sankaran */ 37425fdd593SJeykumar Sankaran static void dpu_crtc_frame_event_cb(void *data, u32 event) 37525fdd593SJeykumar Sankaran { 37625fdd593SJeykumar Sankaran struct drm_crtc *crtc = (struct drm_crtc *)data; 37725fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 37825fdd593SJeykumar Sankaran struct msm_drm_private *priv; 37925fdd593SJeykumar Sankaran struct dpu_crtc_frame_event *fevent; 38025fdd593SJeykumar Sankaran unsigned long flags; 38125fdd593SJeykumar Sankaran u32 crtc_id; 38225fdd593SJeykumar Sankaran 38325fdd593SJeykumar Sankaran /* Nothing to do on idle event */ 38425fdd593SJeykumar Sankaran if (event & DPU_ENCODER_FRAME_EVENT_IDLE) 38525fdd593SJeykumar Sankaran return; 38625fdd593SJeykumar Sankaran 38725fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 38825fdd593SJeykumar Sankaran priv = crtc->dev->dev_private; 38925fdd593SJeykumar Sankaran crtc_id = drm_crtc_index(crtc); 39025fdd593SJeykumar Sankaran 39125fdd593SJeykumar Sankaran trace_dpu_crtc_frame_event_cb(DRMID(crtc), event); 39225fdd593SJeykumar Sankaran 39325fdd593SJeykumar Sankaran spin_lock_irqsave(&dpu_crtc->spin_lock, flags); 39425fdd593SJeykumar Sankaran fevent = list_first_entry_or_null(&dpu_crtc->frame_event_list, 39525fdd593SJeykumar Sankaran struct dpu_crtc_frame_event, list); 39625fdd593SJeykumar Sankaran if (fevent) 39725fdd593SJeykumar Sankaran list_del_init(&fevent->list); 39825fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags); 39925fdd593SJeykumar Sankaran 40025fdd593SJeykumar Sankaran if (!fevent) { 40125fdd593SJeykumar Sankaran DRM_ERROR("crtc%d event %d overflow\n", crtc->base.id, event); 40225fdd593SJeykumar Sankaran return; 40325fdd593SJeykumar Sankaran } 40425fdd593SJeykumar Sankaran 40525fdd593SJeykumar Sankaran fevent->event = event; 40625fdd593SJeykumar Sankaran fevent->crtc = crtc; 40725fdd593SJeykumar Sankaran fevent->ts = ktime_get(); 40825fdd593SJeykumar Sankaran kthread_queue_work(&priv->event_thread[crtc_id].worker, &fevent->work); 40925fdd593SJeykumar Sankaran } 41025fdd593SJeykumar Sankaran 41125fdd593SJeykumar Sankaran void dpu_crtc_complete_commit(struct drm_crtc *crtc, 41225fdd593SJeykumar Sankaran struct drm_crtc_state *old_state) 41325fdd593SJeykumar Sankaran { 41425fdd593SJeykumar Sankaran if (!crtc || !crtc->state) { 41525fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 41625fdd593SJeykumar Sankaran return; 41725fdd593SJeykumar Sankaran } 41825fdd593SJeykumar Sankaran trace_dpu_crtc_complete_commit(DRMID(crtc)); 41925fdd593SJeykumar Sankaran } 42025fdd593SJeykumar Sankaran 42125fdd593SJeykumar Sankaran static void _dpu_crtc_setup_mixer_for_encoder( 42225fdd593SJeykumar Sankaran struct drm_crtc *crtc, 42325fdd593SJeykumar Sankaran struct drm_encoder *enc) 42425fdd593SJeykumar Sankaran { 4259222cdd2SJeykumar Sankaran struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 42625fdd593SJeykumar Sankaran struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); 42725fdd593SJeykumar Sankaran struct dpu_rm *rm = &dpu_kms->rm; 42825fdd593SJeykumar Sankaran struct dpu_crtc_mixer *mixer; 42925fdd593SJeykumar Sankaran struct dpu_hw_ctl *last_valid_ctl = NULL; 43025fdd593SJeykumar Sankaran int i; 43125fdd593SJeykumar Sankaran struct dpu_rm_hw_iter lm_iter, ctl_iter; 43225fdd593SJeykumar Sankaran 43325fdd593SJeykumar Sankaran dpu_rm_init_hw_iter(&lm_iter, enc->base.id, DPU_HW_BLK_LM); 43425fdd593SJeykumar Sankaran dpu_rm_init_hw_iter(&ctl_iter, enc->base.id, DPU_HW_BLK_CTL); 43525fdd593SJeykumar Sankaran 43625fdd593SJeykumar Sankaran /* Set up all the mixers and ctls reserved by this encoder */ 4379222cdd2SJeykumar Sankaran for (i = cstate->num_mixers; i < ARRAY_SIZE(cstate->mixers); i++) { 4389222cdd2SJeykumar Sankaran mixer = &cstate->mixers[i]; 43925fdd593SJeykumar Sankaran 44025fdd593SJeykumar Sankaran if (!dpu_rm_get_hw(rm, &lm_iter)) 44125fdd593SJeykumar Sankaran break; 44225fdd593SJeykumar Sankaran mixer->hw_lm = (struct dpu_hw_mixer *)lm_iter.hw; 44325fdd593SJeykumar Sankaran 44425fdd593SJeykumar Sankaran /* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */ 44525fdd593SJeykumar Sankaran if (!dpu_rm_get_hw(rm, &ctl_iter)) { 44625fdd593SJeykumar Sankaran DPU_DEBUG("no ctl assigned to lm %d, using previous\n", 44725fdd593SJeykumar Sankaran mixer->hw_lm->idx - LM_0); 448cf6916f4SJeykumar Sankaran mixer->lm_ctl = last_valid_ctl; 44925fdd593SJeykumar Sankaran } else { 450cf6916f4SJeykumar Sankaran mixer->lm_ctl = (struct dpu_hw_ctl *)ctl_iter.hw; 451cf6916f4SJeykumar Sankaran last_valid_ctl = mixer->lm_ctl; 45225fdd593SJeykumar Sankaran } 45325fdd593SJeykumar Sankaran 45425fdd593SJeykumar Sankaran /* Shouldn't happen, mixers are always >= ctls */ 455cf6916f4SJeykumar Sankaran if (!mixer->lm_ctl) { 45625fdd593SJeykumar Sankaran DPU_ERROR("no valid ctls found for lm %d\n", 45725fdd593SJeykumar Sankaran mixer->hw_lm->idx - LM_0); 45825fdd593SJeykumar Sankaran return; 45925fdd593SJeykumar Sankaran } 46025fdd593SJeykumar Sankaran 46125fdd593SJeykumar Sankaran mixer->encoder = enc; 46225fdd593SJeykumar Sankaran 4639222cdd2SJeykumar Sankaran cstate->num_mixers++; 46425fdd593SJeykumar Sankaran DPU_DEBUG("setup mixer %d: lm %d\n", 46525fdd593SJeykumar Sankaran i, mixer->hw_lm->idx - LM_0); 46625fdd593SJeykumar Sankaran DPU_DEBUG("setup mixer %d: ctl %d\n", 467cf6916f4SJeykumar Sankaran i, mixer->lm_ctl->idx - CTL_0); 46825fdd593SJeykumar Sankaran } 46925fdd593SJeykumar Sankaran } 47025fdd593SJeykumar Sankaran 47125fdd593SJeykumar Sankaran static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc) 47225fdd593SJeykumar Sankaran { 47325fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 47425fdd593SJeykumar Sankaran struct drm_encoder *enc; 47525fdd593SJeykumar Sankaran 47625fdd593SJeykumar Sankaran mutex_lock(&dpu_crtc->crtc_lock); 47725fdd593SJeykumar Sankaran /* Check for mixers on all encoders attached to this crtc */ 47825fdd593SJeykumar Sankaran list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) { 47925fdd593SJeykumar Sankaran if (enc->crtc != crtc) 48025fdd593SJeykumar Sankaran continue; 48125fdd593SJeykumar Sankaran 48225fdd593SJeykumar Sankaran _dpu_crtc_setup_mixer_for_encoder(crtc, enc); 48325fdd593SJeykumar Sankaran } 48425fdd593SJeykumar Sankaran 48525fdd593SJeykumar Sankaran mutex_unlock(&dpu_crtc->crtc_lock); 48625fdd593SJeykumar Sankaran } 48725fdd593SJeykumar Sankaran 48825fdd593SJeykumar Sankaran static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc, 48925fdd593SJeykumar Sankaran struct drm_crtc_state *state) 49025fdd593SJeykumar Sankaran { 49104b96b63SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 49204b96b63SBruce Wang struct dpu_crtc_state *cstate = to_dpu_crtc_state(state); 49304b96b63SBruce Wang struct drm_display_mode *adj_mode = &state->adjusted_mode; 49404b96b63SBruce Wang u32 crtc_split_width = _dpu_crtc_get_mixer_width(cstate, adj_mode); 49525fdd593SJeykumar Sankaran int i; 49625fdd593SJeykumar Sankaran 4979222cdd2SJeykumar Sankaran for (i = 0; i < cstate->num_mixers; i++) { 49825fdd593SJeykumar Sankaran struct drm_rect *r = &cstate->lm_bounds[i]; 49925fdd593SJeykumar Sankaran r->x1 = crtc_split_width * i; 50025fdd593SJeykumar Sankaran r->y1 = 0; 50125fdd593SJeykumar Sankaran r->x2 = r->x1 + crtc_split_width; 50225fdd593SJeykumar Sankaran r->y2 = dpu_crtc_get_mixer_height(dpu_crtc, cstate, adj_mode); 50325fdd593SJeykumar Sankaran 50425fdd593SJeykumar Sankaran trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i, r); 50525fdd593SJeykumar Sankaran } 50625fdd593SJeykumar Sankaran 50725fdd593SJeykumar Sankaran drm_mode_debug_printmodeline(adj_mode); 50825fdd593SJeykumar Sankaran } 50925fdd593SJeykumar Sankaran 51025fdd593SJeykumar Sankaran static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, 51125fdd593SJeykumar Sankaran struct drm_crtc_state *old_state) 51225fdd593SJeykumar Sankaran { 51325fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 5149222cdd2SJeykumar Sankaran struct dpu_crtc_state *cstate; 51525fdd593SJeykumar Sankaran struct drm_encoder *encoder; 51625fdd593SJeykumar Sankaran struct drm_device *dev; 51725fdd593SJeykumar Sankaran unsigned long flags; 51825fdd593SJeykumar Sankaran struct dpu_crtc_smmu_state_data *smmu_state; 51925fdd593SJeykumar Sankaran 52025fdd593SJeykumar Sankaran if (!crtc) { 52125fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 52225fdd593SJeykumar Sankaran return; 52325fdd593SJeykumar Sankaran } 52425fdd593SJeykumar Sankaran 52525fdd593SJeykumar Sankaran if (!crtc->state->enable) { 52625fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d -> enable %d, skip atomic_begin\n", 52725fdd593SJeykumar Sankaran crtc->base.id, crtc->state->enable); 52825fdd593SJeykumar Sankaran return; 52925fdd593SJeykumar Sankaran } 53025fdd593SJeykumar Sankaran 53125fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d\n", crtc->base.id); 53225fdd593SJeykumar Sankaran 53325fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 5349222cdd2SJeykumar Sankaran cstate = to_dpu_crtc_state(crtc->state); 53525fdd593SJeykumar Sankaran dev = crtc->dev; 53625fdd593SJeykumar Sankaran smmu_state = &dpu_crtc->smmu_state; 53725fdd593SJeykumar Sankaran 5389222cdd2SJeykumar Sankaran if (!cstate->num_mixers) { 53925fdd593SJeykumar Sankaran _dpu_crtc_setup_mixers(crtc); 54025fdd593SJeykumar Sankaran _dpu_crtc_setup_lm_bounds(crtc, crtc->state); 54125fdd593SJeykumar Sankaran } 54225fdd593SJeykumar Sankaran 54325fdd593SJeykumar Sankaran if (dpu_crtc->event) { 54425fdd593SJeykumar Sankaran WARN_ON(dpu_crtc->event); 54525fdd593SJeykumar Sankaran } else { 54625fdd593SJeykumar Sankaran spin_lock_irqsave(&dev->event_lock, flags); 54725fdd593SJeykumar Sankaran dpu_crtc->event = crtc->state->event; 54825fdd593SJeykumar Sankaran crtc->state->event = NULL; 54925fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dev->event_lock, flags); 55025fdd593SJeykumar Sankaran } 55125fdd593SJeykumar Sankaran 55225fdd593SJeykumar Sankaran list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 55325fdd593SJeykumar Sankaran if (encoder->crtc != crtc) 55425fdd593SJeykumar Sankaran continue; 55525fdd593SJeykumar Sankaran 55625fdd593SJeykumar Sankaran /* encoder will trigger pending mask now */ 55725fdd593SJeykumar Sankaran dpu_encoder_trigger_kickoff_pending(encoder); 55825fdd593SJeykumar Sankaran } 55925fdd593SJeykumar Sankaran 56025fdd593SJeykumar Sankaran /* 56125fdd593SJeykumar Sankaran * If no mixers have been allocated in dpu_crtc_atomic_check(), 56225fdd593SJeykumar Sankaran * it means we are trying to flush a CRTC whose state is disabled: 56325fdd593SJeykumar Sankaran * nothing else needs to be done. 56425fdd593SJeykumar Sankaran */ 5659222cdd2SJeykumar Sankaran if (unlikely(!cstate->num_mixers)) 56625fdd593SJeykumar Sankaran return; 56725fdd593SJeykumar Sankaran 56825fdd593SJeykumar Sankaran _dpu_crtc_blend_setup(crtc); 56925fdd593SJeykumar Sankaran 57025fdd593SJeykumar Sankaran /* 57125fdd593SJeykumar Sankaran * PP_DONE irq is only used by command mode for now. 57225fdd593SJeykumar Sankaran * It is better to request pending before FLUSH and START trigger 57325fdd593SJeykumar Sankaran * to make sure no pp_done irq missed. 57425fdd593SJeykumar Sankaran * This is safe because no pp_done will happen before SW trigger 57525fdd593SJeykumar Sankaran * in command mode. 57625fdd593SJeykumar Sankaran */ 57725fdd593SJeykumar Sankaran } 57825fdd593SJeykumar Sankaran 57925fdd593SJeykumar Sankaran static void dpu_crtc_atomic_flush(struct drm_crtc *crtc, 58025fdd593SJeykumar Sankaran struct drm_crtc_state *old_crtc_state) 58125fdd593SJeykumar Sankaran { 58225fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 58325fdd593SJeykumar Sankaran struct drm_device *dev; 58425fdd593SJeykumar Sankaran struct drm_plane *plane; 58525fdd593SJeykumar Sankaran struct msm_drm_private *priv; 58625fdd593SJeykumar Sankaran struct msm_drm_thread *event_thread; 58725fdd593SJeykumar Sankaran unsigned long flags; 58825fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 58925fdd593SJeykumar Sankaran 59025fdd593SJeykumar Sankaran if (!crtc->state->enable) { 59125fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d -> enable %d, skip atomic_flush\n", 59225fdd593SJeykumar Sankaran crtc->base.id, crtc->state->enable); 59325fdd593SJeykumar Sankaran return; 59425fdd593SJeykumar Sankaran } 59525fdd593SJeykumar Sankaran 59625fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d\n", crtc->base.id); 59725fdd593SJeykumar Sankaran 59825fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 59925fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(crtc->state); 60025fdd593SJeykumar Sankaran dev = crtc->dev; 60125fdd593SJeykumar Sankaran priv = dev->dev_private; 60225fdd593SJeykumar Sankaran 60325fdd593SJeykumar Sankaran if (crtc->index >= ARRAY_SIZE(priv->event_thread)) { 60425fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc index[%d]\n", crtc->index); 60525fdd593SJeykumar Sankaran return; 60625fdd593SJeykumar Sankaran } 60725fdd593SJeykumar Sankaran 60825fdd593SJeykumar Sankaran event_thread = &priv->event_thread[crtc->index]; 60925fdd593SJeykumar Sankaran 61025fdd593SJeykumar Sankaran if (dpu_crtc->event) { 61125fdd593SJeykumar Sankaran DPU_DEBUG("already received dpu_crtc->event\n"); 61225fdd593SJeykumar Sankaran } else { 61325fdd593SJeykumar Sankaran spin_lock_irqsave(&dev->event_lock, flags); 61425fdd593SJeykumar Sankaran dpu_crtc->event = crtc->state->event; 61525fdd593SJeykumar Sankaran crtc->state->event = NULL; 61625fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dev->event_lock, flags); 61725fdd593SJeykumar Sankaran } 61825fdd593SJeykumar Sankaran 61925fdd593SJeykumar Sankaran /* 62025fdd593SJeykumar Sankaran * If no mixers has been allocated in dpu_crtc_atomic_check(), 62125fdd593SJeykumar Sankaran * it means we are trying to flush a CRTC whose state is disabled: 62225fdd593SJeykumar Sankaran * nothing else needs to be done. 62325fdd593SJeykumar Sankaran */ 6249222cdd2SJeykumar Sankaran if (unlikely(!cstate->num_mixers)) 62525fdd593SJeykumar Sankaran return; 62625fdd593SJeykumar Sankaran 62725fdd593SJeykumar Sankaran /* 62825fdd593SJeykumar Sankaran * For planes without commit update, drm framework will not add 62925fdd593SJeykumar Sankaran * those planes to current state since hardware update is not 63025fdd593SJeykumar Sankaran * required. However, if those planes were power collapsed since 63125fdd593SJeykumar Sankaran * last commit cycle, driver has to restore the hardware state 63225fdd593SJeykumar Sankaran * of those planes explicitly here prior to plane flush. 63325fdd593SJeykumar Sankaran */ 63425fdd593SJeykumar Sankaran drm_atomic_crtc_for_each_plane(plane, crtc) 63525fdd593SJeykumar Sankaran dpu_plane_restore(plane); 63625fdd593SJeykumar Sankaran 63725fdd593SJeykumar Sankaran /* update performance setting before crtc kickoff */ 63825fdd593SJeykumar Sankaran dpu_core_perf_crtc_update(crtc, 1, false); 63925fdd593SJeykumar Sankaran 64025fdd593SJeykumar Sankaran /* 64125fdd593SJeykumar Sankaran * Final plane updates: Give each plane a chance to complete all 64225fdd593SJeykumar Sankaran * required writes/flushing before crtc's "flush 64325fdd593SJeykumar Sankaran * everything" call below. 64425fdd593SJeykumar Sankaran */ 64525fdd593SJeykumar Sankaran drm_atomic_crtc_for_each_plane(plane, crtc) { 64625fdd593SJeykumar Sankaran if (dpu_crtc->smmu_state.transition_error) 64725fdd593SJeykumar Sankaran dpu_plane_set_error(plane, true); 64825fdd593SJeykumar Sankaran dpu_plane_flush(plane); 64925fdd593SJeykumar Sankaran } 65025fdd593SJeykumar Sankaran 65125fdd593SJeykumar Sankaran /* Kickoff will be scheduled by outer layer */ 65225fdd593SJeykumar Sankaran } 65325fdd593SJeykumar Sankaran 65425fdd593SJeykumar Sankaran /** 65525fdd593SJeykumar Sankaran * dpu_crtc_destroy_state - state destroy hook 65625fdd593SJeykumar Sankaran * @crtc: drm CRTC 65725fdd593SJeykumar Sankaran * @state: CRTC state object to release 65825fdd593SJeykumar Sankaran */ 65925fdd593SJeykumar Sankaran static void dpu_crtc_destroy_state(struct drm_crtc *crtc, 66025fdd593SJeykumar Sankaran struct drm_crtc_state *state) 66125fdd593SJeykumar Sankaran { 66225fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 66325fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 66425fdd593SJeykumar Sankaran 66525fdd593SJeykumar Sankaran if (!crtc || !state) { 66625fdd593SJeykumar Sankaran DPU_ERROR("invalid argument(s)\n"); 66725fdd593SJeykumar Sankaran return; 66825fdd593SJeykumar Sankaran } 66925fdd593SJeykumar Sankaran 67025fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 67125fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(state); 67225fdd593SJeykumar Sankaran 67325fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d\n", crtc->base.id); 67425fdd593SJeykumar Sankaran 67525fdd593SJeykumar Sankaran __drm_atomic_helper_crtc_destroy_state(state); 67625fdd593SJeykumar Sankaran 67725fdd593SJeykumar Sankaran kfree(cstate); 67825fdd593SJeykumar Sankaran } 67925fdd593SJeykumar Sankaran 68025fdd593SJeykumar Sankaran static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc) 68125fdd593SJeykumar Sankaran { 68204b96b63SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 68325fdd593SJeykumar Sankaran int ret, rc = 0; 68425fdd593SJeykumar Sankaran 68525fdd593SJeykumar Sankaran if (!atomic_read(&dpu_crtc->frame_pending)) { 68625fdd593SJeykumar Sankaran DPU_DEBUG("no frames pending\n"); 68725fdd593SJeykumar Sankaran return 0; 68825fdd593SJeykumar Sankaran } 68925fdd593SJeykumar Sankaran 69025fdd593SJeykumar Sankaran DPU_ATRACE_BEGIN("frame done completion wait"); 69125fdd593SJeykumar Sankaran ret = wait_for_completion_timeout(&dpu_crtc->frame_done_comp, 69225fdd593SJeykumar Sankaran msecs_to_jiffies(DPU_FRAME_DONE_TIMEOUT)); 69325fdd593SJeykumar Sankaran if (!ret) { 69425fdd593SJeykumar Sankaran DRM_ERROR("frame done wait timed out, ret:%d\n", ret); 69525fdd593SJeykumar Sankaran rc = -ETIMEDOUT; 69625fdd593SJeykumar Sankaran } 69725fdd593SJeykumar Sankaran DPU_ATRACE_END("frame done completion wait"); 69825fdd593SJeykumar Sankaran 69925fdd593SJeykumar Sankaran return rc; 70025fdd593SJeykumar Sankaran } 70125fdd593SJeykumar Sankaran 70250bcc689SSean Paul void dpu_crtc_commit_kickoff(struct drm_crtc *crtc, bool async) 70325fdd593SJeykumar Sankaran { 70425fdd593SJeykumar Sankaran struct drm_encoder *encoder; 70504b96b63SBruce Wang struct drm_device *dev = crtc->dev; 70604b96b63SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 70704b96b63SBruce Wang struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); 70804b96b63SBruce Wang struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 70925fdd593SJeykumar Sankaran int ret; 71025fdd593SJeykumar Sankaran 71125fdd593SJeykumar Sankaran /* 71225fdd593SJeykumar Sankaran * If no mixers has been allocated in dpu_crtc_atomic_check(), 71325fdd593SJeykumar Sankaran * it means we are trying to start a CRTC whose state is disabled: 71425fdd593SJeykumar Sankaran * nothing else needs to be done. 71525fdd593SJeykumar Sankaran */ 7169222cdd2SJeykumar Sankaran if (unlikely(!cstate->num_mixers)) 71725fdd593SJeykumar Sankaran return; 71825fdd593SJeykumar Sankaran 71925fdd593SJeykumar Sankaran DPU_ATRACE_BEGIN("crtc_commit"); 72025fdd593SJeykumar Sankaran 72125fdd593SJeykumar Sankaran list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 72225fdd593SJeykumar Sankaran struct dpu_encoder_kickoff_params params = { 0 }; 72325fdd593SJeykumar Sankaran 72425fdd593SJeykumar Sankaran if (encoder->crtc != crtc) 72525fdd593SJeykumar Sankaran continue; 72625fdd593SJeykumar Sankaran 72725fdd593SJeykumar Sankaran /* 72825fdd593SJeykumar Sankaran * Encoder will flush/start now, unless it has a tx pending. 72925fdd593SJeykumar Sankaran * If so, it may delay and flush at an irq event (e.g. ppdone) 73025fdd593SJeykumar Sankaran */ 73150bcc689SSean Paul dpu_encoder_prepare_for_kickoff(encoder, ¶ms, async); 73225fdd593SJeykumar Sankaran } 73325fdd593SJeykumar Sankaran 73450bcc689SSean Paul 73550bcc689SSean Paul if (!async) { 73625fdd593SJeykumar Sankaran /* wait for frame_event_done completion */ 73725fdd593SJeykumar Sankaran DPU_ATRACE_BEGIN("wait_for_frame_done_event"); 73825fdd593SJeykumar Sankaran ret = _dpu_crtc_wait_for_frame_done(crtc); 73925fdd593SJeykumar Sankaran DPU_ATRACE_END("wait_for_frame_done_event"); 74025fdd593SJeykumar Sankaran if (ret) { 74125fdd593SJeykumar Sankaran DPU_ERROR("crtc%d wait for frame done failed;frame_pending%d\n", 74225fdd593SJeykumar Sankaran crtc->base.id, 74325fdd593SJeykumar Sankaran atomic_read(&dpu_crtc->frame_pending)); 74425fdd593SJeykumar Sankaran goto end; 74525fdd593SJeykumar Sankaran } 74625fdd593SJeykumar Sankaran 74725fdd593SJeykumar Sankaran if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) { 74825fdd593SJeykumar Sankaran /* acquire bandwidth and other resources */ 74925fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d first commit\n", crtc->base.id); 75025fdd593SJeykumar Sankaran } else 75125fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d commit\n", crtc->base.id); 75225fdd593SJeykumar Sankaran 75325fdd593SJeykumar Sankaran dpu_crtc->play_count++; 75450bcc689SSean Paul } 75525fdd593SJeykumar Sankaran 75625fdd593SJeykumar Sankaran dpu_vbif_clear_errors(dpu_kms); 75725fdd593SJeykumar Sankaran 75825fdd593SJeykumar Sankaran list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 75925fdd593SJeykumar Sankaran if (encoder->crtc != crtc) 76025fdd593SJeykumar Sankaran continue; 76125fdd593SJeykumar Sankaran 76250bcc689SSean Paul dpu_encoder_kickoff(encoder, async); 76325fdd593SJeykumar Sankaran } 76425fdd593SJeykumar Sankaran 76525fdd593SJeykumar Sankaran end: 76650bcc689SSean Paul if (!async) 76725fdd593SJeykumar Sankaran reinit_completion(&dpu_crtc->frame_done_comp); 76825fdd593SJeykumar Sankaran DPU_ATRACE_END("crtc_commit"); 76925fdd593SJeykumar Sankaran } 77025fdd593SJeykumar Sankaran 77125fdd593SJeykumar Sankaran /** 77225fdd593SJeykumar Sankaran * _dpu_crtc_vblank_enable_no_lock - update power resource and vblank request 77325fdd593SJeykumar Sankaran * @dpu_crtc: Pointer to dpu crtc structure 77425fdd593SJeykumar Sankaran * @enable: Whether to enable/disable vblanks 77525fdd593SJeykumar Sankaran */ 7761da03408SBruce Wang static void _dpu_crtc_vblank_enable_no_lock( 77725fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc, bool enable) 77825fdd593SJeykumar Sankaran { 7791da03408SBruce Wang struct drm_crtc *crtc = &dpu_crtc->base; 7801da03408SBruce Wang struct drm_device *dev = crtc->dev; 78125fdd593SJeykumar Sankaran struct drm_encoder *enc; 78225fdd593SJeykumar Sankaran 78325fdd593SJeykumar Sankaran if (enable) { 78425fdd593SJeykumar Sankaran /* drop lock since power crtc cb may try to re-acquire lock */ 78525fdd593SJeykumar Sankaran mutex_unlock(&dpu_crtc->crtc_lock); 7869a9ede3fSBruce Wang pm_runtime_get_sync(dev->dev); 78725fdd593SJeykumar Sankaran mutex_lock(&dpu_crtc->crtc_lock); 78825fdd593SJeykumar Sankaran 78925fdd593SJeykumar Sankaran list_for_each_entry(enc, &dev->mode_config.encoder_list, head) { 79025fdd593SJeykumar Sankaran if (enc->crtc != crtc) 79125fdd593SJeykumar Sankaran continue; 79225fdd593SJeykumar Sankaran 79325fdd593SJeykumar Sankaran trace_dpu_crtc_vblank_enable(DRMID(&dpu_crtc->base), 79425fdd593SJeykumar Sankaran DRMID(enc), enable, 79525fdd593SJeykumar Sankaran dpu_crtc); 79625fdd593SJeykumar Sankaran 79725fdd593SJeykumar Sankaran dpu_encoder_register_vblank_callback(enc, 79825fdd593SJeykumar Sankaran dpu_crtc_vblank_cb, (void *)crtc); 79925fdd593SJeykumar Sankaran } 80025fdd593SJeykumar Sankaran } else { 80125fdd593SJeykumar Sankaran list_for_each_entry(enc, &dev->mode_config.encoder_list, head) { 80225fdd593SJeykumar Sankaran if (enc->crtc != crtc) 80325fdd593SJeykumar Sankaran continue; 80425fdd593SJeykumar Sankaran 80525fdd593SJeykumar Sankaran trace_dpu_crtc_vblank_enable(DRMID(&dpu_crtc->base), 80625fdd593SJeykumar Sankaran DRMID(enc), enable, 80725fdd593SJeykumar Sankaran dpu_crtc); 80825fdd593SJeykumar Sankaran 80925fdd593SJeykumar Sankaran dpu_encoder_register_vblank_callback(enc, NULL, NULL); 81025fdd593SJeykumar Sankaran } 81125fdd593SJeykumar Sankaran 81225fdd593SJeykumar Sankaran /* drop lock since power crtc cb may try to re-acquire lock */ 81325fdd593SJeykumar Sankaran mutex_unlock(&dpu_crtc->crtc_lock); 8149a9ede3fSBruce Wang pm_runtime_put_sync(dev->dev); 81525fdd593SJeykumar Sankaran mutex_lock(&dpu_crtc->crtc_lock); 81625fdd593SJeykumar Sankaran } 81725fdd593SJeykumar Sankaran } 81825fdd593SJeykumar Sankaran 819ff5952a7SSean Paul static void dpu_crtc_reset(struct drm_crtc *crtc) 820ff5952a7SSean Paul { 821ff5952a7SSean Paul struct dpu_crtc_state *cstate; 822ff5952a7SSean Paul 823ff5952a7SSean Paul if (crtc->state) 824ff5952a7SSean Paul dpu_crtc_destroy_state(crtc, crtc->state); 825ff5952a7SSean Paul 826ff5952a7SSean Paul crtc->state = kzalloc(sizeof(*cstate), GFP_KERNEL); 827ff5952a7SSean Paul if (crtc->state) 828ff5952a7SSean Paul crtc->state->crtc = crtc; 829ff5952a7SSean Paul } 830ff5952a7SSean Paul 83125fdd593SJeykumar Sankaran /** 83225fdd593SJeykumar Sankaran * dpu_crtc_duplicate_state - state duplicate hook 83325fdd593SJeykumar Sankaran * @crtc: Pointer to drm crtc structure 83425fdd593SJeykumar Sankaran * @Returns: Pointer to new drm_crtc_state structure 83525fdd593SJeykumar Sankaran */ 83625fdd593SJeykumar Sankaran static struct drm_crtc_state *dpu_crtc_duplicate_state(struct drm_crtc *crtc) 83725fdd593SJeykumar Sankaran { 83825fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 83925fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate, *old_cstate; 84025fdd593SJeykumar Sankaran 84125fdd593SJeykumar Sankaran if (!crtc || !crtc->state) { 84225fdd593SJeykumar Sankaran DPU_ERROR("invalid argument(s)\n"); 84325fdd593SJeykumar Sankaran return NULL; 84425fdd593SJeykumar Sankaran } 84525fdd593SJeykumar Sankaran 84625fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 84725fdd593SJeykumar Sankaran old_cstate = to_dpu_crtc_state(crtc->state); 84825fdd593SJeykumar Sankaran cstate = kmemdup(old_cstate, sizeof(*old_cstate), GFP_KERNEL); 84925fdd593SJeykumar Sankaran if (!cstate) { 85025fdd593SJeykumar Sankaran DPU_ERROR("failed to allocate state\n"); 85125fdd593SJeykumar Sankaran return NULL; 85225fdd593SJeykumar Sankaran } 85325fdd593SJeykumar Sankaran 85425fdd593SJeykumar Sankaran /* duplicate base helper */ 85525fdd593SJeykumar Sankaran __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base); 85625fdd593SJeykumar Sankaran 85725fdd593SJeykumar Sankaran return &cstate->base; 85825fdd593SJeykumar Sankaran } 85925fdd593SJeykumar Sankaran 8603cf63cd5SSean Paul void dpu_crtc_runtime_resume(struct drm_crtc *crtc) 86125fdd593SJeykumar Sankaran { 86204b96b63SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 86325fdd593SJeykumar Sankaran struct drm_encoder *encoder; 86425fdd593SJeykumar Sankaran 86525fdd593SJeykumar Sankaran mutex_lock(&dpu_crtc->crtc_lock); 86625fdd593SJeykumar Sankaran 8673cf63cd5SSean Paul if (!dpu_crtc->enabled) 8683cf63cd5SSean Paul goto end; 8693cf63cd5SSean Paul 8703cf63cd5SSean Paul trace_dpu_crtc_runtime_resume(DRMID(crtc)); 87125fdd593SJeykumar Sankaran 87225fdd593SJeykumar Sankaran /* restore encoder; crtc will be programmed during commit */ 87325fdd593SJeykumar Sankaran drm_for_each_encoder(encoder, crtc->dev) { 87425fdd593SJeykumar Sankaran if (encoder->crtc != crtc) 87525fdd593SJeykumar Sankaran continue; 87625fdd593SJeykumar Sankaran 87725fdd593SJeykumar Sankaran dpu_encoder_virt_restore(encoder); 87825fdd593SJeykumar Sankaran } 87925fdd593SJeykumar Sankaran 8803cf63cd5SSean Paul end: 88125fdd593SJeykumar Sankaran mutex_unlock(&dpu_crtc->crtc_lock); 88225fdd593SJeykumar Sankaran } 88325fdd593SJeykumar Sankaran 88425fdd593SJeykumar Sankaran static void dpu_crtc_disable(struct drm_crtc *crtc) 88525fdd593SJeykumar Sankaran { 88625fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 88725fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 88825fdd593SJeykumar Sankaran struct drm_display_mode *mode; 88925fdd593SJeykumar Sankaran struct drm_encoder *encoder; 89025fdd593SJeykumar Sankaran struct msm_drm_private *priv; 8912f2eb723SRajesh Yadav unsigned long flags; 89225fdd593SJeykumar Sankaran 89325fdd593SJeykumar Sankaran if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) { 89425fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 89525fdd593SJeykumar Sankaran return; 89625fdd593SJeykumar Sankaran } 89725fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 89825fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(crtc->state); 89925fdd593SJeykumar Sankaran mode = &cstate->base.adjusted_mode; 90025fdd593SJeykumar Sankaran priv = crtc->dev->dev_private; 90125fdd593SJeykumar Sankaran 90225fdd593SJeykumar Sankaran DRM_DEBUG_KMS("crtc%d\n", crtc->base.id); 90325fdd593SJeykumar Sankaran 9042f2eb723SRajesh Yadav /* Disable/save vblank irq handling */ 9052f2eb723SRajesh Yadav drm_crtc_vblank_off(crtc); 9062f2eb723SRajesh Yadav 90725fdd593SJeykumar Sankaran mutex_lock(&dpu_crtc->crtc_lock); 90825fdd593SJeykumar Sankaran 90925fdd593SJeykumar Sankaran /* wait for frame_event_done completion */ 91025fdd593SJeykumar Sankaran if (_dpu_crtc_wait_for_frame_done(crtc)) 91125fdd593SJeykumar Sankaran DPU_ERROR("crtc%d wait for frame done failed;frame_pending%d\n", 91225fdd593SJeykumar Sankaran crtc->base.id, 91325fdd593SJeykumar Sankaran atomic_read(&dpu_crtc->frame_pending)); 91425fdd593SJeykumar Sankaran 91525fdd593SJeykumar Sankaran trace_dpu_crtc_disable(DRMID(crtc), false, dpu_crtc); 9167a007a12SBruce Wang if (dpu_crtc->enabled && dpu_crtc->vblank_requested) { 9171da03408SBruce Wang _dpu_crtc_vblank_enable_no_lock(dpu_crtc, false); 91825fdd593SJeykumar Sankaran } 91925fdd593SJeykumar Sankaran dpu_crtc->enabled = false; 92025fdd593SJeykumar Sankaran 92125fdd593SJeykumar Sankaran if (atomic_read(&dpu_crtc->frame_pending)) { 92225fdd593SJeykumar Sankaran trace_dpu_crtc_disable_frame_pending(DRMID(crtc), 92325fdd593SJeykumar Sankaran atomic_read(&dpu_crtc->frame_pending)); 92425fdd593SJeykumar Sankaran dpu_core_perf_crtc_release_bw(crtc); 92525fdd593SJeykumar Sankaran atomic_set(&dpu_crtc->frame_pending, 0); 92625fdd593SJeykumar Sankaran } 92725fdd593SJeykumar Sankaran 92825fdd593SJeykumar Sankaran dpu_core_perf_crtc_update(crtc, 0, true); 92925fdd593SJeykumar Sankaran 93025fdd593SJeykumar Sankaran drm_for_each_encoder(encoder, crtc->dev) { 93125fdd593SJeykumar Sankaran if (encoder->crtc != crtc) 93225fdd593SJeykumar Sankaran continue; 93325fdd593SJeykumar Sankaran dpu_encoder_register_frame_event_callback(encoder, NULL, NULL); 93425fdd593SJeykumar Sankaran } 93525fdd593SJeykumar Sankaran 9369222cdd2SJeykumar Sankaran memset(cstate->mixers, 0, sizeof(cstate->mixers)); 9379222cdd2SJeykumar Sankaran cstate->num_mixers = 0; 93825fdd593SJeykumar Sankaran 93925fdd593SJeykumar Sankaran /* disable clk & bw control until clk & bw properties are set */ 94025fdd593SJeykumar Sankaran cstate->bw_control = false; 94125fdd593SJeykumar Sankaran cstate->bw_split_vote = false; 94225fdd593SJeykumar Sankaran 94325fdd593SJeykumar Sankaran mutex_unlock(&dpu_crtc->crtc_lock); 9442f2eb723SRajesh Yadav 9452f2eb723SRajesh Yadav if (crtc->state->event && !crtc->state->active) { 9462f2eb723SRajesh Yadav spin_lock_irqsave(&crtc->dev->event_lock, flags); 9472f2eb723SRajesh Yadav drm_crtc_send_vblank_event(crtc, crtc->state->event); 9482f2eb723SRajesh Yadav crtc->state->event = NULL; 9492f2eb723SRajesh Yadav spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 9502f2eb723SRajesh Yadav } 95125fdd593SJeykumar Sankaran } 95225fdd593SJeykumar Sankaran 95325fdd593SJeykumar Sankaran static void dpu_crtc_enable(struct drm_crtc *crtc, 95425fdd593SJeykumar Sankaran struct drm_crtc_state *old_crtc_state) 95525fdd593SJeykumar Sankaran { 95625fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 95725fdd593SJeykumar Sankaran struct drm_encoder *encoder; 95825fdd593SJeykumar Sankaran struct msm_drm_private *priv; 95925fdd593SJeykumar Sankaran 96025fdd593SJeykumar Sankaran if (!crtc || !crtc->dev || !crtc->dev->dev_private) { 96125fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 96225fdd593SJeykumar Sankaran return; 96325fdd593SJeykumar Sankaran } 96425fdd593SJeykumar Sankaran priv = crtc->dev->dev_private; 96525fdd593SJeykumar Sankaran 96625fdd593SJeykumar Sankaran DRM_DEBUG_KMS("crtc%d\n", crtc->base.id); 96725fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 96825fdd593SJeykumar Sankaran 96925fdd593SJeykumar Sankaran drm_for_each_encoder(encoder, crtc->dev) { 97025fdd593SJeykumar Sankaran if (encoder->crtc != crtc) 97125fdd593SJeykumar Sankaran continue; 97225fdd593SJeykumar Sankaran dpu_encoder_register_frame_event_callback(encoder, 97325fdd593SJeykumar Sankaran dpu_crtc_frame_event_cb, (void *)crtc); 97425fdd593SJeykumar Sankaran } 97525fdd593SJeykumar Sankaran 97625fdd593SJeykumar Sankaran mutex_lock(&dpu_crtc->crtc_lock); 97725fdd593SJeykumar Sankaran trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc); 9787a007a12SBruce Wang if (!dpu_crtc->enabled && dpu_crtc->vblank_requested) { 9791da03408SBruce Wang _dpu_crtc_vblank_enable_no_lock(dpu_crtc, true); 98025fdd593SJeykumar Sankaran } 98125fdd593SJeykumar Sankaran dpu_crtc->enabled = true; 98225fdd593SJeykumar Sankaran 98325fdd593SJeykumar Sankaran mutex_unlock(&dpu_crtc->crtc_lock); 98425fdd593SJeykumar Sankaran 9852f2eb723SRajesh Yadav /* Enable/restore vblank irq handling */ 9862f2eb723SRajesh Yadav drm_crtc_vblank_on(crtc); 98725fdd593SJeykumar Sankaran } 98825fdd593SJeykumar Sankaran 98925fdd593SJeykumar Sankaran struct plane_state { 99025fdd593SJeykumar Sankaran struct dpu_plane_state *dpu_pstate; 99125fdd593SJeykumar Sankaran const struct drm_plane_state *drm_pstate; 99225fdd593SJeykumar Sankaran int stage; 99325fdd593SJeykumar Sankaran u32 pipe_id; 99425fdd593SJeykumar Sankaran }; 99525fdd593SJeykumar Sankaran 99625fdd593SJeykumar Sankaran static int dpu_crtc_atomic_check(struct drm_crtc *crtc, 99725fdd593SJeykumar Sankaran struct drm_crtc_state *state) 99825fdd593SJeykumar Sankaran { 99925fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 100025fdd593SJeykumar Sankaran struct plane_state *pstates; 100125fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 100225fdd593SJeykumar Sankaran 100325fdd593SJeykumar Sankaran const struct drm_plane_state *pstate; 100425fdd593SJeykumar Sankaran struct drm_plane *plane; 100525fdd593SJeykumar Sankaran struct drm_display_mode *mode; 100625fdd593SJeykumar Sankaran 100725fdd593SJeykumar Sankaran int cnt = 0, rc = 0, mixer_width, i, z_pos; 100825fdd593SJeykumar Sankaran 100925fdd593SJeykumar Sankaran struct dpu_multirect_plane_states multirect_plane[DPU_STAGE_MAX * 2]; 101025fdd593SJeykumar Sankaran int multirect_count = 0; 101125fdd593SJeykumar Sankaran const struct drm_plane_state *pipe_staged[SSPP_MAX]; 101225fdd593SJeykumar Sankaran int left_zpos_cnt = 0, right_zpos_cnt = 0; 101325fdd593SJeykumar Sankaran struct drm_rect crtc_rect = { 0 }; 101425fdd593SJeykumar Sankaran 101525fdd593SJeykumar Sankaran if (!crtc) { 101625fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 101725fdd593SJeykumar Sankaran return -EINVAL; 101825fdd593SJeykumar Sankaran } 101925fdd593SJeykumar Sankaran 102025fdd593SJeykumar Sankaran pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL); 102125fdd593SJeykumar Sankaran 102225fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 102325fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(state); 102425fdd593SJeykumar Sankaran 102525fdd593SJeykumar Sankaran if (!state->enable || !state->active) { 102625fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n", 102725fdd593SJeykumar Sankaran crtc->base.id, state->enable, state->active); 102825fdd593SJeykumar Sankaran goto end; 102925fdd593SJeykumar Sankaran } 103025fdd593SJeykumar Sankaran 103125fdd593SJeykumar Sankaran mode = &state->adjusted_mode; 103225fdd593SJeykumar Sankaran DPU_DEBUG("%s: check", dpu_crtc->name); 103325fdd593SJeykumar Sankaran 103425fdd593SJeykumar Sankaran /* force a full mode set if active state changed */ 103525fdd593SJeykumar Sankaran if (state->active_changed) 103625fdd593SJeykumar Sankaran state->mode_changed = true; 103725fdd593SJeykumar Sankaran 103825fdd593SJeykumar Sankaran memset(pipe_staged, 0, sizeof(pipe_staged)); 103925fdd593SJeykumar Sankaran 104042331668SJeykumar Sankaran mixer_width = _dpu_crtc_get_mixer_width(cstate, mode); 104125fdd593SJeykumar Sankaran 104225fdd593SJeykumar Sankaran _dpu_crtc_setup_lm_bounds(crtc, state); 104325fdd593SJeykumar Sankaran 104425fdd593SJeykumar Sankaran crtc_rect.x2 = mode->hdisplay; 104525fdd593SJeykumar Sankaran crtc_rect.y2 = mode->vdisplay; 104625fdd593SJeykumar Sankaran 104725fdd593SJeykumar Sankaran /* get plane state for all drm planes associated with crtc state */ 104825fdd593SJeykumar Sankaran drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { 104925fdd593SJeykumar Sankaran struct drm_rect dst, clip = crtc_rect; 105025fdd593SJeykumar Sankaran 105125fdd593SJeykumar Sankaran if (IS_ERR_OR_NULL(pstate)) { 105225fdd593SJeykumar Sankaran rc = PTR_ERR(pstate); 105325fdd593SJeykumar Sankaran DPU_ERROR("%s: failed to get plane%d state, %d\n", 105425fdd593SJeykumar Sankaran dpu_crtc->name, plane->base.id, rc); 105525fdd593SJeykumar Sankaran goto end; 105625fdd593SJeykumar Sankaran } 105725fdd593SJeykumar Sankaran if (cnt >= DPU_STAGE_MAX * 4) 105825fdd593SJeykumar Sankaran continue; 105925fdd593SJeykumar Sankaran 106025fdd593SJeykumar Sankaran pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate); 106125fdd593SJeykumar Sankaran pstates[cnt].drm_pstate = pstate; 106225fdd593SJeykumar Sankaran pstates[cnt].stage = pstate->normalized_zpos; 106325fdd593SJeykumar Sankaran pstates[cnt].pipe_id = dpu_plane_pipe(plane); 106425fdd593SJeykumar Sankaran 106525fdd593SJeykumar Sankaran if (pipe_staged[pstates[cnt].pipe_id]) { 106625fdd593SJeykumar Sankaran multirect_plane[multirect_count].r0 = 106725fdd593SJeykumar Sankaran pipe_staged[pstates[cnt].pipe_id]; 106825fdd593SJeykumar Sankaran multirect_plane[multirect_count].r1 = pstate; 106925fdd593SJeykumar Sankaran multirect_count++; 107025fdd593SJeykumar Sankaran 107125fdd593SJeykumar Sankaran pipe_staged[pstates[cnt].pipe_id] = NULL; 107225fdd593SJeykumar Sankaran } else { 107325fdd593SJeykumar Sankaran pipe_staged[pstates[cnt].pipe_id] = pstate; 107425fdd593SJeykumar Sankaran } 107525fdd593SJeykumar Sankaran 107625fdd593SJeykumar Sankaran cnt++; 107725fdd593SJeykumar Sankaran 107825fdd593SJeykumar Sankaran dst = drm_plane_state_dest(pstate); 107996fc56a7SSean Paul if (!drm_rect_intersect(&clip, &dst)) { 108025fdd593SJeykumar Sankaran DPU_ERROR("invalid vertical/horizontal destination\n"); 108125fdd593SJeykumar Sankaran DPU_ERROR("display: " DRM_RECT_FMT " plane: " 108225fdd593SJeykumar Sankaran DRM_RECT_FMT "\n", DRM_RECT_ARG(&crtc_rect), 108325fdd593SJeykumar Sankaran DRM_RECT_ARG(&dst)); 108425fdd593SJeykumar Sankaran rc = -E2BIG; 108525fdd593SJeykumar Sankaran goto end; 108625fdd593SJeykumar Sankaran } 108725fdd593SJeykumar Sankaran } 108825fdd593SJeykumar Sankaran 108925fdd593SJeykumar Sankaran for (i = 1; i < SSPP_MAX; i++) { 109025fdd593SJeykumar Sankaran if (pipe_staged[i]) { 109125fdd593SJeykumar Sankaran dpu_plane_clear_multirect(pipe_staged[i]); 109225fdd593SJeykumar Sankaran 109325fdd593SJeykumar Sankaran if (is_dpu_plane_virtual(pipe_staged[i]->plane)) { 109425fdd593SJeykumar Sankaran DPU_ERROR( 109525fdd593SJeykumar Sankaran "r1 only virt plane:%d not supported\n", 109625fdd593SJeykumar Sankaran pipe_staged[i]->plane->base.id); 109725fdd593SJeykumar Sankaran rc = -EINVAL; 109825fdd593SJeykumar Sankaran goto end; 109925fdd593SJeykumar Sankaran } 110025fdd593SJeykumar Sankaran } 110125fdd593SJeykumar Sankaran } 110225fdd593SJeykumar Sankaran 110325fdd593SJeykumar Sankaran z_pos = -1; 110425fdd593SJeykumar Sankaran for (i = 0; i < cnt; i++) { 110525fdd593SJeykumar Sankaran /* reset counts at every new blend stage */ 110625fdd593SJeykumar Sankaran if (pstates[i].stage != z_pos) { 110725fdd593SJeykumar Sankaran left_zpos_cnt = 0; 110825fdd593SJeykumar Sankaran right_zpos_cnt = 0; 110925fdd593SJeykumar Sankaran z_pos = pstates[i].stage; 111025fdd593SJeykumar Sankaran } 111125fdd593SJeykumar Sankaran 111225fdd593SJeykumar Sankaran /* verify z_pos setting before using it */ 111325fdd593SJeykumar Sankaran if (z_pos >= DPU_STAGE_MAX - DPU_STAGE_0) { 111425fdd593SJeykumar Sankaran DPU_ERROR("> %d plane stages assigned\n", 111525fdd593SJeykumar Sankaran DPU_STAGE_MAX - DPU_STAGE_0); 111625fdd593SJeykumar Sankaran rc = -EINVAL; 111725fdd593SJeykumar Sankaran goto end; 111825fdd593SJeykumar Sankaran } else if (pstates[i].drm_pstate->crtc_x < mixer_width) { 111925fdd593SJeykumar Sankaran if (left_zpos_cnt == 2) { 112025fdd593SJeykumar Sankaran DPU_ERROR("> 2 planes @ stage %d on left\n", 112125fdd593SJeykumar Sankaran z_pos); 112225fdd593SJeykumar Sankaran rc = -EINVAL; 112325fdd593SJeykumar Sankaran goto end; 112425fdd593SJeykumar Sankaran } 112525fdd593SJeykumar Sankaran left_zpos_cnt++; 112625fdd593SJeykumar Sankaran 112725fdd593SJeykumar Sankaran } else { 112825fdd593SJeykumar Sankaran if (right_zpos_cnt == 2) { 112925fdd593SJeykumar Sankaran DPU_ERROR("> 2 planes @ stage %d on right\n", 113025fdd593SJeykumar Sankaran z_pos); 113125fdd593SJeykumar Sankaran rc = -EINVAL; 113225fdd593SJeykumar Sankaran goto end; 113325fdd593SJeykumar Sankaran } 113425fdd593SJeykumar Sankaran right_zpos_cnt++; 113525fdd593SJeykumar Sankaran } 113625fdd593SJeykumar Sankaran 113725fdd593SJeykumar Sankaran pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0; 113825fdd593SJeykumar Sankaran DPU_DEBUG("%s: zpos %d", dpu_crtc->name, z_pos); 113925fdd593SJeykumar Sankaran } 114025fdd593SJeykumar Sankaran 114125fdd593SJeykumar Sankaran for (i = 0; i < multirect_count; i++) { 114225fdd593SJeykumar Sankaran if (dpu_plane_validate_multirect_v2(&multirect_plane[i])) { 114325fdd593SJeykumar Sankaran DPU_ERROR( 114425fdd593SJeykumar Sankaran "multirect validation failed for planes (%d - %d)\n", 114525fdd593SJeykumar Sankaran multirect_plane[i].r0->plane->base.id, 114625fdd593SJeykumar Sankaran multirect_plane[i].r1->plane->base.id); 114725fdd593SJeykumar Sankaran rc = -EINVAL; 114825fdd593SJeykumar Sankaran goto end; 114925fdd593SJeykumar Sankaran } 115025fdd593SJeykumar Sankaran } 115125fdd593SJeykumar Sankaran 115225fdd593SJeykumar Sankaran rc = dpu_core_perf_crtc_check(crtc, state); 115325fdd593SJeykumar Sankaran if (rc) { 115425fdd593SJeykumar Sankaran DPU_ERROR("crtc%d failed performance check %d\n", 115525fdd593SJeykumar Sankaran crtc->base.id, rc); 115625fdd593SJeykumar Sankaran goto end; 115725fdd593SJeykumar Sankaran } 115825fdd593SJeykumar Sankaran 115925fdd593SJeykumar Sankaran /* validate source split: 116025fdd593SJeykumar Sankaran * use pstates sorted by stage to check planes on same stage 116125fdd593SJeykumar Sankaran * we assume that all pipes are in source split so its valid to compare 116225fdd593SJeykumar Sankaran * without taking into account left/right mixer placement 116325fdd593SJeykumar Sankaran */ 116425fdd593SJeykumar Sankaran for (i = 1; i < cnt; i++) { 116525fdd593SJeykumar Sankaran struct plane_state *prv_pstate, *cur_pstate; 116625fdd593SJeykumar Sankaran struct drm_rect left_rect, right_rect; 116725fdd593SJeykumar Sankaran int32_t left_pid, right_pid; 116825fdd593SJeykumar Sankaran int32_t stage; 116925fdd593SJeykumar Sankaran 117025fdd593SJeykumar Sankaran prv_pstate = &pstates[i - 1]; 117125fdd593SJeykumar Sankaran cur_pstate = &pstates[i]; 117225fdd593SJeykumar Sankaran if (prv_pstate->stage != cur_pstate->stage) 117325fdd593SJeykumar Sankaran continue; 117425fdd593SJeykumar Sankaran 117525fdd593SJeykumar Sankaran stage = cur_pstate->stage; 117625fdd593SJeykumar Sankaran 117725fdd593SJeykumar Sankaran left_pid = prv_pstate->dpu_pstate->base.plane->base.id; 117825fdd593SJeykumar Sankaran left_rect = drm_plane_state_dest(prv_pstate->drm_pstate); 117925fdd593SJeykumar Sankaran 118025fdd593SJeykumar Sankaran right_pid = cur_pstate->dpu_pstate->base.plane->base.id; 118125fdd593SJeykumar Sankaran right_rect = drm_plane_state_dest(cur_pstate->drm_pstate); 118225fdd593SJeykumar Sankaran 118325fdd593SJeykumar Sankaran if (right_rect.x1 < left_rect.x1) { 118425fdd593SJeykumar Sankaran swap(left_pid, right_pid); 118525fdd593SJeykumar Sankaran swap(left_rect, right_rect); 118625fdd593SJeykumar Sankaran } 118725fdd593SJeykumar Sankaran 118825fdd593SJeykumar Sankaran /** 118925fdd593SJeykumar Sankaran * - planes are enumerated in pipe-priority order such that 119025fdd593SJeykumar Sankaran * planes with lower drm_id must be left-most in a shared 119125fdd593SJeykumar Sankaran * blend-stage when using source split. 119225fdd593SJeykumar Sankaran * - planes in source split must be contiguous in width 119325fdd593SJeykumar Sankaran * - planes in source split must have same dest yoff and height 119425fdd593SJeykumar Sankaran */ 119525fdd593SJeykumar Sankaran if (right_pid < left_pid) { 119625fdd593SJeykumar Sankaran DPU_ERROR( 119725fdd593SJeykumar Sankaran "invalid src split cfg. priority mismatch. stage: %d left: %d right: %d\n", 119825fdd593SJeykumar Sankaran stage, left_pid, right_pid); 119925fdd593SJeykumar Sankaran rc = -EINVAL; 120025fdd593SJeykumar Sankaran goto end; 120125fdd593SJeykumar Sankaran } else if (right_rect.x1 != drm_rect_width(&left_rect)) { 120225fdd593SJeykumar Sankaran DPU_ERROR("non-contiguous coordinates for src split. " 120325fdd593SJeykumar Sankaran "stage: %d left: " DRM_RECT_FMT " right: " 120425fdd593SJeykumar Sankaran DRM_RECT_FMT "\n", stage, 120525fdd593SJeykumar Sankaran DRM_RECT_ARG(&left_rect), 120625fdd593SJeykumar Sankaran DRM_RECT_ARG(&right_rect)); 120725fdd593SJeykumar Sankaran rc = -EINVAL; 120825fdd593SJeykumar Sankaran goto end; 120925fdd593SJeykumar Sankaran } else if (left_rect.y1 != right_rect.y1 || 121025fdd593SJeykumar Sankaran drm_rect_height(&left_rect) != drm_rect_height(&right_rect)) { 121125fdd593SJeykumar Sankaran DPU_ERROR("source split at stage: %d. invalid " 121225fdd593SJeykumar Sankaran "yoff/height: left: " DRM_RECT_FMT " right: " 121325fdd593SJeykumar Sankaran DRM_RECT_FMT "\n", stage, 121425fdd593SJeykumar Sankaran DRM_RECT_ARG(&left_rect), 121525fdd593SJeykumar Sankaran DRM_RECT_ARG(&right_rect)); 121625fdd593SJeykumar Sankaran rc = -EINVAL; 121725fdd593SJeykumar Sankaran goto end; 121825fdd593SJeykumar Sankaran } 121925fdd593SJeykumar Sankaran } 122025fdd593SJeykumar Sankaran 122125fdd593SJeykumar Sankaran end: 122225fdd593SJeykumar Sankaran kfree(pstates); 122325fdd593SJeykumar Sankaran return rc; 122425fdd593SJeykumar Sankaran } 122525fdd593SJeykumar Sankaran 122625fdd593SJeykumar Sankaran int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) 122725fdd593SJeykumar Sankaran { 12287a007a12SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 122925fdd593SJeykumar Sankaran 123025fdd593SJeykumar Sankaran mutex_lock(&dpu_crtc->crtc_lock); 123125fdd593SJeykumar Sankaran trace_dpu_crtc_vblank(DRMID(&dpu_crtc->base), en, dpu_crtc); 12327a007a12SBruce Wang if (dpu_crtc->enabled) { 12331da03408SBruce Wang _dpu_crtc_vblank_enable_no_lock(dpu_crtc, en); 123425fdd593SJeykumar Sankaran } 123525fdd593SJeykumar Sankaran dpu_crtc->vblank_requested = en; 123625fdd593SJeykumar Sankaran mutex_unlock(&dpu_crtc->crtc_lock); 123725fdd593SJeykumar Sankaran 123825fdd593SJeykumar Sankaran return 0; 123925fdd593SJeykumar Sankaran } 124025fdd593SJeykumar Sankaran 124125fdd593SJeykumar Sankaran #ifdef CONFIG_DEBUG_FS 124225fdd593SJeykumar Sankaran static int _dpu_debugfs_status_show(struct seq_file *s, void *data) 124325fdd593SJeykumar Sankaran { 124425fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 124525fdd593SJeykumar Sankaran struct dpu_plane_state *pstate = NULL; 124625fdd593SJeykumar Sankaran struct dpu_crtc_mixer *m; 124725fdd593SJeykumar Sankaran 124825fdd593SJeykumar Sankaran struct drm_crtc *crtc; 124925fdd593SJeykumar Sankaran struct drm_plane *plane; 125025fdd593SJeykumar Sankaran struct drm_display_mode *mode; 125125fdd593SJeykumar Sankaran struct drm_framebuffer *fb; 125225fdd593SJeykumar Sankaran struct drm_plane_state *state; 125325fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 125425fdd593SJeykumar Sankaran 125525fdd593SJeykumar Sankaran int i, out_width; 125625fdd593SJeykumar Sankaran 125725fdd593SJeykumar Sankaran if (!s || !s->private) 125825fdd593SJeykumar Sankaran return -EINVAL; 125925fdd593SJeykumar Sankaran 126025fdd593SJeykumar Sankaran dpu_crtc = s->private; 126125fdd593SJeykumar Sankaran crtc = &dpu_crtc->base; 12629222cdd2SJeykumar Sankaran 12639222cdd2SJeykumar Sankaran drm_modeset_lock_all(crtc->dev); 126425fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(crtc->state); 126525fdd593SJeykumar Sankaran 126625fdd593SJeykumar Sankaran mutex_lock(&dpu_crtc->crtc_lock); 126725fdd593SJeykumar Sankaran mode = &crtc->state->adjusted_mode; 126842331668SJeykumar Sankaran out_width = _dpu_crtc_get_mixer_width(cstate, mode); 126925fdd593SJeykumar Sankaran 127025fdd593SJeykumar Sankaran seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id, 127125fdd593SJeykumar Sankaran mode->hdisplay, mode->vdisplay); 127225fdd593SJeykumar Sankaran 127325fdd593SJeykumar Sankaran seq_puts(s, "\n"); 127425fdd593SJeykumar Sankaran 12759222cdd2SJeykumar Sankaran for (i = 0; i < cstate->num_mixers; ++i) { 12769222cdd2SJeykumar Sankaran m = &cstate->mixers[i]; 127725fdd593SJeykumar Sankaran if (!m->hw_lm) 127825fdd593SJeykumar Sankaran seq_printf(s, "\tmixer[%d] has no lm\n", i); 1279cf6916f4SJeykumar Sankaran else if (!m->lm_ctl) 128025fdd593SJeykumar Sankaran seq_printf(s, "\tmixer[%d] has no ctl\n", i); 128125fdd593SJeykumar Sankaran else 128225fdd593SJeykumar Sankaran seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n", 1283cf6916f4SJeykumar Sankaran m->hw_lm->idx - LM_0, m->lm_ctl->idx - CTL_0, 128425fdd593SJeykumar Sankaran out_width, mode->vdisplay); 128525fdd593SJeykumar Sankaran } 128625fdd593SJeykumar Sankaran 128725fdd593SJeykumar Sankaran seq_puts(s, "\n"); 128825fdd593SJeykumar Sankaran 128925fdd593SJeykumar Sankaran drm_atomic_crtc_for_each_plane(plane, crtc) { 129025fdd593SJeykumar Sankaran pstate = to_dpu_plane_state(plane->state); 129125fdd593SJeykumar Sankaran state = plane->state; 129225fdd593SJeykumar Sankaran 129325fdd593SJeykumar Sankaran if (!pstate || !state) 129425fdd593SJeykumar Sankaran continue; 129525fdd593SJeykumar Sankaran 129625fdd593SJeykumar Sankaran seq_printf(s, "\tplane:%u stage:%d\n", plane->base.id, 129725fdd593SJeykumar Sankaran pstate->stage); 129825fdd593SJeykumar Sankaran 129925fdd593SJeykumar Sankaran if (plane->state->fb) { 130025fdd593SJeykumar Sankaran fb = plane->state->fb; 130125fdd593SJeykumar Sankaran 130225fdd593SJeykumar Sankaran seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u ", 130325fdd593SJeykumar Sankaran fb->base.id, (char *) &fb->format->format, 130425fdd593SJeykumar Sankaran fb->width, fb->height); 130525fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(fb->format->cpp); ++i) 130625fdd593SJeykumar Sankaran seq_printf(s, "cpp[%d]:%u ", 130725fdd593SJeykumar Sankaran i, fb->format->cpp[i]); 130825fdd593SJeykumar Sankaran seq_puts(s, "\n\t"); 130925fdd593SJeykumar Sankaran 131025fdd593SJeykumar Sankaran seq_printf(s, "modifier:%8llu ", fb->modifier); 131125fdd593SJeykumar Sankaran seq_puts(s, "\n"); 131225fdd593SJeykumar Sankaran 131325fdd593SJeykumar Sankaran seq_puts(s, "\t"); 131425fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) 131525fdd593SJeykumar Sankaran seq_printf(s, "pitches[%d]:%8u ", i, 131625fdd593SJeykumar Sankaran fb->pitches[i]); 131725fdd593SJeykumar Sankaran seq_puts(s, "\n"); 131825fdd593SJeykumar Sankaran 131925fdd593SJeykumar Sankaran seq_puts(s, "\t"); 132025fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) 132125fdd593SJeykumar Sankaran seq_printf(s, "offsets[%d]:%8u ", i, 132225fdd593SJeykumar Sankaran fb->offsets[i]); 132325fdd593SJeykumar Sankaran seq_puts(s, "\n"); 132425fdd593SJeykumar Sankaran } 132525fdd593SJeykumar Sankaran 132625fdd593SJeykumar Sankaran seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n", 132725fdd593SJeykumar Sankaran state->src_x, state->src_y, state->src_w, state->src_h); 132825fdd593SJeykumar Sankaran 132925fdd593SJeykumar Sankaran seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", 133025fdd593SJeykumar Sankaran state->crtc_x, state->crtc_y, state->crtc_w, 133125fdd593SJeykumar Sankaran state->crtc_h); 133225fdd593SJeykumar Sankaran seq_printf(s, "\tmultirect: mode: %d index: %d\n", 133325fdd593SJeykumar Sankaran pstate->multirect_mode, pstate->multirect_index); 133425fdd593SJeykumar Sankaran 133525fdd593SJeykumar Sankaran seq_puts(s, "\n"); 133625fdd593SJeykumar Sankaran } 133725fdd593SJeykumar Sankaran if (dpu_crtc->vblank_cb_count) { 133825fdd593SJeykumar Sankaran ktime_t diff = ktime_sub(ktime_get(), dpu_crtc->vblank_cb_time); 133925fdd593SJeykumar Sankaran s64 diff_ms = ktime_to_ms(diff); 134025fdd593SJeykumar Sankaran s64 fps = diff_ms ? div_s64( 134125fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_count * 1000, diff_ms) : 0; 134225fdd593SJeykumar Sankaran 134325fdd593SJeykumar Sankaran seq_printf(s, 134425fdd593SJeykumar Sankaran "vblank fps:%lld count:%u total:%llums total_framecount:%llu\n", 134525fdd593SJeykumar Sankaran fps, dpu_crtc->vblank_cb_count, 134625fdd593SJeykumar Sankaran ktime_to_ms(diff), dpu_crtc->play_count); 134725fdd593SJeykumar Sankaran 134825fdd593SJeykumar Sankaran /* reset time & count for next measurement */ 134925fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_count = 0; 135025fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_time = ktime_set(0, 0); 135125fdd593SJeykumar Sankaran } 135225fdd593SJeykumar Sankaran 135325fdd593SJeykumar Sankaran seq_printf(s, "vblank_enable:%d\n", dpu_crtc->vblank_requested); 135425fdd593SJeykumar Sankaran 135525fdd593SJeykumar Sankaran mutex_unlock(&dpu_crtc->crtc_lock); 13569222cdd2SJeykumar Sankaran drm_modeset_unlock_all(crtc->dev); 135725fdd593SJeykumar Sankaran 135825fdd593SJeykumar Sankaran return 0; 135925fdd593SJeykumar Sankaran } 136025fdd593SJeykumar Sankaran 136125fdd593SJeykumar Sankaran static int _dpu_debugfs_status_open(struct inode *inode, struct file *file) 136225fdd593SJeykumar Sankaran { 136325fdd593SJeykumar Sankaran return single_open(file, _dpu_debugfs_status_show, inode->i_private); 136425fdd593SJeykumar Sankaran } 136525fdd593SJeykumar Sankaran 136625fdd593SJeykumar Sankaran #define DEFINE_DPU_DEBUGFS_SEQ_FOPS(__prefix) \ 136725fdd593SJeykumar Sankaran static int __prefix ## _open(struct inode *inode, struct file *file) \ 136825fdd593SJeykumar Sankaran { \ 136925fdd593SJeykumar Sankaran return single_open(file, __prefix ## _show, inode->i_private); \ 137025fdd593SJeykumar Sankaran } \ 137125fdd593SJeykumar Sankaran static const struct file_operations __prefix ## _fops = { \ 137225fdd593SJeykumar Sankaran .owner = THIS_MODULE, \ 137325fdd593SJeykumar Sankaran .open = __prefix ## _open, \ 137425fdd593SJeykumar Sankaran .release = single_release, \ 137525fdd593SJeykumar Sankaran .read = seq_read, \ 137625fdd593SJeykumar Sankaran .llseek = seq_lseek, \ 137725fdd593SJeykumar Sankaran } 137825fdd593SJeykumar Sankaran 137925fdd593SJeykumar Sankaran static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v) 138025fdd593SJeykumar Sankaran { 138125fdd593SJeykumar Sankaran struct drm_crtc *crtc = (struct drm_crtc *) s->private; 138225fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 138325fdd593SJeykumar Sankaran int i; 138425fdd593SJeykumar Sankaran 138525fdd593SJeykumar Sankaran seq_printf(s, "client type: %d\n", dpu_crtc_get_client_type(crtc)); 138625fdd593SJeykumar Sankaran seq_printf(s, "intf_mode: %d\n", dpu_crtc_get_intf_mode(crtc)); 138725fdd593SJeykumar Sankaran seq_printf(s, "core_clk_rate: %llu\n", 138825fdd593SJeykumar Sankaran dpu_crtc->cur_perf.core_clk_rate); 1389aeb7b49aSSean Paul for (i = DPU_CORE_PERF_DATA_BUS_ID_MNOC; 1390aeb7b49aSSean Paul i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { 13915e1228d7SSean Paul seq_printf(s, "bw_ctl[%d]: %llu\n", i, 139225fdd593SJeykumar Sankaran dpu_crtc->cur_perf.bw_ctl[i]); 13935e1228d7SSean Paul seq_printf(s, "max_per_pipe_ib[%d]: %llu\n", i, 139425fdd593SJeykumar Sankaran dpu_crtc->cur_perf.max_per_pipe_ib[i]); 139525fdd593SJeykumar Sankaran } 139625fdd593SJeykumar Sankaran 139725fdd593SJeykumar Sankaran return 0; 139825fdd593SJeykumar Sankaran } 139925fdd593SJeykumar Sankaran DEFINE_DPU_DEBUGFS_SEQ_FOPS(dpu_crtc_debugfs_state); 140025fdd593SJeykumar Sankaran 140125fdd593SJeykumar Sankaran static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc) 140225fdd593SJeykumar Sankaran { 140325fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 140425fdd593SJeykumar Sankaran struct dpu_kms *dpu_kms; 140525fdd593SJeykumar Sankaran 140625fdd593SJeykumar Sankaran static const struct file_operations debugfs_status_fops = { 140725fdd593SJeykumar Sankaran .open = _dpu_debugfs_status_open, 140825fdd593SJeykumar Sankaran .read = seq_read, 140925fdd593SJeykumar Sankaran .llseek = seq_lseek, 141025fdd593SJeykumar Sankaran .release = single_release, 141125fdd593SJeykumar Sankaran }; 141225fdd593SJeykumar Sankaran 141325fdd593SJeykumar Sankaran if (!crtc) 141425fdd593SJeykumar Sankaran return -EINVAL; 141525fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 141625fdd593SJeykumar Sankaran 141725fdd593SJeykumar Sankaran dpu_kms = _dpu_crtc_get_kms(crtc); 141825fdd593SJeykumar Sankaran 141925fdd593SJeykumar Sankaran dpu_crtc->debugfs_root = debugfs_create_dir(dpu_crtc->name, 142025fdd593SJeykumar Sankaran crtc->dev->primary->debugfs_root); 142125fdd593SJeykumar Sankaran if (!dpu_crtc->debugfs_root) 142225fdd593SJeykumar Sankaran return -ENOMEM; 142325fdd593SJeykumar Sankaran 142425fdd593SJeykumar Sankaran /* don't error check these */ 142525fdd593SJeykumar Sankaran debugfs_create_file("status", 0400, 142625fdd593SJeykumar Sankaran dpu_crtc->debugfs_root, 142725fdd593SJeykumar Sankaran dpu_crtc, &debugfs_status_fops); 142825fdd593SJeykumar Sankaran debugfs_create_file("state", 0600, 142925fdd593SJeykumar Sankaran dpu_crtc->debugfs_root, 143025fdd593SJeykumar Sankaran &dpu_crtc->base, 143125fdd593SJeykumar Sankaran &dpu_crtc_debugfs_state_fops); 143225fdd593SJeykumar Sankaran 143325fdd593SJeykumar Sankaran return 0; 143425fdd593SJeykumar Sankaran } 143525fdd593SJeykumar Sankaran 143625fdd593SJeykumar Sankaran static void _dpu_crtc_destroy_debugfs(struct drm_crtc *crtc) 143725fdd593SJeykumar Sankaran { 143825fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 143925fdd593SJeykumar Sankaran 144025fdd593SJeykumar Sankaran if (!crtc) 144125fdd593SJeykumar Sankaran return; 144225fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 144325fdd593SJeykumar Sankaran debugfs_remove_recursive(dpu_crtc->debugfs_root); 144425fdd593SJeykumar Sankaran } 144525fdd593SJeykumar Sankaran #else 144625fdd593SJeykumar Sankaran static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc) 144725fdd593SJeykumar Sankaran { 144825fdd593SJeykumar Sankaran return 0; 144925fdd593SJeykumar Sankaran } 145025fdd593SJeykumar Sankaran 145125fdd593SJeykumar Sankaran static void _dpu_crtc_destroy_debugfs(struct drm_crtc *crtc) 145225fdd593SJeykumar Sankaran { 145325fdd593SJeykumar Sankaran } 145425fdd593SJeykumar Sankaran #endif /* CONFIG_DEBUG_FS */ 145525fdd593SJeykumar Sankaran 145625fdd593SJeykumar Sankaran static int dpu_crtc_late_register(struct drm_crtc *crtc) 145725fdd593SJeykumar Sankaran { 145825fdd593SJeykumar Sankaran return _dpu_crtc_init_debugfs(crtc); 145925fdd593SJeykumar Sankaran } 146025fdd593SJeykumar Sankaran 146125fdd593SJeykumar Sankaran static void dpu_crtc_early_unregister(struct drm_crtc *crtc) 146225fdd593SJeykumar Sankaran { 146325fdd593SJeykumar Sankaran _dpu_crtc_destroy_debugfs(crtc); 146425fdd593SJeykumar Sankaran } 146525fdd593SJeykumar Sankaran 146625fdd593SJeykumar Sankaran static const struct drm_crtc_funcs dpu_crtc_funcs = { 146725fdd593SJeykumar Sankaran .set_config = drm_atomic_helper_set_config, 146825fdd593SJeykumar Sankaran .destroy = dpu_crtc_destroy, 146925fdd593SJeykumar Sankaran .page_flip = drm_atomic_helper_page_flip, 1470ff5952a7SSean Paul .reset = dpu_crtc_reset, 147125fdd593SJeykumar Sankaran .atomic_duplicate_state = dpu_crtc_duplicate_state, 147225fdd593SJeykumar Sankaran .atomic_destroy_state = dpu_crtc_destroy_state, 147325fdd593SJeykumar Sankaran .late_register = dpu_crtc_late_register, 147425fdd593SJeykumar Sankaran .early_unregister = dpu_crtc_early_unregister, 147525fdd593SJeykumar Sankaran }; 147625fdd593SJeykumar Sankaran 147725fdd593SJeykumar Sankaran static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = { 147825fdd593SJeykumar Sankaran .disable = dpu_crtc_disable, 147925fdd593SJeykumar Sankaran .atomic_enable = dpu_crtc_enable, 148025fdd593SJeykumar Sankaran .atomic_check = dpu_crtc_atomic_check, 148125fdd593SJeykumar Sankaran .atomic_begin = dpu_crtc_atomic_begin, 148225fdd593SJeykumar Sankaran .atomic_flush = dpu_crtc_atomic_flush, 148325fdd593SJeykumar Sankaran }; 148425fdd593SJeykumar Sankaran 148525fdd593SJeykumar Sankaran /* initialize crtc */ 148607ca1fc0SSravanthi Kollukuduru struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, 148707ca1fc0SSravanthi Kollukuduru struct drm_plane *cursor) 148825fdd593SJeykumar Sankaran { 148925fdd593SJeykumar Sankaran struct drm_crtc *crtc = NULL; 149025fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = NULL; 149125fdd593SJeykumar Sankaran struct msm_drm_private *priv = NULL; 149225fdd593SJeykumar Sankaran struct dpu_kms *kms = NULL; 1493c17aeda0SJordan Crouse int i; 149425fdd593SJeykumar Sankaran 149525fdd593SJeykumar Sankaran priv = dev->dev_private; 149625fdd593SJeykumar Sankaran kms = to_dpu_kms(priv->kms); 149725fdd593SJeykumar Sankaran 149825fdd593SJeykumar Sankaran dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL); 149925fdd593SJeykumar Sankaran if (!dpu_crtc) 150025fdd593SJeykumar Sankaran return ERR_PTR(-ENOMEM); 150125fdd593SJeykumar Sankaran 150225fdd593SJeykumar Sankaran crtc = &dpu_crtc->base; 150325fdd593SJeykumar Sankaran crtc->dev = dev; 150425fdd593SJeykumar Sankaran 150525fdd593SJeykumar Sankaran mutex_init(&dpu_crtc->crtc_lock); 150625fdd593SJeykumar Sankaran spin_lock_init(&dpu_crtc->spin_lock); 150725fdd593SJeykumar Sankaran atomic_set(&dpu_crtc->frame_pending, 0); 150825fdd593SJeykumar Sankaran 150925fdd593SJeykumar Sankaran init_completion(&dpu_crtc->frame_done_comp); 151025fdd593SJeykumar Sankaran 151125fdd593SJeykumar Sankaran INIT_LIST_HEAD(&dpu_crtc->frame_event_list); 151225fdd593SJeykumar Sankaran 151325fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(dpu_crtc->frame_events); i++) { 151425fdd593SJeykumar Sankaran INIT_LIST_HEAD(&dpu_crtc->frame_events[i].list); 151525fdd593SJeykumar Sankaran list_add(&dpu_crtc->frame_events[i].list, 151625fdd593SJeykumar Sankaran &dpu_crtc->frame_event_list); 151725fdd593SJeykumar Sankaran kthread_init_work(&dpu_crtc->frame_events[i].work, 151825fdd593SJeykumar Sankaran dpu_crtc_frame_event_work); 151925fdd593SJeykumar Sankaran } 152025fdd593SJeykumar Sankaran 152107ca1fc0SSravanthi Kollukuduru drm_crtc_init_with_planes(dev, crtc, plane, cursor, &dpu_crtc_funcs, 152225fdd593SJeykumar Sankaran NULL); 152325fdd593SJeykumar Sankaran 152425fdd593SJeykumar Sankaran drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs); 152525fdd593SJeykumar Sankaran plane->crtc = crtc; 152625fdd593SJeykumar Sankaran 152725fdd593SJeykumar Sankaran /* save user friendly CRTC name for later */ 152825fdd593SJeykumar Sankaran snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id); 152925fdd593SJeykumar Sankaran 153025fdd593SJeykumar Sankaran /* initialize event handling */ 1531c17aeda0SJordan Crouse spin_lock_init(&dpu_crtc->event_lock); 153225fdd593SJeykumar Sankaran 153325fdd593SJeykumar Sankaran DPU_DEBUG("%s: successfully initialized crtc\n", dpu_crtc->name); 153425fdd593SJeykumar Sankaran return crtc; 153525fdd593SJeykumar Sankaran } 1536