125fdd593SJeykumar Sankaran /* 225fdd593SJeykumar Sankaran * Copyright (c) 2014-2018 The Linux Foundation. All rights reserved. 325fdd593SJeykumar Sankaran * Copyright (C) 2013 Red Hat 425fdd593SJeykumar Sankaran * Author: Rob Clark <robdclark@gmail.com> 525fdd593SJeykumar Sankaran * 625fdd593SJeykumar Sankaran * This program is free software; you can redistribute it and/or modify it 725fdd593SJeykumar Sankaran * under the terms of the GNU General Public License version 2 as published by 825fdd593SJeykumar Sankaran * the Free Software Foundation. 925fdd593SJeykumar Sankaran * 1025fdd593SJeykumar Sankaran * This program is distributed in the hope that it will be useful, but WITHOUT 1125fdd593SJeykumar Sankaran * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1225fdd593SJeykumar Sankaran * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1325fdd593SJeykumar Sankaran * more details. 1425fdd593SJeykumar Sankaran * 1525fdd593SJeykumar Sankaran * You should have received a copy of the GNU General Public License along with 1625fdd593SJeykumar Sankaran * this program. If not, see <http://www.gnu.org/licenses/>. 1725fdd593SJeykumar Sankaran */ 1825fdd593SJeykumar Sankaran 1925fdd593SJeykumar Sankaran #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 2025fdd593SJeykumar Sankaran #include <linux/sort.h> 2125fdd593SJeykumar Sankaran #include <linux/debugfs.h> 2225fdd593SJeykumar Sankaran #include <linux/ktime.h> 2325fdd593SJeykumar Sankaran #include <drm/drm_mode.h> 2425fdd593SJeykumar Sankaran #include <drm/drm_crtc.h> 2525fdd593SJeykumar Sankaran #include <drm/drm_crtc_helper.h> 2625fdd593SJeykumar Sankaran #include <drm/drm_flip_work.h> 2725fdd593SJeykumar Sankaran #include <drm/drm_rect.h> 2825fdd593SJeykumar Sankaran 2925fdd593SJeykumar Sankaran #include "dpu_kms.h" 3025fdd593SJeykumar Sankaran #include "dpu_hw_lm.h" 3125fdd593SJeykumar Sankaran #include "dpu_hw_ctl.h" 3225fdd593SJeykumar Sankaran #include "dpu_crtc.h" 3325fdd593SJeykumar Sankaran #include "dpu_plane.h" 3425fdd593SJeykumar Sankaran #include "dpu_encoder.h" 3525fdd593SJeykumar Sankaran #include "dpu_vbif.h" 3625fdd593SJeykumar Sankaran #include "dpu_power_handle.h" 3725fdd593SJeykumar Sankaran #include "dpu_core_perf.h" 3825fdd593SJeykumar Sankaran #include "dpu_trace.h" 3925fdd593SJeykumar Sankaran 4025fdd593SJeykumar Sankaran #define DPU_DRM_BLEND_OP_NOT_DEFINED 0 4125fdd593SJeykumar Sankaran #define DPU_DRM_BLEND_OP_OPAQUE 1 4225fdd593SJeykumar Sankaran #define DPU_DRM_BLEND_OP_PREMULTIPLIED 2 4325fdd593SJeykumar Sankaran #define DPU_DRM_BLEND_OP_COVERAGE 3 4425fdd593SJeykumar Sankaran #define DPU_DRM_BLEND_OP_MAX 4 4525fdd593SJeykumar Sankaran 4625fdd593SJeykumar Sankaran /* layer mixer index on dpu_crtc */ 4725fdd593SJeykumar Sankaran #define LEFT_MIXER 0 4825fdd593SJeykumar Sankaran #define RIGHT_MIXER 1 4925fdd593SJeykumar Sankaran 5025fdd593SJeykumar Sankaran #define MISR_BUFF_SIZE 256 5125fdd593SJeykumar Sankaran 5225fdd593SJeykumar Sankaran static inline struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc) 5325fdd593SJeykumar Sankaran { 5425fdd593SJeykumar Sankaran struct msm_drm_private *priv; 5525fdd593SJeykumar Sankaran 5625fdd593SJeykumar Sankaran if (!crtc || !crtc->dev || !crtc->dev->dev_private) { 5725fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 5825fdd593SJeykumar Sankaran return NULL; 5925fdd593SJeykumar Sankaran } 6025fdd593SJeykumar Sankaran priv = crtc->dev->dev_private; 6125fdd593SJeykumar Sankaran if (!priv || !priv->kms) { 6225fdd593SJeykumar Sankaran DPU_ERROR("invalid kms\n"); 6325fdd593SJeykumar Sankaran return NULL; 6425fdd593SJeykumar Sankaran } 6525fdd593SJeykumar Sankaran 6625fdd593SJeykumar Sankaran return to_dpu_kms(priv->kms); 6725fdd593SJeykumar Sankaran } 6825fdd593SJeykumar Sankaran 6925fdd593SJeykumar Sankaran static inline int _dpu_crtc_power_enable(struct dpu_crtc *dpu_crtc, bool enable) 7025fdd593SJeykumar Sankaran { 7125fdd593SJeykumar Sankaran struct drm_crtc *crtc; 7225fdd593SJeykumar Sankaran struct msm_drm_private *priv; 7325fdd593SJeykumar Sankaran struct dpu_kms *dpu_kms; 7425fdd593SJeykumar Sankaran 7525fdd593SJeykumar Sankaran if (!dpu_crtc) { 7625fdd593SJeykumar Sankaran DPU_ERROR("invalid dpu crtc\n"); 7725fdd593SJeykumar Sankaran return -EINVAL; 7825fdd593SJeykumar Sankaran } 7925fdd593SJeykumar Sankaran 8025fdd593SJeykumar Sankaran crtc = &dpu_crtc->base; 8125fdd593SJeykumar Sankaran if (!crtc->dev || !crtc->dev->dev_private) { 8225fdd593SJeykumar Sankaran DPU_ERROR("invalid drm device\n"); 8325fdd593SJeykumar Sankaran return -EINVAL; 8425fdd593SJeykumar Sankaran } 8525fdd593SJeykumar Sankaran 8625fdd593SJeykumar Sankaran priv = crtc->dev->dev_private; 8725fdd593SJeykumar Sankaran if (!priv->kms) { 8825fdd593SJeykumar Sankaran DPU_ERROR("invalid kms\n"); 8925fdd593SJeykumar Sankaran return -EINVAL; 9025fdd593SJeykumar Sankaran } 9125fdd593SJeykumar Sankaran 9225fdd593SJeykumar Sankaran dpu_kms = to_dpu_kms(priv->kms); 9325fdd593SJeykumar Sankaran 9425fdd593SJeykumar Sankaran if (enable) 9525fdd593SJeykumar Sankaran pm_runtime_get_sync(&dpu_kms->pdev->dev); 9625fdd593SJeykumar Sankaran else 9725fdd593SJeykumar Sankaran pm_runtime_put_sync(&dpu_kms->pdev->dev); 9825fdd593SJeykumar Sankaran 9925fdd593SJeykumar Sankaran return 0; 10025fdd593SJeykumar Sankaran } 10125fdd593SJeykumar Sankaran 10225fdd593SJeykumar Sankaran /** 10325fdd593SJeykumar Sankaran * _dpu_crtc_rp_to_crtc - get crtc from resource pool object 10425fdd593SJeykumar Sankaran * @rp: Pointer to resource pool 10525fdd593SJeykumar Sankaran * return: Pointer to drm crtc if success; null otherwise 10625fdd593SJeykumar Sankaran */ 10725fdd593SJeykumar Sankaran static struct drm_crtc *_dpu_crtc_rp_to_crtc(struct dpu_crtc_respool *rp) 10825fdd593SJeykumar Sankaran { 10925fdd593SJeykumar Sankaran if (!rp) 11025fdd593SJeykumar Sankaran return NULL; 11125fdd593SJeykumar Sankaran 11225fdd593SJeykumar Sankaran return container_of(rp, struct dpu_crtc_state, rp)->base.crtc; 11325fdd593SJeykumar Sankaran } 11425fdd593SJeykumar Sankaran 11525fdd593SJeykumar Sankaran /** 11625fdd593SJeykumar Sankaran * _dpu_crtc_rp_reclaim - reclaim unused, or all if forced, resources in pool 11725fdd593SJeykumar Sankaran * @rp: Pointer to resource pool 11825fdd593SJeykumar Sankaran * @force: True to reclaim all resources; otherwise, reclaim only unused ones 11925fdd593SJeykumar Sankaran * return: None 12025fdd593SJeykumar Sankaran */ 12125fdd593SJeykumar Sankaran static void _dpu_crtc_rp_reclaim(struct dpu_crtc_respool *rp, bool force) 12225fdd593SJeykumar Sankaran { 12325fdd593SJeykumar Sankaran struct dpu_crtc_res *res, *next; 12425fdd593SJeykumar Sankaran struct drm_crtc *crtc; 12525fdd593SJeykumar Sankaran 12625fdd593SJeykumar Sankaran crtc = _dpu_crtc_rp_to_crtc(rp); 12725fdd593SJeykumar Sankaran if (!crtc) { 12825fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 12925fdd593SJeykumar Sankaran return; 13025fdd593SJeykumar Sankaran } 13125fdd593SJeykumar Sankaran 13225fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d.%u %s\n", crtc->base.id, rp->sequence_id, 13325fdd593SJeykumar Sankaran force ? "destroy" : "free_unused"); 13425fdd593SJeykumar Sankaran 13525fdd593SJeykumar Sankaran list_for_each_entry_safe(res, next, &rp->res_list, list) { 13625fdd593SJeykumar Sankaran if (!force && !(res->flags & DPU_CRTC_RES_FLAG_FREE)) 13725fdd593SJeykumar Sankaran continue; 13825fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d.%u reclaim res:0x%x/0x%llx/%pK/%d\n", 13925fdd593SJeykumar Sankaran crtc->base.id, rp->sequence_id, 14025fdd593SJeykumar Sankaran res->type, res->tag, res->val, 14125fdd593SJeykumar Sankaran atomic_read(&res->refcount)); 14225fdd593SJeykumar Sankaran list_del(&res->list); 14325fdd593SJeykumar Sankaran if (res->ops.put) 14425fdd593SJeykumar Sankaran res->ops.put(res->val); 14525fdd593SJeykumar Sankaran kfree(res); 14625fdd593SJeykumar Sankaran } 14725fdd593SJeykumar Sankaran } 14825fdd593SJeykumar Sankaran 14925fdd593SJeykumar Sankaran /** 15025fdd593SJeykumar Sankaran * _dpu_crtc_rp_free_unused - free unused resource in pool 15125fdd593SJeykumar Sankaran * @rp: Pointer to resource pool 15225fdd593SJeykumar Sankaran * return: none 15325fdd593SJeykumar Sankaran */ 15425fdd593SJeykumar Sankaran static void _dpu_crtc_rp_free_unused(struct dpu_crtc_respool *rp) 15525fdd593SJeykumar Sankaran { 15625fdd593SJeykumar Sankaran mutex_lock(rp->rp_lock); 15725fdd593SJeykumar Sankaran _dpu_crtc_rp_reclaim(rp, false); 15825fdd593SJeykumar Sankaran mutex_unlock(rp->rp_lock); 15925fdd593SJeykumar Sankaran } 16025fdd593SJeykumar Sankaran 16125fdd593SJeykumar Sankaran /** 16225fdd593SJeykumar Sankaran * _dpu_crtc_rp_destroy - destroy resource pool 16325fdd593SJeykumar Sankaran * @rp: Pointer to resource pool 16425fdd593SJeykumar Sankaran * return: None 16525fdd593SJeykumar Sankaran */ 16625fdd593SJeykumar Sankaran static void _dpu_crtc_rp_destroy(struct dpu_crtc_respool *rp) 16725fdd593SJeykumar Sankaran { 16825fdd593SJeykumar Sankaran mutex_lock(rp->rp_lock); 16925fdd593SJeykumar Sankaran list_del_init(&rp->rp_list); 17025fdd593SJeykumar Sankaran _dpu_crtc_rp_reclaim(rp, true); 17125fdd593SJeykumar Sankaran mutex_unlock(rp->rp_lock); 17225fdd593SJeykumar Sankaran } 17325fdd593SJeykumar Sankaran 17425fdd593SJeykumar Sankaran /** 17525fdd593SJeykumar Sankaran * _dpu_crtc_hw_blk_get - get callback for hardware block 17625fdd593SJeykumar Sankaran * @val: Resource handle 17725fdd593SJeykumar Sankaran * @type: Resource type 17825fdd593SJeykumar Sankaran * @tag: Search tag for given resource 17925fdd593SJeykumar Sankaran * return: Resource handle 18025fdd593SJeykumar Sankaran */ 18125fdd593SJeykumar Sankaran static void *_dpu_crtc_hw_blk_get(void *val, u32 type, u64 tag) 18225fdd593SJeykumar Sankaran { 18325fdd593SJeykumar Sankaran DPU_DEBUG("res:%d/0x%llx/%pK\n", type, tag, val); 18425fdd593SJeykumar Sankaran return dpu_hw_blk_get(val, type, tag); 18525fdd593SJeykumar Sankaran } 18625fdd593SJeykumar Sankaran 18725fdd593SJeykumar Sankaran /** 18825fdd593SJeykumar Sankaran * _dpu_crtc_hw_blk_put - put callback for hardware block 18925fdd593SJeykumar Sankaran * @val: Resource handle 19025fdd593SJeykumar Sankaran * return: None 19125fdd593SJeykumar Sankaran */ 19225fdd593SJeykumar Sankaran static void _dpu_crtc_hw_blk_put(void *val) 19325fdd593SJeykumar Sankaran { 19425fdd593SJeykumar Sankaran DPU_DEBUG("res://%pK\n", val); 19525fdd593SJeykumar Sankaran dpu_hw_blk_put(val); 19625fdd593SJeykumar Sankaran } 19725fdd593SJeykumar Sankaran 19825fdd593SJeykumar Sankaran /** 19925fdd593SJeykumar Sankaran * _dpu_crtc_rp_duplicate - duplicate resource pool and reset reference count 20025fdd593SJeykumar Sankaran * @rp: Pointer to original resource pool 20125fdd593SJeykumar Sankaran * @dup_rp: Pointer to duplicated resource pool 20225fdd593SJeykumar Sankaran * return: None 20325fdd593SJeykumar Sankaran */ 20425fdd593SJeykumar Sankaran static void _dpu_crtc_rp_duplicate(struct dpu_crtc_respool *rp, 20525fdd593SJeykumar Sankaran struct dpu_crtc_respool *dup_rp) 20625fdd593SJeykumar Sankaran { 20725fdd593SJeykumar Sankaran struct dpu_crtc_res *res, *dup_res; 20825fdd593SJeykumar Sankaran struct drm_crtc *crtc; 20925fdd593SJeykumar Sankaran 21025fdd593SJeykumar Sankaran if (!rp || !dup_rp || !rp->rp_head) { 21125fdd593SJeykumar Sankaran DPU_ERROR("invalid resource pool\n"); 21225fdd593SJeykumar Sankaran return; 21325fdd593SJeykumar Sankaran } 21425fdd593SJeykumar Sankaran 21525fdd593SJeykumar Sankaran crtc = _dpu_crtc_rp_to_crtc(rp); 21625fdd593SJeykumar Sankaran if (!crtc) { 21725fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 21825fdd593SJeykumar Sankaran return; 21925fdd593SJeykumar Sankaran } 22025fdd593SJeykumar Sankaran 22125fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d.%u duplicate\n", crtc->base.id, rp->sequence_id); 22225fdd593SJeykumar Sankaran 22325fdd593SJeykumar Sankaran mutex_lock(rp->rp_lock); 22425fdd593SJeykumar Sankaran dup_rp->sequence_id = rp->sequence_id + 1; 22525fdd593SJeykumar Sankaran INIT_LIST_HEAD(&dup_rp->res_list); 22625fdd593SJeykumar Sankaran dup_rp->ops = rp->ops; 22725fdd593SJeykumar Sankaran list_for_each_entry(res, &rp->res_list, list) { 22825fdd593SJeykumar Sankaran dup_res = kzalloc(sizeof(struct dpu_crtc_res), GFP_KERNEL); 22925fdd593SJeykumar Sankaran if (!dup_res) { 23025fdd593SJeykumar Sankaran mutex_unlock(rp->rp_lock); 23125fdd593SJeykumar Sankaran return; 23225fdd593SJeykumar Sankaran } 23325fdd593SJeykumar Sankaran INIT_LIST_HEAD(&dup_res->list); 23425fdd593SJeykumar Sankaran atomic_set(&dup_res->refcount, 0); 23525fdd593SJeykumar Sankaran dup_res->type = res->type; 23625fdd593SJeykumar Sankaran dup_res->tag = res->tag; 23725fdd593SJeykumar Sankaran dup_res->val = res->val; 23825fdd593SJeykumar Sankaran dup_res->ops = res->ops; 23925fdd593SJeykumar Sankaran dup_res->flags = DPU_CRTC_RES_FLAG_FREE; 24025fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d.%u dup res:0x%x/0x%llx/%pK/%d\n", 24125fdd593SJeykumar Sankaran crtc->base.id, dup_rp->sequence_id, 24225fdd593SJeykumar Sankaran dup_res->type, dup_res->tag, dup_res->val, 24325fdd593SJeykumar Sankaran atomic_read(&dup_res->refcount)); 24425fdd593SJeykumar Sankaran list_add_tail(&dup_res->list, &dup_rp->res_list); 24525fdd593SJeykumar Sankaran if (dup_res->ops.get) 24625fdd593SJeykumar Sankaran dup_res->ops.get(dup_res->val, 0, -1); 24725fdd593SJeykumar Sankaran } 24825fdd593SJeykumar Sankaran 24925fdd593SJeykumar Sankaran dup_rp->rp_lock = rp->rp_lock; 25025fdd593SJeykumar Sankaran dup_rp->rp_head = rp->rp_head; 25125fdd593SJeykumar Sankaran INIT_LIST_HEAD(&dup_rp->rp_list); 25225fdd593SJeykumar Sankaran list_add_tail(&dup_rp->rp_list, rp->rp_head); 25325fdd593SJeykumar Sankaran mutex_unlock(rp->rp_lock); 25425fdd593SJeykumar Sankaran } 25525fdd593SJeykumar Sankaran 25625fdd593SJeykumar Sankaran /** 25725fdd593SJeykumar Sankaran * _dpu_crtc_rp_reset - reset resource pool after allocation 25825fdd593SJeykumar Sankaran * @rp: Pointer to original resource pool 25925fdd593SJeykumar Sankaran * @rp_lock: Pointer to serialization resource pool lock 26025fdd593SJeykumar Sankaran * @rp_head: Pointer to crtc resource pool head 26125fdd593SJeykumar Sankaran * return: None 26225fdd593SJeykumar Sankaran */ 26325fdd593SJeykumar Sankaran static void _dpu_crtc_rp_reset(struct dpu_crtc_respool *rp, 26425fdd593SJeykumar Sankaran struct mutex *rp_lock, struct list_head *rp_head) 26525fdd593SJeykumar Sankaran { 26625fdd593SJeykumar Sankaran if (!rp || !rp_lock || !rp_head) { 26725fdd593SJeykumar Sankaran DPU_ERROR("invalid resource pool\n"); 26825fdd593SJeykumar Sankaran return; 26925fdd593SJeykumar Sankaran } 27025fdd593SJeykumar Sankaran 27125fdd593SJeykumar Sankaran mutex_lock(rp_lock); 27225fdd593SJeykumar Sankaran rp->rp_lock = rp_lock; 27325fdd593SJeykumar Sankaran rp->rp_head = rp_head; 27425fdd593SJeykumar Sankaran INIT_LIST_HEAD(&rp->rp_list); 27525fdd593SJeykumar Sankaran rp->sequence_id = 0; 27625fdd593SJeykumar Sankaran INIT_LIST_HEAD(&rp->res_list); 27725fdd593SJeykumar Sankaran rp->ops.get = _dpu_crtc_hw_blk_get; 27825fdd593SJeykumar Sankaran rp->ops.put = _dpu_crtc_hw_blk_put; 27925fdd593SJeykumar Sankaran list_add_tail(&rp->rp_list, rp->rp_head); 28025fdd593SJeykumar Sankaran mutex_unlock(rp_lock); 28125fdd593SJeykumar Sankaran } 28225fdd593SJeykumar Sankaran 28325fdd593SJeykumar Sankaran static void dpu_crtc_destroy(struct drm_crtc *crtc) 28425fdd593SJeykumar Sankaran { 28525fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 28625fdd593SJeykumar Sankaran 28725fdd593SJeykumar Sankaran DPU_DEBUG("\n"); 28825fdd593SJeykumar Sankaran 28925fdd593SJeykumar Sankaran if (!crtc) 29025fdd593SJeykumar Sankaran return; 29125fdd593SJeykumar Sankaran 29225fdd593SJeykumar Sankaran dpu_crtc->phandle = NULL; 29325fdd593SJeykumar Sankaran 29425fdd593SJeykumar Sankaran drm_crtc_cleanup(crtc); 29525fdd593SJeykumar Sankaran mutex_destroy(&dpu_crtc->crtc_lock); 29625fdd593SJeykumar Sankaran kfree(dpu_crtc); 29725fdd593SJeykumar Sankaran } 29825fdd593SJeykumar Sankaran 29925fdd593SJeykumar Sankaran static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, 30074593a28SSravanthi Kollukuduru struct dpu_plane_state *pstate, struct dpu_format *format) 30125fdd593SJeykumar Sankaran { 30225fdd593SJeykumar Sankaran struct dpu_hw_mixer *lm = mixer->hw_lm; 30374593a28SSravanthi Kollukuduru uint32_t blend_op; 30474593a28SSravanthi Kollukuduru struct drm_format_name_buf format_name; 30525fdd593SJeykumar Sankaran 30625fdd593SJeykumar Sankaran /* default to opaque blending */ 30774593a28SSravanthi Kollukuduru blend_op = DPU_BLEND_FG_ALPHA_FG_CONST | 30874593a28SSravanthi Kollukuduru DPU_BLEND_BG_ALPHA_BG_CONST; 30974593a28SSravanthi Kollukuduru 31074593a28SSravanthi Kollukuduru if (format->alpha_enable) { 31174593a28SSravanthi Kollukuduru /* coverage blending */ 31274593a28SSravanthi Kollukuduru blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL | 31374593a28SSravanthi Kollukuduru DPU_BLEND_BG_ALPHA_FG_PIXEL | 31474593a28SSravanthi Kollukuduru DPU_BLEND_BG_INV_ALPHA; 31574593a28SSravanthi Kollukuduru } 31674593a28SSravanthi Kollukuduru 31774593a28SSravanthi Kollukuduru lm->ops.setup_blend_config(lm, pstate->stage, 31874593a28SSravanthi Kollukuduru 0xFF, 0, blend_op); 31974593a28SSravanthi Kollukuduru 32074593a28SSravanthi Kollukuduru DPU_DEBUG("format:%s, alpha_en:%u blend_op:0x%x\n", 32174593a28SSravanthi Kollukuduru drm_get_format_name(format->base.pixel_format, &format_name), 32274593a28SSravanthi Kollukuduru format->alpha_enable, blend_op); 32325fdd593SJeykumar Sankaran } 32425fdd593SJeykumar Sankaran 32525fdd593SJeykumar Sankaran static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) 32625fdd593SJeykumar Sankaran { 32725fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 32825fdd593SJeykumar Sankaran struct dpu_crtc_state *crtc_state; 32925fdd593SJeykumar Sankaran int lm_idx, lm_horiz_position; 33025fdd593SJeykumar Sankaran 33125fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 33225fdd593SJeykumar Sankaran crtc_state = to_dpu_crtc_state(crtc->state); 33325fdd593SJeykumar Sankaran 33425fdd593SJeykumar Sankaran lm_horiz_position = 0; 33525fdd593SJeykumar Sankaran for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) { 33625fdd593SJeykumar Sankaran const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx]; 33725fdd593SJeykumar Sankaran struct dpu_hw_mixer *hw_lm = dpu_crtc->mixers[lm_idx].hw_lm; 33825fdd593SJeykumar Sankaran struct dpu_hw_mixer_cfg cfg; 33925fdd593SJeykumar Sankaran 34025fdd593SJeykumar Sankaran if (!lm_roi || !drm_rect_visible(lm_roi)) 34125fdd593SJeykumar Sankaran continue; 34225fdd593SJeykumar Sankaran 34325fdd593SJeykumar Sankaran cfg.out_width = drm_rect_width(lm_roi); 34425fdd593SJeykumar Sankaran cfg.out_height = drm_rect_height(lm_roi); 34525fdd593SJeykumar Sankaran cfg.right_mixer = lm_horiz_position++; 34625fdd593SJeykumar Sankaran cfg.flags = 0; 34725fdd593SJeykumar Sankaran hw_lm->ops.setup_mixer_out(hw_lm, &cfg); 34825fdd593SJeykumar Sankaran } 34925fdd593SJeykumar Sankaran } 35025fdd593SJeykumar Sankaran 35125fdd593SJeykumar Sankaran static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, 35225fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer) 35325fdd593SJeykumar Sankaran { 35425fdd593SJeykumar Sankaran struct drm_plane *plane; 35525fdd593SJeykumar Sankaran struct drm_framebuffer *fb; 35625fdd593SJeykumar Sankaran struct drm_plane_state *state; 35725fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 35825fdd593SJeykumar Sankaran struct dpu_plane_state *pstate = NULL; 35925fdd593SJeykumar Sankaran struct dpu_format *format; 36025fdd593SJeykumar Sankaran struct dpu_hw_ctl *ctl; 36125fdd593SJeykumar Sankaran struct dpu_hw_mixer *lm; 36225fdd593SJeykumar Sankaran struct dpu_hw_stage_cfg *stage_cfg; 36325fdd593SJeykumar Sankaran 36425fdd593SJeykumar Sankaran u32 flush_mask; 36525fdd593SJeykumar Sankaran uint32_t stage_idx, lm_idx; 36625fdd593SJeykumar Sankaran int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 }; 36725fdd593SJeykumar Sankaran bool bg_alpha_enable = false; 36825fdd593SJeykumar Sankaran 36925fdd593SJeykumar Sankaran if (!dpu_crtc || !mixer) { 37025fdd593SJeykumar Sankaran DPU_ERROR("invalid dpu_crtc or mixer\n"); 37125fdd593SJeykumar Sankaran return; 37225fdd593SJeykumar Sankaran } 37325fdd593SJeykumar Sankaran 37425fdd593SJeykumar Sankaran ctl = mixer->hw_ctl; 37525fdd593SJeykumar Sankaran lm = mixer->hw_lm; 37625fdd593SJeykumar Sankaran stage_cfg = &dpu_crtc->stage_cfg; 37725fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(crtc->state); 37825fdd593SJeykumar Sankaran 37925fdd593SJeykumar Sankaran drm_atomic_crtc_for_each_plane(plane, crtc) { 38025fdd593SJeykumar Sankaran state = plane->state; 38125fdd593SJeykumar Sankaran if (!state) 38225fdd593SJeykumar Sankaran continue; 38325fdd593SJeykumar Sankaran 38425fdd593SJeykumar Sankaran pstate = to_dpu_plane_state(state); 38525fdd593SJeykumar Sankaran fb = state->fb; 38625fdd593SJeykumar Sankaran 38725fdd593SJeykumar Sankaran dpu_plane_get_ctl_flush(plane, ctl, &flush_mask); 38825fdd593SJeykumar Sankaran 38925fdd593SJeykumar Sankaran DPU_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n", 39025fdd593SJeykumar Sankaran crtc->base.id, 39125fdd593SJeykumar Sankaran pstate->stage, 39225fdd593SJeykumar Sankaran plane->base.id, 39325fdd593SJeykumar Sankaran dpu_plane_pipe(plane) - SSPP_VIG0, 39425fdd593SJeykumar Sankaran state->fb ? state->fb->base.id : -1); 39525fdd593SJeykumar Sankaran 39625fdd593SJeykumar Sankaran format = to_dpu_format(msm_framebuffer_format(pstate->base.fb)); 39725fdd593SJeykumar Sankaran if (!format) { 39825fdd593SJeykumar Sankaran DPU_ERROR("invalid format\n"); 39925fdd593SJeykumar Sankaran return; 40025fdd593SJeykumar Sankaran } 40125fdd593SJeykumar Sankaran 40225fdd593SJeykumar Sankaran if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) 40325fdd593SJeykumar Sankaran bg_alpha_enable = true; 40425fdd593SJeykumar Sankaran 40525fdd593SJeykumar Sankaran stage_idx = zpos_cnt[pstate->stage]++; 40625fdd593SJeykumar Sankaran stage_cfg->stage[pstate->stage][stage_idx] = 40725fdd593SJeykumar Sankaran dpu_plane_pipe(plane); 40825fdd593SJeykumar Sankaran stage_cfg->multirect_index[pstate->stage][stage_idx] = 40925fdd593SJeykumar Sankaran pstate->multirect_index; 41025fdd593SJeykumar Sankaran 41125fdd593SJeykumar Sankaran trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), 41225fdd593SJeykumar Sankaran state, pstate, stage_idx, 41325fdd593SJeykumar Sankaran dpu_plane_pipe(plane) - SSPP_VIG0, 41425fdd593SJeykumar Sankaran format->base.pixel_format, 41525fdd593SJeykumar Sankaran fb ? fb->modifier : 0); 41625fdd593SJeykumar Sankaran 41725fdd593SJeykumar Sankaran /* blend config update */ 41825fdd593SJeykumar Sankaran for (lm_idx = 0; lm_idx < dpu_crtc->num_mixers; lm_idx++) { 41974593a28SSravanthi Kollukuduru _dpu_crtc_setup_blend_cfg(mixer + lm_idx, 42074593a28SSravanthi Kollukuduru pstate, format); 42125fdd593SJeykumar Sankaran 42225fdd593SJeykumar Sankaran mixer[lm_idx].flush_mask |= flush_mask; 42325fdd593SJeykumar Sankaran 42425fdd593SJeykumar Sankaran if (bg_alpha_enable && !format->alpha_enable) 42525fdd593SJeykumar Sankaran mixer[lm_idx].mixer_op_mode = 0; 42625fdd593SJeykumar Sankaran else 42725fdd593SJeykumar Sankaran mixer[lm_idx].mixer_op_mode |= 42825fdd593SJeykumar Sankaran 1 << pstate->stage; 42925fdd593SJeykumar Sankaran } 43025fdd593SJeykumar Sankaran } 43125fdd593SJeykumar Sankaran 43225fdd593SJeykumar Sankaran _dpu_crtc_program_lm_output_roi(crtc); 43325fdd593SJeykumar Sankaran } 43425fdd593SJeykumar Sankaran 43525fdd593SJeykumar Sankaran /** 43625fdd593SJeykumar Sankaran * _dpu_crtc_blend_setup - configure crtc mixers 43725fdd593SJeykumar Sankaran * @crtc: Pointer to drm crtc structure 43825fdd593SJeykumar Sankaran */ 43925fdd593SJeykumar Sankaran static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) 44025fdd593SJeykumar Sankaran { 44125fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 44225fdd593SJeykumar Sankaran struct dpu_crtc_state *dpu_crtc_state; 44325fdd593SJeykumar Sankaran struct dpu_crtc_mixer *mixer; 44425fdd593SJeykumar Sankaran struct dpu_hw_ctl *ctl; 44525fdd593SJeykumar Sankaran struct dpu_hw_mixer *lm; 44625fdd593SJeykumar Sankaran 44725fdd593SJeykumar Sankaran int i; 44825fdd593SJeykumar Sankaran 44925fdd593SJeykumar Sankaran if (!crtc) 45025fdd593SJeykumar Sankaran return; 45125fdd593SJeykumar Sankaran 45225fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 45325fdd593SJeykumar Sankaran dpu_crtc_state = to_dpu_crtc_state(crtc->state); 45425fdd593SJeykumar Sankaran mixer = dpu_crtc->mixers; 45525fdd593SJeykumar Sankaran 45625fdd593SJeykumar Sankaran DPU_DEBUG("%s\n", dpu_crtc->name); 45725fdd593SJeykumar Sankaran 45825fdd593SJeykumar Sankaran if (dpu_crtc->num_mixers > CRTC_DUAL_MIXERS) { 45925fdd593SJeykumar Sankaran DPU_ERROR("invalid number mixers: %d\n", dpu_crtc->num_mixers); 46025fdd593SJeykumar Sankaran return; 46125fdd593SJeykumar Sankaran } 46225fdd593SJeykumar Sankaran 46325fdd593SJeykumar Sankaran for (i = 0; i < dpu_crtc->num_mixers; i++) { 46425fdd593SJeykumar Sankaran if (!mixer[i].hw_lm || !mixer[i].hw_ctl) { 46525fdd593SJeykumar Sankaran DPU_ERROR("invalid lm or ctl assigned to mixer\n"); 46625fdd593SJeykumar Sankaran return; 46725fdd593SJeykumar Sankaran } 46825fdd593SJeykumar Sankaran mixer[i].mixer_op_mode = 0; 46925fdd593SJeykumar Sankaran mixer[i].flush_mask = 0; 47025fdd593SJeykumar Sankaran if (mixer[i].hw_ctl->ops.clear_all_blendstages) 47125fdd593SJeykumar Sankaran mixer[i].hw_ctl->ops.clear_all_blendstages( 47225fdd593SJeykumar Sankaran mixer[i].hw_ctl); 47325fdd593SJeykumar Sankaran } 47425fdd593SJeykumar Sankaran 47525fdd593SJeykumar Sankaran /* initialize stage cfg */ 47625fdd593SJeykumar Sankaran memset(&dpu_crtc->stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg)); 47725fdd593SJeykumar Sankaran 47825fdd593SJeykumar Sankaran _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer); 47925fdd593SJeykumar Sankaran 48025fdd593SJeykumar Sankaran for (i = 0; i < dpu_crtc->num_mixers; i++) { 48125fdd593SJeykumar Sankaran ctl = mixer[i].hw_ctl; 48225fdd593SJeykumar Sankaran lm = mixer[i].hw_lm; 48325fdd593SJeykumar Sankaran 48425fdd593SJeykumar Sankaran lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode); 48525fdd593SJeykumar Sankaran 48625fdd593SJeykumar Sankaran mixer[i].flush_mask |= ctl->ops.get_bitmask_mixer(ctl, 48725fdd593SJeykumar Sankaran mixer[i].hw_lm->idx); 48825fdd593SJeykumar Sankaran 48925fdd593SJeykumar Sankaran /* stage config flush mask */ 49025fdd593SJeykumar Sankaran ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); 49125fdd593SJeykumar Sankaran 49225fdd593SJeykumar Sankaran DPU_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n", 49325fdd593SJeykumar Sankaran mixer[i].hw_lm->idx - LM_0, 49425fdd593SJeykumar Sankaran mixer[i].mixer_op_mode, 49525fdd593SJeykumar Sankaran ctl->idx - CTL_0, 49625fdd593SJeykumar Sankaran mixer[i].flush_mask); 49725fdd593SJeykumar Sankaran 49825fdd593SJeykumar Sankaran ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, 49925fdd593SJeykumar Sankaran &dpu_crtc->stage_cfg); 50025fdd593SJeykumar Sankaran } 50125fdd593SJeykumar Sankaran } 50225fdd593SJeykumar Sankaran 50325fdd593SJeykumar Sankaran /** 50425fdd593SJeykumar Sankaran * _dpu_crtc_complete_flip - signal pending page_flip events 50525fdd593SJeykumar Sankaran * Any pending vblank events are added to the vblank_event_list 50625fdd593SJeykumar Sankaran * so that the next vblank interrupt shall signal them. 50725fdd593SJeykumar Sankaran * However PAGE_FLIP events are not handled through the vblank_event_list. 50825fdd593SJeykumar Sankaran * This API signals any pending PAGE_FLIP events requested through 50925fdd593SJeykumar Sankaran * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the dpu_crtc->event. 51025fdd593SJeykumar Sankaran * @crtc: Pointer to drm crtc structure 51125fdd593SJeykumar Sankaran */ 51225fdd593SJeykumar Sankaran static void _dpu_crtc_complete_flip(struct drm_crtc *crtc) 51325fdd593SJeykumar Sankaran { 51425fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 51525fdd593SJeykumar Sankaran struct drm_device *dev = crtc->dev; 51625fdd593SJeykumar Sankaran unsigned long flags; 51725fdd593SJeykumar Sankaran 51825fdd593SJeykumar Sankaran spin_lock_irqsave(&dev->event_lock, flags); 51925fdd593SJeykumar Sankaran if (dpu_crtc->event) { 52025fdd593SJeykumar Sankaran DRM_DEBUG_VBL("%s: send event: %pK\n", dpu_crtc->name, 52125fdd593SJeykumar Sankaran dpu_crtc->event); 52225fdd593SJeykumar Sankaran trace_dpu_crtc_complete_flip(DRMID(crtc)); 52325fdd593SJeykumar Sankaran drm_crtc_send_vblank_event(crtc, dpu_crtc->event); 52425fdd593SJeykumar Sankaran dpu_crtc->event = NULL; 52525fdd593SJeykumar Sankaran } 52625fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dev->event_lock, flags); 52725fdd593SJeykumar Sankaran } 52825fdd593SJeykumar Sankaran 52925fdd593SJeykumar Sankaran enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc) 53025fdd593SJeykumar Sankaran { 53125fdd593SJeykumar Sankaran struct drm_encoder *encoder; 53225fdd593SJeykumar Sankaran 53325fdd593SJeykumar Sankaran if (!crtc || !crtc->dev) { 53425fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 53525fdd593SJeykumar Sankaran return INTF_MODE_NONE; 53625fdd593SJeykumar Sankaran } 53725fdd593SJeykumar Sankaran 53825fdd593SJeykumar Sankaran drm_for_each_encoder(encoder, crtc->dev) 53925fdd593SJeykumar Sankaran if (encoder->crtc == crtc) 54025fdd593SJeykumar Sankaran return dpu_encoder_get_intf_mode(encoder); 54125fdd593SJeykumar Sankaran 54225fdd593SJeykumar Sankaran return INTF_MODE_NONE; 54325fdd593SJeykumar Sankaran } 54425fdd593SJeykumar Sankaran 54525fdd593SJeykumar Sankaran static void dpu_crtc_vblank_cb(void *data) 54625fdd593SJeykumar Sankaran { 54725fdd593SJeykumar Sankaran struct drm_crtc *crtc = (struct drm_crtc *)data; 54825fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 54925fdd593SJeykumar Sankaran 55025fdd593SJeykumar Sankaran /* keep statistics on vblank callback - with auto reset via debugfs */ 55125fdd593SJeykumar Sankaran if (ktime_compare(dpu_crtc->vblank_cb_time, ktime_set(0, 0)) == 0) 55225fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_time = ktime_get(); 55325fdd593SJeykumar Sankaran else 55425fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_count++; 55525fdd593SJeykumar Sankaran _dpu_crtc_complete_flip(crtc); 55625fdd593SJeykumar Sankaran drm_crtc_handle_vblank(crtc); 55725fdd593SJeykumar Sankaran trace_dpu_crtc_vblank_cb(DRMID(crtc)); 55825fdd593SJeykumar Sankaran } 55925fdd593SJeykumar Sankaran 56025fdd593SJeykumar Sankaran static void dpu_crtc_frame_event_work(struct kthread_work *work) 56125fdd593SJeykumar Sankaran { 56225fdd593SJeykumar Sankaran struct msm_drm_private *priv; 56325fdd593SJeykumar Sankaran struct dpu_crtc_frame_event *fevent; 56425fdd593SJeykumar Sankaran struct drm_crtc *crtc; 56525fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 56625fdd593SJeykumar Sankaran struct dpu_kms *dpu_kms; 56725fdd593SJeykumar Sankaran unsigned long flags; 56825fdd593SJeykumar Sankaran bool frame_done = false; 56925fdd593SJeykumar Sankaran 57025fdd593SJeykumar Sankaran if (!work) { 57125fdd593SJeykumar Sankaran DPU_ERROR("invalid work handle\n"); 57225fdd593SJeykumar Sankaran return; 57325fdd593SJeykumar Sankaran } 57425fdd593SJeykumar Sankaran 57525fdd593SJeykumar Sankaran fevent = container_of(work, struct dpu_crtc_frame_event, work); 57625fdd593SJeykumar Sankaran if (!fevent->crtc || !fevent->crtc->state) { 57725fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 57825fdd593SJeykumar Sankaran return; 57925fdd593SJeykumar Sankaran } 58025fdd593SJeykumar Sankaran 58125fdd593SJeykumar Sankaran crtc = fevent->crtc; 58225fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 58325fdd593SJeykumar Sankaran 58425fdd593SJeykumar Sankaran dpu_kms = _dpu_crtc_get_kms(crtc); 58525fdd593SJeykumar Sankaran if (!dpu_kms) { 58625fdd593SJeykumar Sankaran DPU_ERROR("invalid kms handle\n"); 58725fdd593SJeykumar Sankaran return; 58825fdd593SJeykumar Sankaran } 58925fdd593SJeykumar Sankaran priv = dpu_kms->dev->dev_private; 59025fdd593SJeykumar Sankaran DPU_ATRACE_BEGIN("crtc_frame_event"); 59125fdd593SJeykumar Sankaran 59225fdd593SJeykumar Sankaran DRM_DEBUG_KMS("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event, 59325fdd593SJeykumar Sankaran ktime_to_ns(fevent->ts)); 59425fdd593SJeykumar Sankaran 59525fdd593SJeykumar Sankaran if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE 59625fdd593SJeykumar Sankaran | DPU_ENCODER_FRAME_EVENT_ERROR 59725fdd593SJeykumar Sankaran | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) { 59825fdd593SJeykumar Sankaran 59925fdd593SJeykumar Sankaran if (atomic_read(&dpu_crtc->frame_pending) < 1) { 60025fdd593SJeykumar Sankaran /* this should not happen */ 60125fdd593SJeykumar Sankaran DRM_ERROR("crtc%d ev:%u ts:%lld frame_pending:%d\n", 60225fdd593SJeykumar Sankaran crtc->base.id, 60325fdd593SJeykumar Sankaran fevent->event, 60425fdd593SJeykumar Sankaran ktime_to_ns(fevent->ts), 60525fdd593SJeykumar Sankaran atomic_read(&dpu_crtc->frame_pending)); 60625fdd593SJeykumar Sankaran } else if (atomic_dec_return(&dpu_crtc->frame_pending) == 0) { 60725fdd593SJeykumar Sankaran /* release bandwidth and other resources */ 60825fdd593SJeykumar Sankaran trace_dpu_crtc_frame_event_done(DRMID(crtc), 60925fdd593SJeykumar Sankaran fevent->event); 61025fdd593SJeykumar Sankaran dpu_core_perf_crtc_release_bw(crtc); 61125fdd593SJeykumar Sankaran } else { 61225fdd593SJeykumar Sankaran trace_dpu_crtc_frame_event_more_pending(DRMID(crtc), 61325fdd593SJeykumar Sankaran fevent->event); 61425fdd593SJeykumar Sankaran } 61525fdd593SJeykumar Sankaran 61625fdd593SJeykumar Sankaran if (fevent->event & DPU_ENCODER_FRAME_EVENT_DONE) 61725fdd593SJeykumar Sankaran dpu_core_perf_crtc_update(crtc, 0, false); 61825fdd593SJeykumar Sankaran 61925fdd593SJeykumar Sankaran if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE 62025fdd593SJeykumar Sankaran | DPU_ENCODER_FRAME_EVENT_ERROR)) 62125fdd593SJeykumar Sankaran frame_done = true; 62225fdd593SJeykumar Sankaran } 62325fdd593SJeykumar Sankaran 62425fdd593SJeykumar Sankaran if (fevent->event & DPU_ENCODER_FRAME_EVENT_PANEL_DEAD) 62525fdd593SJeykumar Sankaran DPU_ERROR("crtc%d ts:%lld received panel dead event\n", 62625fdd593SJeykumar Sankaran crtc->base.id, ktime_to_ns(fevent->ts)); 62725fdd593SJeykumar Sankaran 62825fdd593SJeykumar Sankaran if (frame_done) 62925fdd593SJeykumar Sankaran complete_all(&dpu_crtc->frame_done_comp); 63025fdd593SJeykumar Sankaran 63125fdd593SJeykumar Sankaran spin_lock_irqsave(&dpu_crtc->spin_lock, flags); 63225fdd593SJeykumar Sankaran list_add_tail(&fevent->list, &dpu_crtc->frame_event_list); 63325fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags); 63425fdd593SJeykumar Sankaran DPU_ATRACE_END("crtc_frame_event"); 63525fdd593SJeykumar Sankaran } 63625fdd593SJeykumar Sankaran 63725fdd593SJeykumar Sankaran /* 63825fdd593SJeykumar Sankaran * dpu_crtc_frame_event_cb - crtc frame event callback API. CRTC module 63925fdd593SJeykumar Sankaran * registers this API to encoder for all frame event callbacks like 64025fdd593SJeykumar Sankaran * frame_error, frame_done, idle_timeout, etc. Encoder may call different events 64125fdd593SJeykumar Sankaran * from different context - IRQ, user thread, commit_thread, etc. Each event 64225fdd593SJeykumar Sankaran * should be carefully reviewed and should be processed in proper task context 64325fdd593SJeykumar Sankaran * to avoid schedulin delay or properly manage the irq context's bottom half 64425fdd593SJeykumar Sankaran * processing. 64525fdd593SJeykumar Sankaran */ 64625fdd593SJeykumar Sankaran static void dpu_crtc_frame_event_cb(void *data, u32 event) 64725fdd593SJeykumar Sankaran { 64825fdd593SJeykumar Sankaran struct drm_crtc *crtc = (struct drm_crtc *)data; 64925fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 65025fdd593SJeykumar Sankaran struct msm_drm_private *priv; 65125fdd593SJeykumar Sankaran struct dpu_crtc_frame_event *fevent; 65225fdd593SJeykumar Sankaran unsigned long flags; 65325fdd593SJeykumar Sankaran u32 crtc_id; 65425fdd593SJeykumar Sankaran 65525fdd593SJeykumar Sankaran if (!crtc || !crtc->dev || !crtc->dev->dev_private) { 65625fdd593SJeykumar Sankaran DPU_ERROR("invalid parameters\n"); 65725fdd593SJeykumar Sankaran return; 65825fdd593SJeykumar Sankaran } 65925fdd593SJeykumar Sankaran 66025fdd593SJeykumar Sankaran /* Nothing to do on idle event */ 66125fdd593SJeykumar Sankaran if (event & DPU_ENCODER_FRAME_EVENT_IDLE) 66225fdd593SJeykumar Sankaran return; 66325fdd593SJeykumar Sankaran 66425fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 66525fdd593SJeykumar Sankaran priv = crtc->dev->dev_private; 66625fdd593SJeykumar Sankaran crtc_id = drm_crtc_index(crtc); 66725fdd593SJeykumar Sankaran 66825fdd593SJeykumar Sankaran trace_dpu_crtc_frame_event_cb(DRMID(crtc), event); 66925fdd593SJeykumar Sankaran 67025fdd593SJeykumar Sankaran spin_lock_irqsave(&dpu_crtc->spin_lock, flags); 67125fdd593SJeykumar Sankaran fevent = list_first_entry_or_null(&dpu_crtc->frame_event_list, 67225fdd593SJeykumar Sankaran struct dpu_crtc_frame_event, list); 67325fdd593SJeykumar Sankaran if (fevent) 67425fdd593SJeykumar Sankaran list_del_init(&fevent->list); 67525fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags); 67625fdd593SJeykumar Sankaran 67725fdd593SJeykumar Sankaran if (!fevent) { 67825fdd593SJeykumar Sankaran DRM_ERROR("crtc%d event %d overflow\n", crtc->base.id, event); 67925fdd593SJeykumar Sankaran return; 68025fdd593SJeykumar Sankaran } 68125fdd593SJeykumar Sankaran 68225fdd593SJeykumar Sankaran fevent->event = event; 68325fdd593SJeykumar Sankaran fevent->crtc = crtc; 68425fdd593SJeykumar Sankaran fevent->ts = ktime_get(); 68525fdd593SJeykumar Sankaran kthread_queue_work(&priv->event_thread[crtc_id].worker, &fevent->work); 68625fdd593SJeykumar Sankaran } 68725fdd593SJeykumar Sankaran 68825fdd593SJeykumar Sankaran void dpu_crtc_complete_commit(struct drm_crtc *crtc, 68925fdd593SJeykumar Sankaran struct drm_crtc_state *old_state) 69025fdd593SJeykumar Sankaran { 69125fdd593SJeykumar Sankaran if (!crtc || !crtc->state) { 69225fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 69325fdd593SJeykumar Sankaran return; 69425fdd593SJeykumar Sankaran } 69525fdd593SJeykumar Sankaran trace_dpu_crtc_complete_commit(DRMID(crtc)); 69625fdd593SJeykumar Sankaran } 69725fdd593SJeykumar Sankaran 69825fdd593SJeykumar Sankaran static void _dpu_crtc_setup_mixer_for_encoder( 69925fdd593SJeykumar Sankaran struct drm_crtc *crtc, 70025fdd593SJeykumar Sankaran struct drm_encoder *enc) 70125fdd593SJeykumar Sankaran { 70225fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 70325fdd593SJeykumar Sankaran struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); 70425fdd593SJeykumar Sankaran struct dpu_rm *rm = &dpu_kms->rm; 70525fdd593SJeykumar Sankaran struct dpu_crtc_mixer *mixer; 70625fdd593SJeykumar Sankaran struct dpu_hw_ctl *last_valid_ctl = NULL; 70725fdd593SJeykumar Sankaran int i; 70825fdd593SJeykumar Sankaran struct dpu_rm_hw_iter lm_iter, ctl_iter; 70925fdd593SJeykumar Sankaran 71025fdd593SJeykumar Sankaran dpu_rm_init_hw_iter(&lm_iter, enc->base.id, DPU_HW_BLK_LM); 71125fdd593SJeykumar Sankaran dpu_rm_init_hw_iter(&ctl_iter, enc->base.id, DPU_HW_BLK_CTL); 71225fdd593SJeykumar Sankaran 71325fdd593SJeykumar Sankaran /* Set up all the mixers and ctls reserved by this encoder */ 71425fdd593SJeykumar Sankaran for (i = dpu_crtc->num_mixers; i < ARRAY_SIZE(dpu_crtc->mixers); i++) { 71525fdd593SJeykumar Sankaran mixer = &dpu_crtc->mixers[i]; 71625fdd593SJeykumar Sankaran 71725fdd593SJeykumar Sankaran if (!dpu_rm_get_hw(rm, &lm_iter)) 71825fdd593SJeykumar Sankaran break; 71925fdd593SJeykumar Sankaran mixer->hw_lm = (struct dpu_hw_mixer *)lm_iter.hw; 72025fdd593SJeykumar Sankaran 72125fdd593SJeykumar Sankaran /* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */ 72225fdd593SJeykumar Sankaran if (!dpu_rm_get_hw(rm, &ctl_iter)) { 72325fdd593SJeykumar Sankaran DPU_DEBUG("no ctl assigned to lm %d, using previous\n", 72425fdd593SJeykumar Sankaran mixer->hw_lm->idx - LM_0); 72525fdd593SJeykumar Sankaran mixer->hw_ctl = last_valid_ctl; 72625fdd593SJeykumar Sankaran } else { 72725fdd593SJeykumar Sankaran mixer->hw_ctl = (struct dpu_hw_ctl *)ctl_iter.hw; 72825fdd593SJeykumar Sankaran last_valid_ctl = mixer->hw_ctl; 72925fdd593SJeykumar Sankaran } 73025fdd593SJeykumar Sankaran 73125fdd593SJeykumar Sankaran /* Shouldn't happen, mixers are always >= ctls */ 73225fdd593SJeykumar Sankaran if (!mixer->hw_ctl) { 73325fdd593SJeykumar Sankaran DPU_ERROR("no valid ctls found for lm %d\n", 73425fdd593SJeykumar Sankaran mixer->hw_lm->idx - LM_0); 73525fdd593SJeykumar Sankaran return; 73625fdd593SJeykumar Sankaran } 73725fdd593SJeykumar Sankaran 73825fdd593SJeykumar Sankaran mixer->encoder = enc; 73925fdd593SJeykumar Sankaran 74025fdd593SJeykumar Sankaran dpu_crtc->num_mixers++; 74125fdd593SJeykumar Sankaran DPU_DEBUG("setup mixer %d: lm %d\n", 74225fdd593SJeykumar Sankaran i, mixer->hw_lm->idx - LM_0); 74325fdd593SJeykumar Sankaran DPU_DEBUG("setup mixer %d: ctl %d\n", 74425fdd593SJeykumar Sankaran i, mixer->hw_ctl->idx - CTL_0); 74525fdd593SJeykumar Sankaran } 74625fdd593SJeykumar Sankaran } 74725fdd593SJeykumar Sankaran 74825fdd593SJeykumar Sankaran static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc) 74925fdd593SJeykumar Sankaran { 75025fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 75125fdd593SJeykumar Sankaran struct drm_encoder *enc; 75225fdd593SJeykumar Sankaran 75325fdd593SJeykumar Sankaran dpu_crtc->num_mixers = 0; 75425fdd593SJeykumar Sankaran dpu_crtc->mixers_swapped = false; 75525fdd593SJeykumar Sankaran memset(dpu_crtc->mixers, 0, sizeof(dpu_crtc->mixers)); 75625fdd593SJeykumar Sankaran 75725fdd593SJeykumar Sankaran mutex_lock(&dpu_crtc->crtc_lock); 75825fdd593SJeykumar Sankaran /* Check for mixers on all encoders attached to this crtc */ 75925fdd593SJeykumar Sankaran list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) { 76025fdd593SJeykumar Sankaran if (enc->crtc != crtc) 76125fdd593SJeykumar Sankaran continue; 76225fdd593SJeykumar Sankaran 76325fdd593SJeykumar Sankaran _dpu_crtc_setup_mixer_for_encoder(crtc, enc); 76425fdd593SJeykumar Sankaran } 76525fdd593SJeykumar Sankaran 76625fdd593SJeykumar Sankaran mutex_unlock(&dpu_crtc->crtc_lock); 76725fdd593SJeykumar Sankaran } 76825fdd593SJeykumar Sankaran 76925fdd593SJeykumar Sankaran static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc, 77025fdd593SJeykumar Sankaran struct drm_crtc_state *state) 77125fdd593SJeykumar Sankaran { 77225fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 77325fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 77425fdd593SJeykumar Sankaran struct drm_display_mode *adj_mode; 77525fdd593SJeykumar Sankaran u32 crtc_split_width; 77625fdd593SJeykumar Sankaran int i; 77725fdd593SJeykumar Sankaran 77825fdd593SJeykumar Sankaran if (!crtc || !state) { 77925fdd593SJeykumar Sankaran DPU_ERROR("invalid args\n"); 78025fdd593SJeykumar Sankaran return; 78125fdd593SJeykumar Sankaran } 78225fdd593SJeykumar Sankaran 78325fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 78425fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(state); 78525fdd593SJeykumar Sankaran 78625fdd593SJeykumar Sankaran adj_mode = &state->adjusted_mode; 78725fdd593SJeykumar Sankaran crtc_split_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, adj_mode); 78825fdd593SJeykumar Sankaran 78925fdd593SJeykumar Sankaran for (i = 0; i < dpu_crtc->num_mixers; i++) { 79025fdd593SJeykumar Sankaran struct drm_rect *r = &cstate->lm_bounds[i]; 79125fdd593SJeykumar Sankaran r->x1 = crtc_split_width * i; 79225fdd593SJeykumar Sankaran r->y1 = 0; 79325fdd593SJeykumar Sankaran r->x2 = r->x1 + crtc_split_width; 79425fdd593SJeykumar Sankaran r->y2 = dpu_crtc_get_mixer_height(dpu_crtc, cstate, adj_mode); 79525fdd593SJeykumar Sankaran 79625fdd593SJeykumar Sankaran trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i, r); 79725fdd593SJeykumar Sankaran } 79825fdd593SJeykumar Sankaran 79925fdd593SJeykumar Sankaran drm_mode_debug_printmodeline(adj_mode); 80025fdd593SJeykumar Sankaran } 80125fdd593SJeykumar Sankaran 80225fdd593SJeykumar Sankaran static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, 80325fdd593SJeykumar Sankaran struct drm_crtc_state *old_state) 80425fdd593SJeykumar Sankaran { 80525fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 80625fdd593SJeykumar Sankaran struct drm_encoder *encoder; 80725fdd593SJeykumar Sankaran struct drm_device *dev; 80825fdd593SJeykumar Sankaran unsigned long flags; 80925fdd593SJeykumar Sankaran struct dpu_crtc_smmu_state_data *smmu_state; 81025fdd593SJeykumar Sankaran 81125fdd593SJeykumar Sankaran if (!crtc) { 81225fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 81325fdd593SJeykumar Sankaran return; 81425fdd593SJeykumar Sankaran } 81525fdd593SJeykumar Sankaran 81625fdd593SJeykumar Sankaran if (!crtc->state->enable) { 81725fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d -> enable %d, skip atomic_begin\n", 81825fdd593SJeykumar Sankaran crtc->base.id, crtc->state->enable); 81925fdd593SJeykumar Sankaran return; 82025fdd593SJeykumar Sankaran } 82125fdd593SJeykumar Sankaran 82225fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d\n", crtc->base.id); 82325fdd593SJeykumar Sankaran 82425fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 82525fdd593SJeykumar Sankaran dev = crtc->dev; 82625fdd593SJeykumar Sankaran smmu_state = &dpu_crtc->smmu_state; 82725fdd593SJeykumar Sankaran 82825fdd593SJeykumar Sankaran if (!dpu_crtc->num_mixers) { 82925fdd593SJeykumar Sankaran _dpu_crtc_setup_mixers(crtc); 83025fdd593SJeykumar Sankaran _dpu_crtc_setup_lm_bounds(crtc, crtc->state); 83125fdd593SJeykumar Sankaran } 83225fdd593SJeykumar Sankaran 83325fdd593SJeykumar Sankaran if (dpu_crtc->event) { 83425fdd593SJeykumar Sankaran WARN_ON(dpu_crtc->event); 83525fdd593SJeykumar Sankaran } else { 83625fdd593SJeykumar Sankaran spin_lock_irqsave(&dev->event_lock, flags); 83725fdd593SJeykumar Sankaran dpu_crtc->event = crtc->state->event; 83825fdd593SJeykumar Sankaran crtc->state->event = NULL; 83925fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dev->event_lock, flags); 84025fdd593SJeykumar Sankaran } 84125fdd593SJeykumar Sankaran 84225fdd593SJeykumar Sankaran list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 84325fdd593SJeykumar Sankaran if (encoder->crtc != crtc) 84425fdd593SJeykumar Sankaran continue; 84525fdd593SJeykumar Sankaran 84625fdd593SJeykumar Sankaran /* encoder will trigger pending mask now */ 84725fdd593SJeykumar Sankaran dpu_encoder_trigger_kickoff_pending(encoder); 84825fdd593SJeykumar Sankaran } 84925fdd593SJeykumar Sankaran 85025fdd593SJeykumar Sankaran /* 85125fdd593SJeykumar Sankaran * If no mixers have been allocated in dpu_crtc_atomic_check(), 85225fdd593SJeykumar Sankaran * it means we are trying to flush a CRTC whose state is disabled: 85325fdd593SJeykumar Sankaran * nothing else needs to be done. 85425fdd593SJeykumar Sankaran */ 85525fdd593SJeykumar Sankaran if (unlikely(!dpu_crtc->num_mixers)) 85625fdd593SJeykumar Sankaran return; 85725fdd593SJeykumar Sankaran 85825fdd593SJeykumar Sankaran _dpu_crtc_blend_setup(crtc); 85925fdd593SJeykumar Sankaran 86025fdd593SJeykumar Sankaran /* 86125fdd593SJeykumar Sankaran * PP_DONE irq is only used by command mode for now. 86225fdd593SJeykumar Sankaran * It is better to request pending before FLUSH and START trigger 86325fdd593SJeykumar Sankaran * to make sure no pp_done irq missed. 86425fdd593SJeykumar Sankaran * This is safe because no pp_done will happen before SW trigger 86525fdd593SJeykumar Sankaran * in command mode. 86625fdd593SJeykumar Sankaran */ 86725fdd593SJeykumar Sankaran } 86825fdd593SJeykumar Sankaran 86925fdd593SJeykumar Sankaran static void dpu_crtc_atomic_flush(struct drm_crtc *crtc, 87025fdd593SJeykumar Sankaran struct drm_crtc_state *old_crtc_state) 87125fdd593SJeykumar Sankaran { 87225fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 87325fdd593SJeykumar Sankaran struct drm_device *dev; 87425fdd593SJeykumar Sankaran struct drm_plane *plane; 87525fdd593SJeykumar Sankaran struct msm_drm_private *priv; 87625fdd593SJeykumar Sankaran struct msm_drm_thread *event_thread; 87725fdd593SJeykumar Sankaran unsigned long flags; 87825fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 87925fdd593SJeykumar Sankaran 88025fdd593SJeykumar Sankaran if (!crtc || !crtc->dev || !crtc->dev->dev_private) { 88125fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 88225fdd593SJeykumar Sankaran return; 88325fdd593SJeykumar Sankaran } 88425fdd593SJeykumar Sankaran 88525fdd593SJeykumar Sankaran if (!crtc->state->enable) { 88625fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d -> enable %d, skip atomic_flush\n", 88725fdd593SJeykumar Sankaran crtc->base.id, crtc->state->enable); 88825fdd593SJeykumar Sankaran return; 88925fdd593SJeykumar Sankaran } 89025fdd593SJeykumar Sankaran 89125fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d\n", crtc->base.id); 89225fdd593SJeykumar Sankaran 89325fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 89425fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(crtc->state); 89525fdd593SJeykumar Sankaran dev = crtc->dev; 89625fdd593SJeykumar Sankaran priv = dev->dev_private; 89725fdd593SJeykumar Sankaran 89825fdd593SJeykumar Sankaran if (crtc->index >= ARRAY_SIZE(priv->event_thread)) { 89925fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc index[%d]\n", crtc->index); 90025fdd593SJeykumar Sankaran return; 90125fdd593SJeykumar Sankaran } 90225fdd593SJeykumar Sankaran 90325fdd593SJeykumar Sankaran event_thread = &priv->event_thread[crtc->index]; 90425fdd593SJeykumar Sankaran 90525fdd593SJeykumar Sankaran if (dpu_crtc->event) { 90625fdd593SJeykumar Sankaran DPU_DEBUG("already received dpu_crtc->event\n"); 90725fdd593SJeykumar Sankaran } else { 90825fdd593SJeykumar Sankaran spin_lock_irqsave(&dev->event_lock, flags); 90925fdd593SJeykumar Sankaran dpu_crtc->event = crtc->state->event; 91025fdd593SJeykumar Sankaran crtc->state->event = NULL; 91125fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dev->event_lock, flags); 91225fdd593SJeykumar Sankaran } 91325fdd593SJeykumar Sankaran 91425fdd593SJeykumar Sankaran /* 91525fdd593SJeykumar Sankaran * If no mixers has been allocated in dpu_crtc_atomic_check(), 91625fdd593SJeykumar Sankaran * it means we are trying to flush a CRTC whose state is disabled: 91725fdd593SJeykumar Sankaran * nothing else needs to be done. 91825fdd593SJeykumar Sankaran */ 91925fdd593SJeykumar Sankaran if (unlikely(!dpu_crtc->num_mixers)) 92025fdd593SJeykumar Sankaran return; 92125fdd593SJeykumar Sankaran 92225fdd593SJeykumar Sankaran /* 92325fdd593SJeykumar Sankaran * For planes without commit update, drm framework will not add 92425fdd593SJeykumar Sankaran * those planes to current state since hardware update is not 92525fdd593SJeykumar Sankaran * required. However, if those planes were power collapsed since 92625fdd593SJeykumar Sankaran * last commit cycle, driver has to restore the hardware state 92725fdd593SJeykumar Sankaran * of those planes explicitly here prior to plane flush. 92825fdd593SJeykumar Sankaran */ 92925fdd593SJeykumar Sankaran drm_atomic_crtc_for_each_plane(plane, crtc) 93025fdd593SJeykumar Sankaran dpu_plane_restore(plane); 93125fdd593SJeykumar Sankaran 93225fdd593SJeykumar Sankaran /* update performance setting before crtc kickoff */ 93325fdd593SJeykumar Sankaran dpu_core_perf_crtc_update(crtc, 1, false); 93425fdd593SJeykumar Sankaran 93525fdd593SJeykumar Sankaran /* 93625fdd593SJeykumar Sankaran * Final plane updates: Give each plane a chance to complete all 93725fdd593SJeykumar Sankaran * required writes/flushing before crtc's "flush 93825fdd593SJeykumar Sankaran * everything" call below. 93925fdd593SJeykumar Sankaran */ 94025fdd593SJeykumar Sankaran drm_atomic_crtc_for_each_plane(plane, crtc) { 94125fdd593SJeykumar Sankaran if (dpu_crtc->smmu_state.transition_error) 94225fdd593SJeykumar Sankaran dpu_plane_set_error(plane, true); 94325fdd593SJeykumar Sankaran dpu_plane_flush(plane); 94425fdd593SJeykumar Sankaran } 94525fdd593SJeykumar Sankaran 94625fdd593SJeykumar Sankaran /* Kickoff will be scheduled by outer layer */ 94725fdd593SJeykumar Sankaran } 94825fdd593SJeykumar Sankaran 94925fdd593SJeykumar Sankaran /** 95025fdd593SJeykumar Sankaran * dpu_crtc_destroy_state - state destroy hook 95125fdd593SJeykumar Sankaran * @crtc: drm CRTC 95225fdd593SJeykumar Sankaran * @state: CRTC state object to release 95325fdd593SJeykumar Sankaran */ 95425fdd593SJeykumar Sankaran static void dpu_crtc_destroy_state(struct drm_crtc *crtc, 95525fdd593SJeykumar Sankaran struct drm_crtc_state *state) 95625fdd593SJeykumar Sankaran { 95725fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 95825fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 95925fdd593SJeykumar Sankaran 96025fdd593SJeykumar Sankaran if (!crtc || !state) { 96125fdd593SJeykumar Sankaran DPU_ERROR("invalid argument(s)\n"); 96225fdd593SJeykumar Sankaran return; 96325fdd593SJeykumar Sankaran } 96425fdd593SJeykumar Sankaran 96525fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 96625fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(state); 96725fdd593SJeykumar Sankaran 96825fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d\n", crtc->base.id); 96925fdd593SJeykumar Sankaran 97025fdd593SJeykumar Sankaran _dpu_crtc_rp_destroy(&cstate->rp); 97125fdd593SJeykumar Sankaran 97225fdd593SJeykumar Sankaran __drm_atomic_helper_crtc_destroy_state(state); 97325fdd593SJeykumar Sankaran 97425fdd593SJeykumar Sankaran kfree(cstate); 97525fdd593SJeykumar Sankaran } 97625fdd593SJeykumar Sankaran 97725fdd593SJeykumar Sankaran static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc) 97825fdd593SJeykumar Sankaran { 97925fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 98025fdd593SJeykumar Sankaran int ret, rc = 0; 98125fdd593SJeykumar Sankaran 98225fdd593SJeykumar Sankaran if (!crtc) { 98325fdd593SJeykumar Sankaran DPU_ERROR("invalid argument\n"); 98425fdd593SJeykumar Sankaran return -EINVAL; 98525fdd593SJeykumar Sankaran } 98625fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 98725fdd593SJeykumar Sankaran 98825fdd593SJeykumar Sankaran if (!atomic_read(&dpu_crtc->frame_pending)) { 98925fdd593SJeykumar Sankaran DPU_DEBUG("no frames pending\n"); 99025fdd593SJeykumar Sankaran return 0; 99125fdd593SJeykumar Sankaran } 99225fdd593SJeykumar Sankaran 99325fdd593SJeykumar Sankaran DPU_ATRACE_BEGIN("frame done completion wait"); 99425fdd593SJeykumar Sankaran ret = wait_for_completion_timeout(&dpu_crtc->frame_done_comp, 99525fdd593SJeykumar Sankaran msecs_to_jiffies(DPU_FRAME_DONE_TIMEOUT)); 99625fdd593SJeykumar Sankaran if (!ret) { 99725fdd593SJeykumar Sankaran DRM_ERROR("frame done wait timed out, ret:%d\n", ret); 99825fdd593SJeykumar Sankaran rc = -ETIMEDOUT; 99925fdd593SJeykumar Sankaran } 100025fdd593SJeykumar Sankaran DPU_ATRACE_END("frame done completion wait"); 100125fdd593SJeykumar Sankaran 100225fdd593SJeykumar Sankaran return rc; 100325fdd593SJeykumar Sankaran } 100425fdd593SJeykumar Sankaran 100525fdd593SJeykumar Sankaran void dpu_crtc_commit_kickoff(struct drm_crtc *crtc) 100625fdd593SJeykumar Sankaran { 100725fdd593SJeykumar Sankaran struct drm_encoder *encoder; 100825fdd593SJeykumar Sankaran struct drm_device *dev; 100925fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 101025fdd593SJeykumar Sankaran struct msm_drm_private *priv; 101125fdd593SJeykumar Sankaran struct dpu_kms *dpu_kms; 101225fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 101325fdd593SJeykumar Sankaran int ret; 101425fdd593SJeykumar Sankaran 101525fdd593SJeykumar Sankaran if (!crtc) { 101625fdd593SJeykumar Sankaran DPU_ERROR("invalid argument\n"); 101725fdd593SJeykumar Sankaran return; 101825fdd593SJeykumar Sankaran } 101925fdd593SJeykumar Sankaran dev = crtc->dev; 102025fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 102125fdd593SJeykumar Sankaran dpu_kms = _dpu_crtc_get_kms(crtc); 102225fdd593SJeykumar Sankaran 102325fdd593SJeykumar Sankaran if (!dpu_kms || !dpu_kms->dev || !dpu_kms->dev->dev_private) { 102425fdd593SJeykumar Sankaran DPU_ERROR("invalid argument\n"); 102525fdd593SJeykumar Sankaran return; 102625fdd593SJeykumar Sankaran } 102725fdd593SJeykumar Sankaran 102825fdd593SJeykumar Sankaran priv = dpu_kms->dev->dev_private; 102925fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(crtc->state); 103025fdd593SJeykumar Sankaran 103125fdd593SJeykumar Sankaran /* 103225fdd593SJeykumar Sankaran * If no mixers has been allocated in dpu_crtc_atomic_check(), 103325fdd593SJeykumar Sankaran * it means we are trying to start a CRTC whose state is disabled: 103425fdd593SJeykumar Sankaran * nothing else needs to be done. 103525fdd593SJeykumar Sankaran */ 103625fdd593SJeykumar Sankaran if (unlikely(!dpu_crtc->num_mixers)) 103725fdd593SJeykumar Sankaran return; 103825fdd593SJeykumar Sankaran 103925fdd593SJeykumar Sankaran DPU_ATRACE_BEGIN("crtc_commit"); 104025fdd593SJeykumar Sankaran 104125fdd593SJeykumar Sankaran list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 104225fdd593SJeykumar Sankaran struct dpu_encoder_kickoff_params params = { 0 }; 104325fdd593SJeykumar Sankaran 104425fdd593SJeykumar Sankaran if (encoder->crtc != crtc) 104525fdd593SJeykumar Sankaran continue; 104625fdd593SJeykumar Sankaran 104725fdd593SJeykumar Sankaran /* 104825fdd593SJeykumar Sankaran * Encoder will flush/start now, unless it has a tx pending. 104925fdd593SJeykumar Sankaran * If so, it may delay and flush at an irq event (e.g. ppdone) 105025fdd593SJeykumar Sankaran */ 105125fdd593SJeykumar Sankaran dpu_encoder_prepare_for_kickoff(encoder, ¶ms); 105225fdd593SJeykumar Sankaran } 105325fdd593SJeykumar Sankaran 105425fdd593SJeykumar Sankaran /* wait for frame_event_done completion */ 105525fdd593SJeykumar Sankaran DPU_ATRACE_BEGIN("wait_for_frame_done_event"); 105625fdd593SJeykumar Sankaran ret = _dpu_crtc_wait_for_frame_done(crtc); 105725fdd593SJeykumar Sankaran DPU_ATRACE_END("wait_for_frame_done_event"); 105825fdd593SJeykumar Sankaran if (ret) { 105925fdd593SJeykumar Sankaran DPU_ERROR("crtc%d wait for frame done failed;frame_pending%d\n", 106025fdd593SJeykumar Sankaran crtc->base.id, 106125fdd593SJeykumar Sankaran atomic_read(&dpu_crtc->frame_pending)); 106225fdd593SJeykumar Sankaran goto end; 106325fdd593SJeykumar Sankaran } 106425fdd593SJeykumar Sankaran 106525fdd593SJeykumar Sankaran if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) { 106625fdd593SJeykumar Sankaran /* acquire bandwidth and other resources */ 106725fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d first commit\n", crtc->base.id); 106825fdd593SJeykumar Sankaran } else 106925fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d commit\n", crtc->base.id); 107025fdd593SJeykumar Sankaran 107125fdd593SJeykumar Sankaran dpu_crtc->play_count++; 107225fdd593SJeykumar Sankaran 107325fdd593SJeykumar Sankaran dpu_vbif_clear_errors(dpu_kms); 107425fdd593SJeykumar Sankaran 107525fdd593SJeykumar Sankaran list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 107625fdd593SJeykumar Sankaran if (encoder->crtc != crtc) 107725fdd593SJeykumar Sankaran continue; 107825fdd593SJeykumar Sankaran 107925fdd593SJeykumar Sankaran dpu_encoder_kickoff(encoder); 108025fdd593SJeykumar Sankaran } 108125fdd593SJeykumar Sankaran 108225fdd593SJeykumar Sankaran end: 108325fdd593SJeykumar Sankaran reinit_completion(&dpu_crtc->frame_done_comp); 108425fdd593SJeykumar Sankaran DPU_ATRACE_END("crtc_commit"); 108525fdd593SJeykumar Sankaran } 108625fdd593SJeykumar Sankaran 108725fdd593SJeykumar Sankaran /** 108825fdd593SJeykumar Sankaran * _dpu_crtc_vblank_enable_no_lock - update power resource and vblank request 108925fdd593SJeykumar Sankaran * @dpu_crtc: Pointer to dpu crtc structure 109025fdd593SJeykumar Sankaran * @enable: Whether to enable/disable vblanks 109125fdd593SJeykumar Sankaran * 109225fdd593SJeykumar Sankaran * @Return: error code 109325fdd593SJeykumar Sankaran */ 109425fdd593SJeykumar Sankaran static int _dpu_crtc_vblank_enable_no_lock( 109525fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc, bool enable) 109625fdd593SJeykumar Sankaran { 109725fdd593SJeykumar Sankaran struct drm_device *dev; 109825fdd593SJeykumar Sankaran struct drm_crtc *crtc; 109925fdd593SJeykumar Sankaran struct drm_encoder *enc; 110025fdd593SJeykumar Sankaran 110125fdd593SJeykumar Sankaran if (!dpu_crtc) { 110225fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 110325fdd593SJeykumar Sankaran return -EINVAL; 110425fdd593SJeykumar Sankaran } 110525fdd593SJeykumar Sankaran 110625fdd593SJeykumar Sankaran crtc = &dpu_crtc->base; 110725fdd593SJeykumar Sankaran dev = crtc->dev; 110825fdd593SJeykumar Sankaran 110925fdd593SJeykumar Sankaran if (enable) { 111025fdd593SJeykumar Sankaran int ret; 111125fdd593SJeykumar Sankaran 111225fdd593SJeykumar Sankaran /* drop lock since power crtc cb may try to re-acquire lock */ 111325fdd593SJeykumar Sankaran mutex_unlock(&dpu_crtc->crtc_lock); 111425fdd593SJeykumar Sankaran ret = _dpu_crtc_power_enable(dpu_crtc, true); 111525fdd593SJeykumar Sankaran mutex_lock(&dpu_crtc->crtc_lock); 111625fdd593SJeykumar Sankaran if (ret) 111725fdd593SJeykumar Sankaran return ret; 111825fdd593SJeykumar Sankaran 111925fdd593SJeykumar Sankaran list_for_each_entry(enc, &dev->mode_config.encoder_list, head) { 112025fdd593SJeykumar Sankaran if (enc->crtc != crtc) 112125fdd593SJeykumar Sankaran continue; 112225fdd593SJeykumar Sankaran 112325fdd593SJeykumar Sankaran trace_dpu_crtc_vblank_enable(DRMID(&dpu_crtc->base), 112425fdd593SJeykumar Sankaran DRMID(enc), enable, 112525fdd593SJeykumar Sankaran dpu_crtc); 112625fdd593SJeykumar Sankaran 112725fdd593SJeykumar Sankaran dpu_encoder_register_vblank_callback(enc, 112825fdd593SJeykumar Sankaran dpu_crtc_vblank_cb, (void *)crtc); 112925fdd593SJeykumar Sankaran } 113025fdd593SJeykumar Sankaran } else { 113125fdd593SJeykumar Sankaran list_for_each_entry(enc, &dev->mode_config.encoder_list, head) { 113225fdd593SJeykumar Sankaran if (enc->crtc != crtc) 113325fdd593SJeykumar Sankaran continue; 113425fdd593SJeykumar Sankaran 113525fdd593SJeykumar Sankaran trace_dpu_crtc_vblank_enable(DRMID(&dpu_crtc->base), 113625fdd593SJeykumar Sankaran DRMID(enc), enable, 113725fdd593SJeykumar Sankaran dpu_crtc); 113825fdd593SJeykumar Sankaran 113925fdd593SJeykumar Sankaran dpu_encoder_register_vblank_callback(enc, NULL, NULL); 114025fdd593SJeykumar Sankaran } 114125fdd593SJeykumar Sankaran 114225fdd593SJeykumar Sankaran /* drop lock since power crtc cb may try to re-acquire lock */ 114325fdd593SJeykumar Sankaran mutex_unlock(&dpu_crtc->crtc_lock); 114425fdd593SJeykumar Sankaran _dpu_crtc_power_enable(dpu_crtc, false); 114525fdd593SJeykumar Sankaran mutex_lock(&dpu_crtc->crtc_lock); 114625fdd593SJeykumar Sankaran } 114725fdd593SJeykumar Sankaran 114825fdd593SJeykumar Sankaran return 0; 114925fdd593SJeykumar Sankaran } 115025fdd593SJeykumar Sankaran 115125fdd593SJeykumar Sankaran /** 115225fdd593SJeykumar Sankaran * _dpu_crtc_set_suspend - notify crtc of suspend enable/disable 115325fdd593SJeykumar Sankaran * @crtc: Pointer to drm crtc object 115425fdd593SJeykumar Sankaran * @enable: true to enable suspend, false to indicate resume 115525fdd593SJeykumar Sankaran */ 115625fdd593SJeykumar Sankaran static void _dpu_crtc_set_suspend(struct drm_crtc *crtc, bool enable) 115725fdd593SJeykumar Sankaran { 115825fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 115925fdd593SJeykumar Sankaran struct msm_drm_private *priv; 116025fdd593SJeykumar Sankaran struct dpu_kms *dpu_kms; 116125fdd593SJeykumar Sankaran int ret = 0; 116225fdd593SJeykumar Sankaran 116325fdd593SJeykumar Sankaran if (!crtc || !crtc->dev || !crtc->dev->dev_private) { 116425fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 116525fdd593SJeykumar Sankaran return; 116625fdd593SJeykumar Sankaran } 116725fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 116825fdd593SJeykumar Sankaran priv = crtc->dev->dev_private; 116925fdd593SJeykumar Sankaran 117025fdd593SJeykumar Sankaran if (!priv->kms) { 117125fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc kms\n"); 117225fdd593SJeykumar Sankaran return; 117325fdd593SJeykumar Sankaran } 117425fdd593SJeykumar Sankaran dpu_kms = to_dpu_kms(priv->kms); 117525fdd593SJeykumar Sankaran 117625fdd593SJeykumar Sankaran DRM_DEBUG_KMS("crtc%d suspend = %d\n", crtc->base.id, enable); 117725fdd593SJeykumar Sankaran 117825fdd593SJeykumar Sankaran mutex_lock(&dpu_crtc->crtc_lock); 117925fdd593SJeykumar Sankaran 118025fdd593SJeykumar Sankaran /* 118125fdd593SJeykumar Sankaran * If the vblank is enabled, release a power reference on suspend 118225fdd593SJeykumar Sankaran * and take it back during resume (if it is still enabled). 118325fdd593SJeykumar Sankaran */ 118425fdd593SJeykumar Sankaran trace_dpu_crtc_set_suspend(DRMID(&dpu_crtc->base), enable, dpu_crtc); 118525fdd593SJeykumar Sankaran if (dpu_crtc->suspend == enable) 118625fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d suspend already set to %d, ignoring update\n", 118725fdd593SJeykumar Sankaran crtc->base.id, enable); 118825fdd593SJeykumar Sankaran else if (dpu_crtc->enabled && dpu_crtc->vblank_requested) { 118925fdd593SJeykumar Sankaran ret = _dpu_crtc_vblank_enable_no_lock(dpu_crtc, !enable); 119025fdd593SJeykumar Sankaran if (ret) 119125fdd593SJeykumar Sankaran DPU_ERROR("%s vblank enable failed: %d\n", 119225fdd593SJeykumar Sankaran dpu_crtc->name, ret); 119325fdd593SJeykumar Sankaran } 119425fdd593SJeykumar Sankaran 119525fdd593SJeykumar Sankaran dpu_crtc->suspend = enable; 119625fdd593SJeykumar Sankaran mutex_unlock(&dpu_crtc->crtc_lock); 119725fdd593SJeykumar Sankaran } 119825fdd593SJeykumar Sankaran 119925fdd593SJeykumar Sankaran /** 120025fdd593SJeykumar Sankaran * dpu_crtc_duplicate_state - state duplicate hook 120125fdd593SJeykumar Sankaran * @crtc: Pointer to drm crtc structure 120225fdd593SJeykumar Sankaran * @Returns: Pointer to new drm_crtc_state structure 120325fdd593SJeykumar Sankaran */ 120425fdd593SJeykumar Sankaran static struct drm_crtc_state *dpu_crtc_duplicate_state(struct drm_crtc *crtc) 120525fdd593SJeykumar Sankaran { 120625fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 120725fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate, *old_cstate; 120825fdd593SJeykumar Sankaran 120925fdd593SJeykumar Sankaran if (!crtc || !crtc->state) { 121025fdd593SJeykumar Sankaran DPU_ERROR("invalid argument(s)\n"); 121125fdd593SJeykumar Sankaran return NULL; 121225fdd593SJeykumar Sankaran } 121325fdd593SJeykumar Sankaran 121425fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 121525fdd593SJeykumar Sankaran old_cstate = to_dpu_crtc_state(crtc->state); 121625fdd593SJeykumar Sankaran cstate = kmemdup(old_cstate, sizeof(*old_cstate), GFP_KERNEL); 121725fdd593SJeykumar Sankaran if (!cstate) { 121825fdd593SJeykumar Sankaran DPU_ERROR("failed to allocate state\n"); 121925fdd593SJeykumar Sankaran return NULL; 122025fdd593SJeykumar Sankaran } 122125fdd593SJeykumar Sankaran 122225fdd593SJeykumar Sankaran /* duplicate base helper */ 122325fdd593SJeykumar Sankaran __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base); 122425fdd593SJeykumar Sankaran 122525fdd593SJeykumar Sankaran _dpu_crtc_rp_duplicate(&old_cstate->rp, &cstate->rp); 122625fdd593SJeykumar Sankaran 122725fdd593SJeykumar Sankaran return &cstate->base; 122825fdd593SJeykumar Sankaran } 122925fdd593SJeykumar Sankaran 123025fdd593SJeykumar Sankaran /** 123125fdd593SJeykumar Sankaran * dpu_crtc_reset - reset hook for CRTCs 123225fdd593SJeykumar Sankaran * Resets the atomic state for @crtc by freeing the state pointer (which might 123325fdd593SJeykumar Sankaran * be NULL, e.g. at driver load time) and allocating a new empty state object. 123425fdd593SJeykumar Sankaran * @crtc: Pointer to drm crtc structure 123525fdd593SJeykumar Sankaran */ 123625fdd593SJeykumar Sankaran static void dpu_crtc_reset(struct drm_crtc *crtc) 123725fdd593SJeykumar Sankaran { 123825fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 123925fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 124025fdd593SJeykumar Sankaran 124125fdd593SJeykumar Sankaran if (!crtc) { 124225fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 124325fdd593SJeykumar Sankaran return; 124425fdd593SJeykumar Sankaran } 124525fdd593SJeykumar Sankaran 124625fdd593SJeykumar Sankaran /* revert suspend actions, if necessary */ 124725fdd593SJeykumar Sankaran if (dpu_kms_is_suspend_state(crtc->dev)) 124825fdd593SJeykumar Sankaran _dpu_crtc_set_suspend(crtc, false); 124925fdd593SJeykumar Sankaran 125025fdd593SJeykumar Sankaran /* remove previous state, if present */ 125125fdd593SJeykumar Sankaran if (crtc->state) { 125225fdd593SJeykumar Sankaran dpu_crtc_destroy_state(crtc, crtc->state); 125325fdd593SJeykumar Sankaran crtc->state = 0; 125425fdd593SJeykumar Sankaran } 125525fdd593SJeykumar Sankaran 125625fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 125725fdd593SJeykumar Sankaran cstate = kzalloc(sizeof(*cstate), GFP_KERNEL); 125825fdd593SJeykumar Sankaran if (!cstate) { 125925fdd593SJeykumar Sankaran DPU_ERROR("failed to allocate state\n"); 126025fdd593SJeykumar Sankaran return; 126125fdd593SJeykumar Sankaran } 126225fdd593SJeykumar Sankaran 126325fdd593SJeykumar Sankaran _dpu_crtc_rp_reset(&cstate->rp, &dpu_crtc->rp_lock, 126425fdd593SJeykumar Sankaran &dpu_crtc->rp_head); 126525fdd593SJeykumar Sankaran 126625fdd593SJeykumar Sankaran cstate->base.crtc = crtc; 126725fdd593SJeykumar Sankaran crtc->state = &cstate->base; 126825fdd593SJeykumar Sankaran } 126925fdd593SJeykumar Sankaran 127025fdd593SJeykumar Sankaran static void dpu_crtc_handle_power_event(u32 event_type, void *arg) 127125fdd593SJeykumar Sankaran { 127225fdd593SJeykumar Sankaran struct drm_crtc *crtc = arg; 127325fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 127425fdd593SJeykumar Sankaran struct drm_encoder *encoder; 127525fdd593SJeykumar Sankaran struct dpu_crtc_mixer *m; 127625fdd593SJeykumar Sankaran u32 i, misr_status; 127725fdd593SJeykumar Sankaran 127825fdd593SJeykumar Sankaran if (!crtc) { 127925fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 128025fdd593SJeykumar Sankaran return; 128125fdd593SJeykumar Sankaran } 128225fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 128325fdd593SJeykumar Sankaran 128425fdd593SJeykumar Sankaran mutex_lock(&dpu_crtc->crtc_lock); 128525fdd593SJeykumar Sankaran 128625fdd593SJeykumar Sankaran trace_dpu_crtc_handle_power_event(DRMID(crtc), event_type); 128725fdd593SJeykumar Sankaran 128825fdd593SJeykumar Sankaran switch (event_type) { 128925fdd593SJeykumar Sankaran case DPU_POWER_EVENT_POST_ENABLE: 129025fdd593SJeykumar Sankaran /* restore encoder; crtc will be programmed during commit */ 129125fdd593SJeykumar Sankaran drm_for_each_encoder(encoder, crtc->dev) { 129225fdd593SJeykumar Sankaran if (encoder->crtc != crtc) 129325fdd593SJeykumar Sankaran continue; 129425fdd593SJeykumar Sankaran 129525fdd593SJeykumar Sankaran dpu_encoder_virt_restore(encoder); 129625fdd593SJeykumar Sankaran } 129725fdd593SJeykumar Sankaran 129825fdd593SJeykumar Sankaran for (i = 0; i < dpu_crtc->num_mixers; ++i) { 129925fdd593SJeykumar Sankaran m = &dpu_crtc->mixers[i]; 130025fdd593SJeykumar Sankaran if (!m->hw_lm || !m->hw_lm->ops.setup_misr || 130125fdd593SJeykumar Sankaran !dpu_crtc->misr_enable) 130225fdd593SJeykumar Sankaran continue; 130325fdd593SJeykumar Sankaran 130425fdd593SJeykumar Sankaran m->hw_lm->ops.setup_misr(m->hw_lm, true, 130525fdd593SJeykumar Sankaran dpu_crtc->misr_frame_count); 130625fdd593SJeykumar Sankaran } 130725fdd593SJeykumar Sankaran break; 130825fdd593SJeykumar Sankaran case DPU_POWER_EVENT_PRE_DISABLE: 130925fdd593SJeykumar Sankaran for (i = 0; i < dpu_crtc->num_mixers; ++i) { 131025fdd593SJeykumar Sankaran m = &dpu_crtc->mixers[i]; 131125fdd593SJeykumar Sankaran if (!m->hw_lm || !m->hw_lm->ops.collect_misr || 131225fdd593SJeykumar Sankaran !dpu_crtc->misr_enable) 131325fdd593SJeykumar Sankaran continue; 131425fdd593SJeykumar Sankaran 131525fdd593SJeykumar Sankaran misr_status = m->hw_lm->ops.collect_misr(m->hw_lm); 131625fdd593SJeykumar Sankaran dpu_crtc->misr_data[i] = misr_status ? misr_status : 131725fdd593SJeykumar Sankaran dpu_crtc->misr_data[i]; 131825fdd593SJeykumar Sankaran } 131925fdd593SJeykumar Sankaran break; 132025fdd593SJeykumar Sankaran case DPU_POWER_EVENT_POST_DISABLE: 132125fdd593SJeykumar Sankaran /** 132225fdd593SJeykumar Sankaran * Nothing to do. All the planes on the CRTC will be 132325fdd593SJeykumar Sankaran * programmed for every frame 132425fdd593SJeykumar Sankaran */ 132525fdd593SJeykumar Sankaran break; 132625fdd593SJeykumar Sankaran default: 132725fdd593SJeykumar Sankaran DPU_DEBUG("event:%d not handled\n", event_type); 132825fdd593SJeykumar Sankaran break; 132925fdd593SJeykumar Sankaran } 133025fdd593SJeykumar Sankaran 133125fdd593SJeykumar Sankaran mutex_unlock(&dpu_crtc->crtc_lock); 133225fdd593SJeykumar Sankaran } 133325fdd593SJeykumar Sankaran 133425fdd593SJeykumar Sankaran static void dpu_crtc_disable(struct drm_crtc *crtc) 133525fdd593SJeykumar Sankaran { 133625fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 133725fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 133825fdd593SJeykumar Sankaran struct drm_display_mode *mode; 133925fdd593SJeykumar Sankaran struct drm_encoder *encoder; 134025fdd593SJeykumar Sankaran struct msm_drm_private *priv; 134125fdd593SJeykumar Sankaran int ret; 13422f2eb723SRajesh Yadav unsigned long flags; 134325fdd593SJeykumar Sankaran 134425fdd593SJeykumar Sankaran if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) { 134525fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 134625fdd593SJeykumar Sankaran return; 134725fdd593SJeykumar Sankaran } 134825fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 134925fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(crtc->state); 135025fdd593SJeykumar Sankaran mode = &cstate->base.adjusted_mode; 135125fdd593SJeykumar Sankaran priv = crtc->dev->dev_private; 135225fdd593SJeykumar Sankaran 135325fdd593SJeykumar Sankaran DRM_DEBUG_KMS("crtc%d\n", crtc->base.id); 135425fdd593SJeykumar Sankaran 135525fdd593SJeykumar Sankaran if (dpu_kms_is_suspend_state(crtc->dev)) 135625fdd593SJeykumar Sankaran _dpu_crtc_set_suspend(crtc, true); 135725fdd593SJeykumar Sankaran 13582f2eb723SRajesh Yadav /* Disable/save vblank irq handling */ 13592f2eb723SRajesh Yadav drm_crtc_vblank_off(crtc); 13602f2eb723SRajesh Yadav 136125fdd593SJeykumar Sankaran mutex_lock(&dpu_crtc->crtc_lock); 136225fdd593SJeykumar Sankaran 136325fdd593SJeykumar Sankaran /* wait for frame_event_done completion */ 136425fdd593SJeykumar Sankaran if (_dpu_crtc_wait_for_frame_done(crtc)) 136525fdd593SJeykumar Sankaran DPU_ERROR("crtc%d wait for frame done failed;frame_pending%d\n", 136625fdd593SJeykumar Sankaran crtc->base.id, 136725fdd593SJeykumar Sankaran atomic_read(&dpu_crtc->frame_pending)); 136825fdd593SJeykumar Sankaran 136925fdd593SJeykumar Sankaran trace_dpu_crtc_disable(DRMID(crtc), false, dpu_crtc); 137025fdd593SJeykumar Sankaran if (dpu_crtc->enabled && !dpu_crtc->suspend && 137125fdd593SJeykumar Sankaran dpu_crtc->vblank_requested) { 137225fdd593SJeykumar Sankaran ret = _dpu_crtc_vblank_enable_no_lock(dpu_crtc, false); 137325fdd593SJeykumar Sankaran if (ret) 137425fdd593SJeykumar Sankaran DPU_ERROR("%s vblank enable failed: %d\n", 137525fdd593SJeykumar Sankaran dpu_crtc->name, ret); 137625fdd593SJeykumar Sankaran } 137725fdd593SJeykumar Sankaran dpu_crtc->enabled = false; 137825fdd593SJeykumar Sankaran 137925fdd593SJeykumar Sankaran if (atomic_read(&dpu_crtc->frame_pending)) { 138025fdd593SJeykumar Sankaran trace_dpu_crtc_disable_frame_pending(DRMID(crtc), 138125fdd593SJeykumar Sankaran atomic_read(&dpu_crtc->frame_pending)); 138225fdd593SJeykumar Sankaran dpu_core_perf_crtc_release_bw(crtc); 138325fdd593SJeykumar Sankaran atomic_set(&dpu_crtc->frame_pending, 0); 138425fdd593SJeykumar Sankaran } 138525fdd593SJeykumar Sankaran 138625fdd593SJeykumar Sankaran dpu_core_perf_crtc_update(crtc, 0, true); 138725fdd593SJeykumar Sankaran 138825fdd593SJeykumar Sankaran drm_for_each_encoder(encoder, crtc->dev) { 138925fdd593SJeykumar Sankaran if (encoder->crtc != crtc) 139025fdd593SJeykumar Sankaran continue; 139125fdd593SJeykumar Sankaran dpu_encoder_register_frame_event_callback(encoder, NULL, NULL); 139225fdd593SJeykumar Sankaran } 139325fdd593SJeykumar Sankaran 139425fdd593SJeykumar Sankaran if (dpu_crtc->power_event) 139525fdd593SJeykumar Sankaran dpu_power_handle_unregister_event(dpu_crtc->phandle, 139625fdd593SJeykumar Sankaran dpu_crtc->power_event); 139725fdd593SJeykumar Sankaran 139825fdd593SJeykumar Sankaran memset(dpu_crtc->mixers, 0, sizeof(dpu_crtc->mixers)); 139925fdd593SJeykumar Sankaran dpu_crtc->num_mixers = 0; 140025fdd593SJeykumar Sankaran dpu_crtc->mixers_swapped = false; 140125fdd593SJeykumar Sankaran 140225fdd593SJeykumar Sankaran /* disable clk & bw control until clk & bw properties are set */ 140325fdd593SJeykumar Sankaran cstate->bw_control = false; 140425fdd593SJeykumar Sankaran cstate->bw_split_vote = false; 140525fdd593SJeykumar Sankaran 140625fdd593SJeykumar Sankaran mutex_unlock(&dpu_crtc->crtc_lock); 14072f2eb723SRajesh Yadav 14082f2eb723SRajesh Yadav if (crtc->state->event && !crtc->state->active) { 14092f2eb723SRajesh Yadav spin_lock_irqsave(&crtc->dev->event_lock, flags); 14102f2eb723SRajesh Yadav drm_crtc_send_vblank_event(crtc, crtc->state->event); 14112f2eb723SRajesh Yadav crtc->state->event = NULL; 14122f2eb723SRajesh Yadav spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 14132f2eb723SRajesh Yadav } 141425fdd593SJeykumar Sankaran } 141525fdd593SJeykumar Sankaran 141625fdd593SJeykumar Sankaran static void dpu_crtc_enable(struct drm_crtc *crtc, 141725fdd593SJeykumar Sankaran struct drm_crtc_state *old_crtc_state) 141825fdd593SJeykumar Sankaran { 141925fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 142025fdd593SJeykumar Sankaran struct drm_encoder *encoder; 142125fdd593SJeykumar Sankaran struct msm_drm_private *priv; 142225fdd593SJeykumar Sankaran int ret; 142325fdd593SJeykumar Sankaran 142425fdd593SJeykumar Sankaran if (!crtc || !crtc->dev || !crtc->dev->dev_private) { 142525fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 142625fdd593SJeykumar Sankaran return; 142725fdd593SJeykumar Sankaran } 142825fdd593SJeykumar Sankaran priv = crtc->dev->dev_private; 142925fdd593SJeykumar Sankaran 143025fdd593SJeykumar Sankaran DRM_DEBUG_KMS("crtc%d\n", crtc->base.id); 143125fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 143225fdd593SJeykumar Sankaran 143325fdd593SJeykumar Sankaran drm_for_each_encoder(encoder, crtc->dev) { 143425fdd593SJeykumar Sankaran if (encoder->crtc != crtc) 143525fdd593SJeykumar Sankaran continue; 143625fdd593SJeykumar Sankaran dpu_encoder_register_frame_event_callback(encoder, 143725fdd593SJeykumar Sankaran dpu_crtc_frame_event_cb, (void *)crtc); 143825fdd593SJeykumar Sankaran } 143925fdd593SJeykumar Sankaran 144025fdd593SJeykumar Sankaran mutex_lock(&dpu_crtc->crtc_lock); 144125fdd593SJeykumar Sankaran trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc); 144225fdd593SJeykumar Sankaran if (!dpu_crtc->enabled && !dpu_crtc->suspend && 144325fdd593SJeykumar Sankaran dpu_crtc->vblank_requested) { 144425fdd593SJeykumar Sankaran ret = _dpu_crtc_vblank_enable_no_lock(dpu_crtc, true); 144525fdd593SJeykumar Sankaran if (ret) 144625fdd593SJeykumar Sankaran DPU_ERROR("%s vblank enable failed: %d\n", 144725fdd593SJeykumar Sankaran dpu_crtc->name, ret); 144825fdd593SJeykumar Sankaran } 144925fdd593SJeykumar Sankaran dpu_crtc->enabled = true; 145025fdd593SJeykumar Sankaran 145125fdd593SJeykumar Sankaran mutex_unlock(&dpu_crtc->crtc_lock); 145225fdd593SJeykumar Sankaran 14532f2eb723SRajesh Yadav /* Enable/restore vblank irq handling */ 14542f2eb723SRajesh Yadav drm_crtc_vblank_on(crtc); 14552f2eb723SRajesh Yadav 145625fdd593SJeykumar Sankaran dpu_crtc->power_event = dpu_power_handle_register_event( 145725fdd593SJeykumar Sankaran dpu_crtc->phandle, 145825fdd593SJeykumar Sankaran DPU_POWER_EVENT_POST_ENABLE | DPU_POWER_EVENT_POST_DISABLE | 145925fdd593SJeykumar Sankaran DPU_POWER_EVENT_PRE_DISABLE, 146025fdd593SJeykumar Sankaran dpu_crtc_handle_power_event, crtc, dpu_crtc->name); 146125fdd593SJeykumar Sankaran 146225fdd593SJeykumar Sankaran } 146325fdd593SJeykumar Sankaran 146425fdd593SJeykumar Sankaran struct plane_state { 146525fdd593SJeykumar Sankaran struct dpu_plane_state *dpu_pstate; 146625fdd593SJeykumar Sankaran const struct drm_plane_state *drm_pstate; 146725fdd593SJeykumar Sankaran int stage; 146825fdd593SJeykumar Sankaran u32 pipe_id; 146925fdd593SJeykumar Sankaran }; 147025fdd593SJeykumar Sankaran 147125fdd593SJeykumar Sankaran static int dpu_crtc_atomic_check(struct drm_crtc *crtc, 147225fdd593SJeykumar Sankaran struct drm_crtc_state *state) 147325fdd593SJeykumar Sankaran { 147425fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 147525fdd593SJeykumar Sankaran struct plane_state *pstates; 147625fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 147725fdd593SJeykumar Sankaran 147825fdd593SJeykumar Sankaran const struct drm_plane_state *pstate; 147925fdd593SJeykumar Sankaran struct drm_plane *plane; 148025fdd593SJeykumar Sankaran struct drm_display_mode *mode; 148125fdd593SJeykumar Sankaran 148225fdd593SJeykumar Sankaran int cnt = 0, rc = 0, mixer_width, i, z_pos; 148325fdd593SJeykumar Sankaran 148425fdd593SJeykumar Sankaran struct dpu_multirect_plane_states multirect_plane[DPU_STAGE_MAX * 2]; 148525fdd593SJeykumar Sankaran int multirect_count = 0; 148625fdd593SJeykumar Sankaran const struct drm_plane_state *pipe_staged[SSPP_MAX]; 148725fdd593SJeykumar Sankaran int left_zpos_cnt = 0, right_zpos_cnt = 0; 148825fdd593SJeykumar Sankaran struct drm_rect crtc_rect = { 0 }; 148925fdd593SJeykumar Sankaran 149025fdd593SJeykumar Sankaran if (!crtc) { 149125fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 149225fdd593SJeykumar Sankaran return -EINVAL; 149325fdd593SJeykumar Sankaran } 149425fdd593SJeykumar Sankaran 149525fdd593SJeykumar Sankaran pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL); 149625fdd593SJeykumar Sankaran 149725fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 149825fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(state); 149925fdd593SJeykumar Sankaran 150025fdd593SJeykumar Sankaran if (!state->enable || !state->active) { 150125fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n", 150225fdd593SJeykumar Sankaran crtc->base.id, state->enable, state->active); 150325fdd593SJeykumar Sankaran goto end; 150425fdd593SJeykumar Sankaran } 150525fdd593SJeykumar Sankaran 150625fdd593SJeykumar Sankaran mode = &state->adjusted_mode; 150725fdd593SJeykumar Sankaran DPU_DEBUG("%s: check", dpu_crtc->name); 150825fdd593SJeykumar Sankaran 150925fdd593SJeykumar Sankaran /* force a full mode set if active state changed */ 151025fdd593SJeykumar Sankaran if (state->active_changed) 151125fdd593SJeykumar Sankaran state->mode_changed = true; 151225fdd593SJeykumar Sankaran 151325fdd593SJeykumar Sankaran memset(pipe_staged, 0, sizeof(pipe_staged)); 151425fdd593SJeykumar Sankaran 151525fdd593SJeykumar Sankaran mixer_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode); 151625fdd593SJeykumar Sankaran 151725fdd593SJeykumar Sankaran _dpu_crtc_setup_lm_bounds(crtc, state); 151825fdd593SJeykumar Sankaran 151925fdd593SJeykumar Sankaran crtc_rect.x2 = mode->hdisplay; 152025fdd593SJeykumar Sankaran crtc_rect.y2 = mode->vdisplay; 152125fdd593SJeykumar Sankaran 152225fdd593SJeykumar Sankaran /* get plane state for all drm planes associated with crtc state */ 152325fdd593SJeykumar Sankaran drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { 152425fdd593SJeykumar Sankaran struct drm_rect dst, clip = crtc_rect; 152525fdd593SJeykumar Sankaran 152625fdd593SJeykumar Sankaran if (IS_ERR_OR_NULL(pstate)) { 152725fdd593SJeykumar Sankaran rc = PTR_ERR(pstate); 152825fdd593SJeykumar Sankaran DPU_ERROR("%s: failed to get plane%d state, %d\n", 152925fdd593SJeykumar Sankaran dpu_crtc->name, plane->base.id, rc); 153025fdd593SJeykumar Sankaran goto end; 153125fdd593SJeykumar Sankaran } 153225fdd593SJeykumar Sankaran if (cnt >= DPU_STAGE_MAX * 4) 153325fdd593SJeykumar Sankaran continue; 153425fdd593SJeykumar Sankaran 153525fdd593SJeykumar Sankaran pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate); 153625fdd593SJeykumar Sankaran pstates[cnt].drm_pstate = pstate; 153725fdd593SJeykumar Sankaran pstates[cnt].stage = pstate->normalized_zpos; 153825fdd593SJeykumar Sankaran pstates[cnt].pipe_id = dpu_plane_pipe(plane); 153925fdd593SJeykumar Sankaran 154025fdd593SJeykumar Sankaran if (pipe_staged[pstates[cnt].pipe_id]) { 154125fdd593SJeykumar Sankaran multirect_plane[multirect_count].r0 = 154225fdd593SJeykumar Sankaran pipe_staged[pstates[cnt].pipe_id]; 154325fdd593SJeykumar Sankaran multirect_plane[multirect_count].r1 = pstate; 154425fdd593SJeykumar Sankaran multirect_count++; 154525fdd593SJeykumar Sankaran 154625fdd593SJeykumar Sankaran pipe_staged[pstates[cnt].pipe_id] = NULL; 154725fdd593SJeykumar Sankaran } else { 154825fdd593SJeykumar Sankaran pipe_staged[pstates[cnt].pipe_id] = pstate; 154925fdd593SJeykumar Sankaran } 155025fdd593SJeykumar Sankaran 155125fdd593SJeykumar Sankaran cnt++; 155225fdd593SJeykumar Sankaran 155325fdd593SJeykumar Sankaran dst = drm_plane_state_dest(pstate); 155496fc56a7SSean Paul if (!drm_rect_intersect(&clip, &dst)) { 155525fdd593SJeykumar Sankaran DPU_ERROR("invalid vertical/horizontal destination\n"); 155625fdd593SJeykumar Sankaran DPU_ERROR("display: " DRM_RECT_FMT " plane: " 155725fdd593SJeykumar Sankaran DRM_RECT_FMT "\n", DRM_RECT_ARG(&crtc_rect), 155825fdd593SJeykumar Sankaran DRM_RECT_ARG(&dst)); 155925fdd593SJeykumar Sankaran rc = -E2BIG; 156025fdd593SJeykumar Sankaran goto end; 156125fdd593SJeykumar Sankaran } 156225fdd593SJeykumar Sankaran } 156325fdd593SJeykumar Sankaran 156425fdd593SJeykumar Sankaran for (i = 1; i < SSPP_MAX; i++) { 156525fdd593SJeykumar Sankaran if (pipe_staged[i]) { 156625fdd593SJeykumar Sankaran dpu_plane_clear_multirect(pipe_staged[i]); 156725fdd593SJeykumar Sankaran 156825fdd593SJeykumar Sankaran if (is_dpu_plane_virtual(pipe_staged[i]->plane)) { 156925fdd593SJeykumar Sankaran DPU_ERROR( 157025fdd593SJeykumar Sankaran "r1 only virt plane:%d not supported\n", 157125fdd593SJeykumar Sankaran pipe_staged[i]->plane->base.id); 157225fdd593SJeykumar Sankaran rc = -EINVAL; 157325fdd593SJeykumar Sankaran goto end; 157425fdd593SJeykumar Sankaran } 157525fdd593SJeykumar Sankaran } 157625fdd593SJeykumar Sankaran } 157725fdd593SJeykumar Sankaran 157825fdd593SJeykumar Sankaran z_pos = -1; 157925fdd593SJeykumar Sankaran for (i = 0; i < cnt; i++) { 158025fdd593SJeykumar Sankaran /* reset counts at every new blend stage */ 158125fdd593SJeykumar Sankaran if (pstates[i].stage != z_pos) { 158225fdd593SJeykumar Sankaran left_zpos_cnt = 0; 158325fdd593SJeykumar Sankaran right_zpos_cnt = 0; 158425fdd593SJeykumar Sankaran z_pos = pstates[i].stage; 158525fdd593SJeykumar Sankaran } 158625fdd593SJeykumar Sankaran 158725fdd593SJeykumar Sankaran /* verify z_pos setting before using it */ 158825fdd593SJeykumar Sankaran if (z_pos >= DPU_STAGE_MAX - DPU_STAGE_0) { 158925fdd593SJeykumar Sankaran DPU_ERROR("> %d plane stages assigned\n", 159025fdd593SJeykumar Sankaran DPU_STAGE_MAX - DPU_STAGE_0); 159125fdd593SJeykumar Sankaran rc = -EINVAL; 159225fdd593SJeykumar Sankaran goto end; 159325fdd593SJeykumar Sankaran } else if (pstates[i].drm_pstate->crtc_x < mixer_width) { 159425fdd593SJeykumar Sankaran if (left_zpos_cnt == 2) { 159525fdd593SJeykumar Sankaran DPU_ERROR("> 2 planes @ stage %d on left\n", 159625fdd593SJeykumar Sankaran z_pos); 159725fdd593SJeykumar Sankaran rc = -EINVAL; 159825fdd593SJeykumar Sankaran goto end; 159925fdd593SJeykumar Sankaran } 160025fdd593SJeykumar Sankaran left_zpos_cnt++; 160125fdd593SJeykumar Sankaran 160225fdd593SJeykumar Sankaran } else { 160325fdd593SJeykumar Sankaran if (right_zpos_cnt == 2) { 160425fdd593SJeykumar Sankaran DPU_ERROR("> 2 planes @ stage %d on right\n", 160525fdd593SJeykumar Sankaran z_pos); 160625fdd593SJeykumar Sankaran rc = -EINVAL; 160725fdd593SJeykumar Sankaran goto end; 160825fdd593SJeykumar Sankaran } 160925fdd593SJeykumar Sankaran right_zpos_cnt++; 161025fdd593SJeykumar Sankaran } 161125fdd593SJeykumar Sankaran 161225fdd593SJeykumar Sankaran pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0; 161325fdd593SJeykumar Sankaran DPU_DEBUG("%s: zpos %d", dpu_crtc->name, z_pos); 161425fdd593SJeykumar Sankaran } 161525fdd593SJeykumar Sankaran 161625fdd593SJeykumar Sankaran for (i = 0; i < multirect_count; i++) { 161725fdd593SJeykumar Sankaran if (dpu_plane_validate_multirect_v2(&multirect_plane[i])) { 161825fdd593SJeykumar Sankaran DPU_ERROR( 161925fdd593SJeykumar Sankaran "multirect validation failed for planes (%d - %d)\n", 162025fdd593SJeykumar Sankaran multirect_plane[i].r0->plane->base.id, 162125fdd593SJeykumar Sankaran multirect_plane[i].r1->plane->base.id); 162225fdd593SJeykumar Sankaran rc = -EINVAL; 162325fdd593SJeykumar Sankaran goto end; 162425fdd593SJeykumar Sankaran } 162525fdd593SJeykumar Sankaran } 162625fdd593SJeykumar Sankaran 162725fdd593SJeykumar Sankaran rc = dpu_core_perf_crtc_check(crtc, state); 162825fdd593SJeykumar Sankaran if (rc) { 162925fdd593SJeykumar Sankaran DPU_ERROR("crtc%d failed performance check %d\n", 163025fdd593SJeykumar Sankaran crtc->base.id, rc); 163125fdd593SJeykumar Sankaran goto end; 163225fdd593SJeykumar Sankaran } 163325fdd593SJeykumar Sankaran 163425fdd593SJeykumar Sankaran /* validate source split: 163525fdd593SJeykumar Sankaran * use pstates sorted by stage to check planes on same stage 163625fdd593SJeykumar Sankaran * we assume that all pipes are in source split so its valid to compare 163725fdd593SJeykumar Sankaran * without taking into account left/right mixer placement 163825fdd593SJeykumar Sankaran */ 163925fdd593SJeykumar Sankaran for (i = 1; i < cnt; i++) { 164025fdd593SJeykumar Sankaran struct plane_state *prv_pstate, *cur_pstate; 164125fdd593SJeykumar Sankaran struct drm_rect left_rect, right_rect; 164225fdd593SJeykumar Sankaran int32_t left_pid, right_pid; 164325fdd593SJeykumar Sankaran int32_t stage; 164425fdd593SJeykumar Sankaran 164525fdd593SJeykumar Sankaran prv_pstate = &pstates[i - 1]; 164625fdd593SJeykumar Sankaran cur_pstate = &pstates[i]; 164725fdd593SJeykumar Sankaran if (prv_pstate->stage != cur_pstate->stage) 164825fdd593SJeykumar Sankaran continue; 164925fdd593SJeykumar Sankaran 165025fdd593SJeykumar Sankaran stage = cur_pstate->stage; 165125fdd593SJeykumar Sankaran 165225fdd593SJeykumar Sankaran left_pid = prv_pstate->dpu_pstate->base.plane->base.id; 165325fdd593SJeykumar Sankaran left_rect = drm_plane_state_dest(prv_pstate->drm_pstate); 165425fdd593SJeykumar Sankaran 165525fdd593SJeykumar Sankaran right_pid = cur_pstate->dpu_pstate->base.plane->base.id; 165625fdd593SJeykumar Sankaran right_rect = drm_plane_state_dest(cur_pstate->drm_pstate); 165725fdd593SJeykumar Sankaran 165825fdd593SJeykumar Sankaran if (right_rect.x1 < left_rect.x1) { 165925fdd593SJeykumar Sankaran swap(left_pid, right_pid); 166025fdd593SJeykumar Sankaran swap(left_rect, right_rect); 166125fdd593SJeykumar Sankaran } 166225fdd593SJeykumar Sankaran 166325fdd593SJeykumar Sankaran /** 166425fdd593SJeykumar Sankaran * - planes are enumerated in pipe-priority order such that 166525fdd593SJeykumar Sankaran * planes with lower drm_id must be left-most in a shared 166625fdd593SJeykumar Sankaran * blend-stage when using source split. 166725fdd593SJeykumar Sankaran * - planes in source split must be contiguous in width 166825fdd593SJeykumar Sankaran * - planes in source split must have same dest yoff and height 166925fdd593SJeykumar Sankaran */ 167025fdd593SJeykumar Sankaran if (right_pid < left_pid) { 167125fdd593SJeykumar Sankaran DPU_ERROR( 167225fdd593SJeykumar Sankaran "invalid src split cfg. priority mismatch. stage: %d left: %d right: %d\n", 167325fdd593SJeykumar Sankaran stage, left_pid, right_pid); 167425fdd593SJeykumar Sankaran rc = -EINVAL; 167525fdd593SJeykumar Sankaran goto end; 167625fdd593SJeykumar Sankaran } else if (right_rect.x1 != drm_rect_width(&left_rect)) { 167725fdd593SJeykumar Sankaran DPU_ERROR("non-contiguous coordinates for src split. " 167825fdd593SJeykumar Sankaran "stage: %d left: " DRM_RECT_FMT " right: " 167925fdd593SJeykumar Sankaran DRM_RECT_FMT "\n", stage, 168025fdd593SJeykumar Sankaran DRM_RECT_ARG(&left_rect), 168125fdd593SJeykumar Sankaran DRM_RECT_ARG(&right_rect)); 168225fdd593SJeykumar Sankaran rc = -EINVAL; 168325fdd593SJeykumar Sankaran goto end; 168425fdd593SJeykumar Sankaran } else if (left_rect.y1 != right_rect.y1 || 168525fdd593SJeykumar Sankaran drm_rect_height(&left_rect) != drm_rect_height(&right_rect)) { 168625fdd593SJeykumar Sankaran DPU_ERROR("source split at stage: %d. invalid " 168725fdd593SJeykumar Sankaran "yoff/height: left: " DRM_RECT_FMT " right: " 168825fdd593SJeykumar Sankaran DRM_RECT_FMT "\n", stage, 168925fdd593SJeykumar Sankaran DRM_RECT_ARG(&left_rect), 169025fdd593SJeykumar Sankaran DRM_RECT_ARG(&right_rect)); 169125fdd593SJeykumar Sankaran rc = -EINVAL; 169225fdd593SJeykumar Sankaran goto end; 169325fdd593SJeykumar Sankaran } 169425fdd593SJeykumar Sankaran } 169525fdd593SJeykumar Sankaran 169625fdd593SJeykumar Sankaran end: 169725fdd593SJeykumar Sankaran _dpu_crtc_rp_free_unused(&cstate->rp); 169825fdd593SJeykumar Sankaran kfree(pstates); 169925fdd593SJeykumar Sankaran return rc; 170025fdd593SJeykumar Sankaran } 170125fdd593SJeykumar Sankaran 170225fdd593SJeykumar Sankaran int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) 170325fdd593SJeykumar Sankaran { 170425fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 170525fdd593SJeykumar Sankaran int ret; 170625fdd593SJeykumar Sankaran 170725fdd593SJeykumar Sankaran if (!crtc) { 170825fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 170925fdd593SJeykumar Sankaran return -EINVAL; 171025fdd593SJeykumar Sankaran } 171125fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 171225fdd593SJeykumar Sankaran 171325fdd593SJeykumar Sankaran mutex_lock(&dpu_crtc->crtc_lock); 171425fdd593SJeykumar Sankaran trace_dpu_crtc_vblank(DRMID(&dpu_crtc->base), en, dpu_crtc); 171525fdd593SJeykumar Sankaran if (dpu_crtc->enabled && !dpu_crtc->suspend) { 171625fdd593SJeykumar Sankaran ret = _dpu_crtc_vblank_enable_no_lock(dpu_crtc, en); 171725fdd593SJeykumar Sankaran if (ret) 171825fdd593SJeykumar Sankaran DPU_ERROR("%s vblank enable failed: %d\n", 171925fdd593SJeykumar Sankaran dpu_crtc->name, ret); 172025fdd593SJeykumar Sankaran } 172125fdd593SJeykumar Sankaran dpu_crtc->vblank_requested = en; 172225fdd593SJeykumar Sankaran mutex_unlock(&dpu_crtc->crtc_lock); 172325fdd593SJeykumar Sankaran 172425fdd593SJeykumar Sankaran return 0; 172525fdd593SJeykumar Sankaran } 172625fdd593SJeykumar Sankaran 172725fdd593SJeykumar Sankaran #ifdef CONFIG_DEBUG_FS 172825fdd593SJeykumar Sankaran static int _dpu_debugfs_status_show(struct seq_file *s, void *data) 172925fdd593SJeykumar Sankaran { 173025fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 173125fdd593SJeykumar Sankaran struct dpu_plane_state *pstate = NULL; 173225fdd593SJeykumar Sankaran struct dpu_crtc_mixer *m; 173325fdd593SJeykumar Sankaran 173425fdd593SJeykumar Sankaran struct drm_crtc *crtc; 173525fdd593SJeykumar Sankaran struct drm_plane *plane; 173625fdd593SJeykumar Sankaran struct drm_display_mode *mode; 173725fdd593SJeykumar Sankaran struct drm_framebuffer *fb; 173825fdd593SJeykumar Sankaran struct drm_plane_state *state; 173925fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 174025fdd593SJeykumar Sankaran 174125fdd593SJeykumar Sankaran int i, out_width; 174225fdd593SJeykumar Sankaran 174325fdd593SJeykumar Sankaran if (!s || !s->private) 174425fdd593SJeykumar Sankaran return -EINVAL; 174525fdd593SJeykumar Sankaran 174625fdd593SJeykumar Sankaran dpu_crtc = s->private; 174725fdd593SJeykumar Sankaran crtc = &dpu_crtc->base; 174825fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(crtc->state); 174925fdd593SJeykumar Sankaran 175025fdd593SJeykumar Sankaran mutex_lock(&dpu_crtc->crtc_lock); 175125fdd593SJeykumar Sankaran mode = &crtc->state->adjusted_mode; 175225fdd593SJeykumar Sankaran out_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode); 175325fdd593SJeykumar Sankaran 175425fdd593SJeykumar Sankaran seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id, 175525fdd593SJeykumar Sankaran mode->hdisplay, mode->vdisplay); 175625fdd593SJeykumar Sankaran 175725fdd593SJeykumar Sankaran seq_puts(s, "\n"); 175825fdd593SJeykumar Sankaran 175925fdd593SJeykumar Sankaran for (i = 0; i < dpu_crtc->num_mixers; ++i) { 176025fdd593SJeykumar Sankaran m = &dpu_crtc->mixers[i]; 176125fdd593SJeykumar Sankaran if (!m->hw_lm) 176225fdd593SJeykumar Sankaran seq_printf(s, "\tmixer[%d] has no lm\n", i); 176325fdd593SJeykumar Sankaran else if (!m->hw_ctl) 176425fdd593SJeykumar Sankaran seq_printf(s, "\tmixer[%d] has no ctl\n", i); 176525fdd593SJeykumar Sankaran else 176625fdd593SJeykumar Sankaran seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n", 176725fdd593SJeykumar Sankaran m->hw_lm->idx - LM_0, m->hw_ctl->idx - CTL_0, 176825fdd593SJeykumar Sankaran out_width, mode->vdisplay); 176925fdd593SJeykumar Sankaran } 177025fdd593SJeykumar Sankaran 177125fdd593SJeykumar Sankaran seq_puts(s, "\n"); 177225fdd593SJeykumar Sankaran 177325fdd593SJeykumar Sankaran drm_atomic_crtc_for_each_plane(plane, crtc) { 177425fdd593SJeykumar Sankaran pstate = to_dpu_plane_state(plane->state); 177525fdd593SJeykumar Sankaran state = plane->state; 177625fdd593SJeykumar Sankaran 177725fdd593SJeykumar Sankaran if (!pstate || !state) 177825fdd593SJeykumar Sankaran continue; 177925fdd593SJeykumar Sankaran 178025fdd593SJeykumar Sankaran seq_printf(s, "\tplane:%u stage:%d\n", plane->base.id, 178125fdd593SJeykumar Sankaran pstate->stage); 178225fdd593SJeykumar Sankaran 178325fdd593SJeykumar Sankaran if (plane->state->fb) { 178425fdd593SJeykumar Sankaran fb = plane->state->fb; 178525fdd593SJeykumar Sankaran 178625fdd593SJeykumar Sankaran seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u ", 178725fdd593SJeykumar Sankaran fb->base.id, (char *) &fb->format->format, 178825fdd593SJeykumar Sankaran fb->width, fb->height); 178925fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(fb->format->cpp); ++i) 179025fdd593SJeykumar Sankaran seq_printf(s, "cpp[%d]:%u ", 179125fdd593SJeykumar Sankaran i, fb->format->cpp[i]); 179225fdd593SJeykumar Sankaran seq_puts(s, "\n\t"); 179325fdd593SJeykumar Sankaran 179425fdd593SJeykumar Sankaran seq_printf(s, "modifier:%8llu ", fb->modifier); 179525fdd593SJeykumar Sankaran seq_puts(s, "\n"); 179625fdd593SJeykumar Sankaran 179725fdd593SJeykumar Sankaran seq_puts(s, "\t"); 179825fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) 179925fdd593SJeykumar Sankaran seq_printf(s, "pitches[%d]:%8u ", i, 180025fdd593SJeykumar Sankaran fb->pitches[i]); 180125fdd593SJeykumar Sankaran seq_puts(s, "\n"); 180225fdd593SJeykumar Sankaran 180325fdd593SJeykumar Sankaran seq_puts(s, "\t"); 180425fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) 180525fdd593SJeykumar Sankaran seq_printf(s, "offsets[%d]:%8u ", i, 180625fdd593SJeykumar Sankaran fb->offsets[i]); 180725fdd593SJeykumar Sankaran seq_puts(s, "\n"); 180825fdd593SJeykumar Sankaran } 180925fdd593SJeykumar Sankaran 181025fdd593SJeykumar Sankaran seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n", 181125fdd593SJeykumar Sankaran state->src_x, state->src_y, state->src_w, state->src_h); 181225fdd593SJeykumar Sankaran 181325fdd593SJeykumar Sankaran seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", 181425fdd593SJeykumar Sankaran state->crtc_x, state->crtc_y, state->crtc_w, 181525fdd593SJeykumar Sankaran state->crtc_h); 181625fdd593SJeykumar Sankaran seq_printf(s, "\tmultirect: mode: %d index: %d\n", 181725fdd593SJeykumar Sankaran pstate->multirect_mode, pstate->multirect_index); 181825fdd593SJeykumar Sankaran 181925fdd593SJeykumar Sankaran seq_puts(s, "\n"); 182025fdd593SJeykumar Sankaran } 182125fdd593SJeykumar Sankaran if (dpu_crtc->vblank_cb_count) { 182225fdd593SJeykumar Sankaran ktime_t diff = ktime_sub(ktime_get(), dpu_crtc->vblank_cb_time); 182325fdd593SJeykumar Sankaran s64 diff_ms = ktime_to_ms(diff); 182425fdd593SJeykumar Sankaran s64 fps = diff_ms ? div_s64( 182525fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_count * 1000, diff_ms) : 0; 182625fdd593SJeykumar Sankaran 182725fdd593SJeykumar Sankaran seq_printf(s, 182825fdd593SJeykumar Sankaran "vblank fps:%lld count:%u total:%llums total_framecount:%llu\n", 182925fdd593SJeykumar Sankaran fps, dpu_crtc->vblank_cb_count, 183025fdd593SJeykumar Sankaran ktime_to_ms(diff), dpu_crtc->play_count); 183125fdd593SJeykumar Sankaran 183225fdd593SJeykumar Sankaran /* reset time & count for next measurement */ 183325fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_count = 0; 183425fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_time = ktime_set(0, 0); 183525fdd593SJeykumar Sankaran } 183625fdd593SJeykumar Sankaran 183725fdd593SJeykumar Sankaran seq_printf(s, "vblank_enable:%d\n", dpu_crtc->vblank_requested); 183825fdd593SJeykumar Sankaran 183925fdd593SJeykumar Sankaran mutex_unlock(&dpu_crtc->crtc_lock); 184025fdd593SJeykumar Sankaran 184125fdd593SJeykumar Sankaran return 0; 184225fdd593SJeykumar Sankaran } 184325fdd593SJeykumar Sankaran 184425fdd593SJeykumar Sankaran static int _dpu_debugfs_status_open(struct inode *inode, struct file *file) 184525fdd593SJeykumar Sankaran { 184625fdd593SJeykumar Sankaran return single_open(file, _dpu_debugfs_status_show, inode->i_private); 184725fdd593SJeykumar Sankaran } 184825fdd593SJeykumar Sankaran 184925fdd593SJeykumar Sankaran static ssize_t _dpu_crtc_misr_setup(struct file *file, 185025fdd593SJeykumar Sankaran const char __user *user_buf, size_t count, loff_t *ppos) 185125fdd593SJeykumar Sankaran { 185225fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 185325fdd593SJeykumar Sankaran struct dpu_crtc_mixer *m; 185425fdd593SJeykumar Sankaran int i = 0, rc; 185525fdd593SJeykumar Sankaran char buf[MISR_BUFF_SIZE + 1]; 185625fdd593SJeykumar Sankaran u32 frame_count, enable; 185725fdd593SJeykumar Sankaran size_t buff_copy; 185825fdd593SJeykumar Sankaran 185925fdd593SJeykumar Sankaran if (!file || !file->private_data) 186025fdd593SJeykumar Sankaran return -EINVAL; 186125fdd593SJeykumar Sankaran 186225fdd593SJeykumar Sankaran dpu_crtc = file->private_data; 186325fdd593SJeykumar Sankaran buff_copy = min_t(size_t, count, MISR_BUFF_SIZE); 186425fdd593SJeykumar Sankaran if (copy_from_user(buf, user_buf, buff_copy)) { 186525fdd593SJeykumar Sankaran DPU_ERROR("buffer copy failed\n"); 186625fdd593SJeykumar Sankaran return -EINVAL; 186725fdd593SJeykumar Sankaran } 186825fdd593SJeykumar Sankaran 186925fdd593SJeykumar Sankaran buf[buff_copy] = 0; /* end of string */ 187025fdd593SJeykumar Sankaran 187125fdd593SJeykumar Sankaran if (sscanf(buf, "%u %u", &enable, &frame_count) != 2) 187225fdd593SJeykumar Sankaran return -EINVAL; 187325fdd593SJeykumar Sankaran 187425fdd593SJeykumar Sankaran rc = _dpu_crtc_power_enable(dpu_crtc, true); 187525fdd593SJeykumar Sankaran if (rc) 187625fdd593SJeykumar Sankaran return rc; 187725fdd593SJeykumar Sankaran 187825fdd593SJeykumar Sankaran mutex_lock(&dpu_crtc->crtc_lock); 187925fdd593SJeykumar Sankaran dpu_crtc->misr_enable = enable; 188025fdd593SJeykumar Sankaran dpu_crtc->misr_frame_count = frame_count; 188125fdd593SJeykumar Sankaran for (i = 0; i < dpu_crtc->num_mixers; ++i) { 188225fdd593SJeykumar Sankaran dpu_crtc->misr_data[i] = 0; 188325fdd593SJeykumar Sankaran m = &dpu_crtc->mixers[i]; 188425fdd593SJeykumar Sankaran if (!m->hw_lm || !m->hw_lm->ops.setup_misr) 188525fdd593SJeykumar Sankaran continue; 188625fdd593SJeykumar Sankaran 188725fdd593SJeykumar Sankaran m->hw_lm->ops.setup_misr(m->hw_lm, enable, frame_count); 188825fdd593SJeykumar Sankaran } 188925fdd593SJeykumar Sankaran mutex_unlock(&dpu_crtc->crtc_lock); 189025fdd593SJeykumar Sankaran _dpu_crtc_power_enable(dpu_crtc, false); 189125fdd593SJeykumar Sankaran 189225fdd593SJeykumar Sankaran return count; 189325fdd593SJeykumar Sankaran } 189425fdd593SJeykumar Sankaran 189525fdd593SJeykumar Sankaran static ssize_t _dpu_crtc_misr_read(struct file *file, 189625fdd593SJeykumar Sankaran char __user *user_buff, size_t count, loff_t *ppos) 189725fdd593SJeykumar Sankaran { 189825fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 189925fdd593SJeykumar Sankaran struct dpu_crtc_mixer *m; 190025fdd593SJeykumar Sankaran int i = 0, rc; 190125fdd593SJeykumar Sankaran u32 misr_status; 190225fdd593SJeykumar Sankaran ssize_t len = 0; 190325fdd593SJeykumar Sankaran char buf[MISR_BUFF_SIZE + 1] = {'\0'}; 190425fdd593SJeykumar Sankaran 190525fdd593SJeykumar Sankaran if (*ppos) 190625fdd593SJeykumar Sankaran return 0; 190725fdd593SJeykumar Sankaran 190825fdd593SJeykumar Sankaran if (!file || !file->private_data) 190925fdd593SJeykumar Sankaran return -EINVAL; 191025fdd593SJeykumar Sankaran 191125fdd593SJeykumar Sankaran dpu_crtc = file->private_data; 191225fdd593SJeykumar Sankaran rc = _dpu_crtc_power_enable(dpu_crtc, true); 191325fdd593SJeykumar Sankaran if (rc) 191425fdd593SJeykumar Sankaran return rc; 191525fdd593SJeykumar Sankaran 191625fdd593SJeykumar Sankaran mutex_lock(&dpu_crtc->crtc_lock); 191725fdd593SJeykumar Sankaran if (!dpu_crtc->misr_enable) { 191825fdd593SJeykumar Sankaran len += snprintf(buf + len, MISR_BUFF_SIZE - len, 191925fdd593SJeykumar Sankaran "disabled\n"); 192025fdd593SJeykumar Sankaran goto buff_check; 192125fdd593SJeykumar Sankaran } 192225fdd593SJeykumar Sankaran 192325fdd593SJeykumar Sankaran for (i = 0; i < dpu_crtc->num_mixers; ++i) { 192425fdd593SJeykumar Sankaran m = &dpu_crtc->mixers[i]; 192525fdd593SJeykumar Sankaran if (!m->hw_lm || !m->hw_lm->ops.collect_misr) 192625fdd593SJeykumar Sankaran continue; 192725fdd593SJeykumar Sankaran 192825fdd593SJeykumar Sankaran misr_status = m->hw_lm->ops.collect_misr(m->hw_lm); 192925fdd593SJeykumar Sankaran dpu_crtc->misr_data[i] = misr_status ? misr_status : 193025fdd593SJeykumar Sankaran dpu_crtc->misr_data[i]; 193125fdd593SJeykumar Sankaran len += snprintf(buf + len, MISR_BUFF_SIZE - len, "lm idx:%d\n", 193225fdd593SJeykumar Sankaran m->hw_lm->idx - LM_0); 193325fdd593SJeykumar Sankaran len += snprintf(buf + len, MISR_BUFF_SIZE - len, "0x%x\n", 193425fdd593SJeykumar Sankaran dpu_crtc->misr_data[i]); 193525fdd593SJeykumar Sankaran } 193625fdd593SJeykumar Sankaran 193725fdd593SJeykumar Sankaran buff_check: 193825fdd593SJeykumar Sankaran if (count <= len) { 193925fdd593SJeykumar Sankaran len = 0; 194025fdd593SJeykumar Sankaran goto end; 194125fdd593SJeykumar Sankaran } 194225fdd593SJeykumar Sankaran 194325fdd593SJeykumar Sankaran if (copy_to_user(user_buff, buf, len)) { 194425fdd593SJeykumar Sankaran len = -EFAULT; 194525fdd593SJeykumar Sankaran goto end; 194625fdd593SJeykumar Sankaran } 194725fdd593SJeykumar Sankaran 194825fdd593SJeykumar Sankaran *ppos += len; /* increase offset */ 194925fdd593SJeykumar Sankaran 195025fdd593SJeykumar Sankaran end: 195125fdd593SJeykumar Sankaran mutex_unlock(&dpu_crtc->crtc_lock); 195225fdd593SJeykumar Sankaran _dpu_crtc_power_enable(dpu_crtc, false); 195325fdd593SJeykumar Sankaran return len; 195425fdd593SJeykumar Sankaran } 195525fdd593SJeykumar Sankaran 195625fdd593SJeykumar Sankaran #define DEFINE_DPU_DEBUGFS_SEQ_FOPS(__prefix) \ 195725fdd593SJeykumar Sankaran static int __prefix ## _open(struct inode *inode, struct file *file) \ 195825fdd593SJeykumar Sankaran { \ 195925fdd593SJeykumar Sankaran return single_open(file, __prefix ## _show, inode->i_private); \ 196025fdd593SJeykumar Sankaran } \ 196125fdd593SJeykumar Sankaran static const struct file_operations __prefix ## _fops = { \ 196225fdd593SJeykumar Sankaran .owner = THIS_MODULE, \ 196325fdd593SJeykumar Sankaran .open = __prefix ## _open, \ 196425fdd593SJeykumar Sankaran .release = single_release, \ 196525fdd593SJeykumar Sankaran .read = seq_read, \ 196625fdd593SJeykumar Sankaran .llseek = seq_lseek, \ 196725fdd593SJeykumar Sankaran } 196825fdd593SJeykumar Sankaran 196925fdd593SJeykumar Sankaran static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v) 197025fdd593SJeykumar Sankaran { 197125fdd593SJeykumar Sankaran struct drm_crtc *crtc = (struct drm_crtc *) s->private; 197225fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 197325fdd593SJeykumar Sankaran struct dpu_crtc_res *res; 197425fdd593SJeykumar Sankaran struct dpu_crtc_respool *rp; 197525fdd593SJeykumar Sankaran int i; 197625fdd593SJeykumar Sankaran 197725fdd593SJeykumar Sankaran seq_printf(s, "client type: %d\n", dpu_crtc_get_client_type(crtc)); 197825fdd593SJeykumar Sankaran seq_printf(s, "intf_mode: %d\n", dpu_crtc_get_intf_mode(crtc)); 197925fdd593SJeykumar Sankaran seq_printf(s, "core_clk_rate: %llu\n", 198025fdd593SJeykumar Sankaran dpu_crtc->cur_perf.core_clk_rate); 198125fdd593SJeykumar Sankaran for (i = DPU_POWER_HANDLE_DBUS_ID_MNOC; 198225fdd593SJeykumar Sankaran i < DPU_POWER_HANDLE_DBUS_ID_MAX; i++) { 198325fdd593SJeykumar Sankaran seq_printf(s, "bw_ctl[%s]: %llu\n", 198425fdd593SJeykumar Sankaran dpu_power_handle_get_dbus_name(i), 198525fdd593SJeykumar Sankaran dpu_crtc->cur_perf.bw_ctl[i]); 198625fdd593SJeykumar Sankaran seq_printf(s, "max_per_pipe_ib[%s]: %llu\n", 198725fdd593SJeykumar Sankaran dpu_power_handle_get_dbus_name(i), 198825fdd593SJeykumar Sankaran dpu_crtc->cur_perf.max_per_pipe_ib[i]); 198925fdd593SJeykumar Sankaran } 199025fdd593SJeykumar Sankaran 199125fdd593SJeykumar Sankaran mutex_lock(&dpu_crtc->rp_lock); 199225fdd593SJeykumar Sankaran list_for_each_entry(rp, &dpu_crtc->rp_head, rp_list) { 199325fdd593SJeykumar Sankaran seq_printf(s, "rp.%d: ", rp->sequence_id); 199425fdd593SJeykumar Sankaran list_for_each_entry(res, &rp->res_list, list) 199525fdd593SJeykumar Sankaran seq_printf(s, "0x%x/0x%llx/%pK/%d ", 199625fdd593SJeykumar Sankaran res->type, res->tag, res->val, 199725fdd593SJeykumar Sankaran atomic_read(&res->refcount)); 199825fdd593SJeykumar Sankaran seq_puts(s, "\n"); 199925fdd593SJeykumar Sankaran } 200025fdd593SJeykumar Sankaran mutex_unlock(&dpu_crtc->rp_lock); 200125fdd593SJeykumar Sankaran 200225fdd593SJeykumar Sankaran return 0; 200325fdd593SJeykumar Sankaran } 200425fdd593SJeykumar Sankaran DEFINE_DPU_DEBUGFS_SEQ_FOPS(dpu_crtc_debugfs_state); 200525fdd593SJeykumar Sankaran 200625fdd593SJeykumar Sankaran static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc) 200725fdd593SJeykumar Sankaran { 200825fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 200925fdd593SJeykumar Sankaran struct dpu_kms *dpu_kms; 201025fdd593SJeykumar Sankaran 201125fdd593SJeykumar Sankaran static const struct file_operations debugfs_status_fops = { 201225fdd593SJeykumar Sankaran .open = _dpu_debugfs_status_open, 201325fdd593SJeykumar Sankaran .read = seq_read, 201425fdd593SJeykumar Sankaran .llseek = seq_lseek, 201525fdd593SJeykumar Sankaran .release = single_release, 201625fdd593SJeykumar Sankaran }; 201725fdd593SJeykumar Sankaran static const struct file_operations debugfs_misr_fops = { 201825fdd593SJeykumar Sankaran .open = simple_open, 201925fdd593SJeykumar Sankaran .read = _dpu_crtc_misr_read, 202025fdd593SJeykumar Sankaran .write = _dpu_crtc_misr_setup, 202125fdd593SJeykumar Sankaran }; 202225fdd593SJeykumar Sankaran 202325fdd593SJeykumar Sankaran if (!crtc) 202425fdd593SJeykumar Sankaran return -EINVAL; 202525fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 202625fdd593SJeykumar Sankaran 202725fdd593SJeykumar Sankaran dpu_kms = _dpu_crtc_get_kms(crtc); 202825fdd593SJeykumar Sankaran if (!dpu_kms) 202925fdd593SJeykumar Sankaran return -EINVAL; 203025fdd593SJeykumar Sankaran 203125fdd593SJeykumar Sankaran dpu_crtc->debugfs_root = debugfs_create_dir(dpu_crtc->name, 203225fdd593SJeykumar Sankaran crtc->dev->primary->debugfs_root); 203325fdd593SJeykumar Sankaran if (!dpu_crtc->debugfs_root) 203425fdd593SJeykumar Sankaran return -ENOMEM; 203525fdd593SJeykumar Sankaran 203625fdd593SJeykumar Sankaran /* don't error check these */ 203725fdd593SJeykumar Sankaran debugfs_create_file("status", 0400, 203825fdd593SJeykumar Sankaran dpu_crtc->debugfs_root, 203925fdd593SJeykumar Sankaran dpu_crtc, &debugfs_status_fops); 204025fdd593SJeykumar Sankaran debugfs_create_file("state", 0600, 204125fdd593SJeykumar Sankaran dpu_crtc->debugfs_root, 204225fdd593SJeykumar Sankaran &dpu_crtc->base, 204325fdd593SJeykumar Sankaran &dpu_crtc_debugfs_state_fops); 204425fdd593SJeykumar Sankaran debugfs_create_file("misr_data", 0600, dpu_crtc->debugfs_root, 204525fdd593SJeykumar Sankaran dpu_crtc, &debugfs_misr_fops); 204625fdd593SJeykumar Sankaran 204725fdd593SJeykumar Sankaran return 0; 204825fdd593SJeykumar Sankaran } 204925fdd593SJeykumar Sankaran 205025fdd593SJeykumar Sankaran static void _dpu_crtc_destroy_debugfs(struct drm_crtc *crtc) 205125fdd593SJeykumar Sankaran { 205225fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 205325fdd593SJeykumar Sankaran 205425fdd593SJeykumar Sankaran if (!crtc) 205525fdd593SJeykumar Sankaran return; 205625fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 205725fdd593SJeykumar Sankaran debugfs_remove_recursive(dpu_crtc->debugfs_root); 205825fdd593SJeykumar Sankaran } 205925fdd593SJeykumar Sankaran #else 206025fdd593SJeykumar Sankaran static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc) 206125fdd593SJeykumar Sankaran { 206225fdd593SJeykumar Sankaran return 0; 206325fdd593SJeykumar Sankaran } 206425fdd593SJeykumar Sankaran 206525fdd593SJeykumar Sankaran static void _dpu_crtc_destroy_debugfs(struct drm_crtc *crtc) 206625fdd593SJeykumar Sankaran { 206725fdd593SJeykumar Sankaran } 206825fdd593SJeykumar Sankaran #endif /* CONFIG_DEBUG_FS */ 206925fdd593SJeykumar Sankaran 207025fdd593SJeykumar Sankaran static int dpu_crtc_late_register(struct drm_crtc *crtc) 207125fdd593SJeykumar Sankaran { 207225fdd593SJeykumar Sankaran return _dpu_crtc_init_debugfs(crtc); 207325fdd593SJeykumar Sankaran } 207425fdd593SJeykumar Sankaran 207525fdd593SJeykumar Sankaran static void dpu_crtc_early_unregister(struct drm_crtc *crtc) 207625fdd593SJeykumar Sankaran { 207725fdd593SJeykumar Sankaran _dpu_crtc_destroy_debugfs(crtc); 207825fdd593SJeykumar Sankaran } 207925fdd593SJeykumar Sankaran 208025fdd593SJeykumar Sankaran static const struct drm_crtc_funcs dpu_crtc_funcs = { 208125fdd593SJeykumar Sankaran .set_config = drm_atomic_helper_set_config, 208225fdd593SJeykumar Sankaran .destroy = dpu_crtc_destroy, 208325fdd593SJeykumar Sankaran .page_flip = drm_atomic_helper_page_flip, 208425fdd593SJeykumar Sankaran .reset = dpu_crtc_reset, 208525fdd593SJeykumar Sankaran .atomic_duplicate_state = dpu_crtc_duplicate_state, 208625fdd593SJeykumar Sankaran .atomic_destroy_state = dpu_crtc_destroy_state, 208725fdd593SJeykumar Sankaran .late_register = dpu_crtc_late_register, 208825fdd593SJeykumar Sankaran .early_unregister = dpu_crtc_early_unregister, 208925fdd593SJeykumar Sankaran }; 209025fdd593SJeykumar Sankaran 209125fdd593SJeykumar Sankaran static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = { 209225fdd593SJeykumar Sankaran .disable = dpu_crtc_disable, 209325fdd593SJeykumar Sankaran .atomic_enable = dpu_crtc_enable, 209425fdd593SJeykumar Sankaran .atomic_check = dpu_crtc_atomic_check, 209525fdd593SJeykumar Sankaran .atomic_begin = dpu_crtc_atomic_begin, 209625fdd593SJeykumar Sankaran .atomic_flush = dpu_crtc_atomic_flush, 209725fdd593SJeykumar Sankaran }; 209825fdd593SJeykumar Sankaran 209925fdd593SJeykumar Sankaran /* initialize crtc */ 210007ca1fc0SSravanthi Kollukuduru struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, 210107ca1fc0SSravanthi Kollukuduru struct drm_plane *cursor) 210225fdd593SJeykumar Sankaran { 210325fdd593SJeykumar Sankaran struct drm_crtc *crtc = NULL; 210425fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = NULL; 210525fdd593SJeykumar Sankaran struct msm_drm_private *priv = NULL; 210625fdd593SJeykumar Sankaran struct dpu_kms *kms = NULL; 2107c17aeda0SJordan Crouse int i; 210825fdd593SJeykumar Sankaran 210925fdd593SJeykumar Sankaran priv = dev->dev_private; 211025fdd593SJeykumar Sankaran kms = to_dpu_kms(priv->kms); 211125fdd593SJeykumar Sankaran 211225fdd593SJeykumar Sankaran dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL); 211325fdd593SJeykumar Sankaran if (!dpu_crtc) 211425fdd593SJeykumar Sankaran return ERR_PTR(-ENOMEM); 211525fdd593SJeykumar Sankaran 211625fdd593SJeykumar Sankaran crtc = &dpu_crtc->base; 211725fdd593SJeykumar Sankaran crtc->dev = dev; 211825fdd593SJeykumar Sankaran 211925fdd593SJeykumar Sankaran mutex_init(&dpu_crtc->crtc_lock); 212025fdd593SJeykumar Sankaran spin_lock_init(&dpu_crtc->spin_lock); 212125fdd593SJeykumar Sankaran atomic_set(&dpu_crtc->frame_pending, 0); 212225fdd593SJeykumar Sankaran 212325fdd593SJeykumar Sankaran mutex_init(&dpu_crtc->rp_lock); 212425fdd593SJeykumar Sankaran INIT_LIST_HEAD(&dpu_crtc->rp_head); 212525fdd593SJeykumar Sankaran 212625fdd593SJeykumar Sankaran init_completion(&dpu_crtc->frame_done_comp); 212725fdd593SJeykumar Sankaran 212825fdd593SJeykumar Sankaran INIT_LIST_HEAD(&dpu_crtc->frame_event_list); 212925fdd593SJeykumar Sankaran 213025fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(dpu_crtc->frame_events); i++) { 213125fdd593SJeykumar Sankaran INIT_LIST_HEAD(&dpu_crtc->frame_events[i].list); 213225fdd593SJeykumar Sankaran list_add(&dpu_crtc->frame_events[i].list, 213325fdd593SJeykumar Sankaran &dpu_crtc->frame_event_list); 213425fdd593SJeykumar Sankaran kthread_init_work(&dpu_crtc->frame_events[i].work, 213525fdd593SJeykumar Sankaran dpu_crtc_frame_event_work); 213625fdd593SJeykumar Sankaran } 213725fdd593SJeykumar Sankaran 213807ca1fc0SSravanthi Kollukuduru drm_crtc_init_with_planes(dev, crtc, plane, cursor, &dpu_crtc_funcs, 213925fdd593SJeykumar Sankaran NULL); 214025fdd593SJeykumar Sankaran 214125fdd593SJeykumar Sankaran drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs); 214225fdd593SJeykumar Sankaran plane->crtc = crtc; 214325fdd593SJeykumar Sankaran 214425fdd593SJeykumar Sankaran /* save user friendly CRTC name for later */ 214525fdd593SJeykumar Sankaran snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id); 214625fdd593SJeykumar Sankaran 214725fdd593SJeykumar Sankaran /* initialize event handling */ 2148c17aeda0SJordan Crouse spin_lock_init(&dpu_crtc->event_lock); 214925fdd593SJeykumar Sankaran 215025fdd593SJeykumar Sankaran dpu_crtc->phandle = &kms->phandle; 215125fdd593SJeykumar Sankaran 215225fdd593SJeykumar Sankaran DPU_DEBUG("%s: successfully initialized crtc\n", dpu_crtc->name); 215325fdd593SJeykumar Sankaran return crtc; 215425fdd593SJeykumar Sankaran } 2155