125fdd593SJeykumar Sankaran /* 225fdd593SJeykumar Sankaran * Copyright (c) 2014-2018 The Linux Foundation. All rights reserved. 325fdd593SJeykumar Sankaran * Copyright (C) 2013 Red Hat 425fdd593SJeykumar Sankaran * Author: Rob Clark <robdclark@gmail.com> 525fdd593SJeykumar Sankaran * 625fdd593SJeykumar Sankaran * This program is free software; you can redistribute it and/or modify it 725fdd593SJeykumar Sankaran * under the terms of the GNU General Public License version 2 as published by 825fdd593SJeykumar Sankaran * the Free Software Foundation. 925fdd593SJeykumar Sankaran * 1025fdd593SJeykumar Sankaran * This program is distributed in the hope that it will be useful, but WITHOUT 1125fdd593SJeykumar Sankaran * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1225fdd593SJeykumar Sankaran * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1325fdd593SJeykumar Sankaran * more details. 1425fdd593SJeykumar Sankaran * 1525fdd593SJeykumar Sankaran * You should have received a copy of the GNU General Public License along with 1625fdd593SJeykumar Sankaran * this program. If not, see <http://www.gnu.org/licenses/>. 1725fdd593SJeykumar Sankaran */ 1825fdd593SJeykumar Sankaran 1925fdd593SJeykumar Sankaran #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ 2025fdd593SJeykumar Sankaran #include <linux/sort.h> 2125fdd593SJeykumar Sankaran #include <linux/debugfs.h> 2225fdd593SJeykumar Sankaran #include <linux/ktime.h> 2325fdd593SJeykumar Sankaran #include <drm/drm_mode.h> 2425fdd593SJeykumar Sankaran #include <drm/drm_crtc.h> 2525fdd593SJeykumar Sankaran #include <drm/drm_crtc_helper.h> 2625fdd593SJeykumar Sankaran #include <drm/drm_flip_work.h> 2725fdd593SJeykumar Sankaran #include <drm/drm_rect.h> 2825fdd593SJeykumar Sankaran 2925fdd593SJeykumar Sankaran #include "dpu_kms.h" 3025fdd593SJeykumar Sankaran #include "dpu_hw_lm.h" 3125fdd593SJeykumar Sankaran #include "dpu_hw_ctl.h" 3225fdd593SJeykumar Sankaran #include "dpu_crtc.h" 3325fdd593SJeykumar Sankaran #include "dpu_plane.h" 3425fdd593SJeykumar Sankaran #include "dpu_encoder.h" 3525fdd593SJeykumar Sankaran #include "dpu_vbif.h" 3625fdd593SJeykumar Sankaran #include "dpu_core_perf.h" 3725fdd593SJeykumar Sankaran #include "dpu_trace.h" 3825fdd593SJeykumar Sankaran 3925fdd593SJeykumar Sankaran #define DPU_DRM_BLEND_OP_NOT_DEFINED 0 4025fdd593SJeykumar Sankaran #define DPU_DRM_BLEND_OP_OPAQUE 1 4125fdd593SJeykumar Sankaran #define DPU_DRM_BLEND_OP_PREMULTIPLIED 2 4225fdd593SJeykumar Sankaran #define DPU_DRM_BLEND_OP_COVERAGE 3 4325fdd593SJeykumar Sankaran #define DPU_DRM_BLEND_OP_MAX 4 4425fdd593SJeykumar Sankaran 4525fdd593SJeykumar Sankaran /* layer mixer index on dpu_crtc */ 4625fdd593SJeykumar Sankaran #define LEFT_MIXER 0 4725fdd593SJeykumar Sankaran #define RIGHT_MIXER 1 4825fdd593SJeykumar Sankaran 4958fba464SSean Paul static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc) 5025fdd593SJeykumar Sankaran { 5104b96b63SBruce Wang struct msm_drm_private *priv = crtc->dev->dev_private; 5225fdd593SJeykumar Sankaran 5325fdd593SJeykumar Sankaran return to_dpu_kms(priv->kms); 5425fdd593SJeykumar Sankaran } 5525fdd593SJeykumar Sankaran 5625fdd593SJeykumar Sankaran static void dpu_crtc_destroy(struct drm_crtc *crtc) 5725fdd593SJeykumar Sankaran { 5825fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 5925fdd593SJeykumar Sankaran 6025fdd593SJeykumar Sankaran DPU_DEBUG("\n"); 6125fdd593SJeykumar Sankaran 6225fdd593SJeykumar Sankaran if (!crtc) 6325fdd593SJeykumar Sankaran return; 6425fdd593SJeykumar Sankaran 6525fdd593SJeykumar Sankaran drm_crtc_cleanup(crtc); 6625fdd593SJeykumar Sankaran kfree(dpu_crtc); 6725fdd593SJeykumar Sankaran } 6825fdd593SJeykumar Sankaran 6925fdd593SJeykumar Sankaran static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, 7074593a28SSravanthi Kollukuduru struct dpu_plane_state *pstate, struct dpu_format *format) 7125fdd593SJeykumar Sankaran { 7225fdd593SJeykumar Sankaran struct dpu_hw_mixer *lm = mixer->hw_lm; 7374593a28SSravanthi Kollukuduru uint32_t blend_op; 7474593a28SSravanthi Kollukuduru struct drm_format_name_buf format_name; 7525fdd593SJeykumar Sankaran 7625fdd593SJeykumar Sankaran /* default to opaque blending */ 7774593a28SSravanthi Kollukuduru blend_op = DPU_BLEND_FG_ALPHA_FG_CONST | 7874593a28SSravanthi Kollukuduru DPU_BLEND_BG_ALPHA_BG_CONST; 7974593a28SSravanthi Kollukuduru 8074593a28SSravanthi Kollukuduru if (format->alpha_enable) { 8174593a28SSravanthi Kollukuduru /* coverage blending */ 8274593a28SSravanthi Kollukuduru blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL | 8374593a28SSravanthi Kollukuduru DPU_BLEND_BG_ALPHA_FG_PIXEL | 8474593a28SSravanthi Kollukuduru DPU_BLEND_BG_INV_ALPHA; 8574593a28SSravanthi Kollukuduru } 8674593a28SSravanthi Kollukuduru 8774593a28SSravanthi Kollukuduru lm->ops.setup_blend_config(lm, pstate->stage, 8874593a28SSravanthi Kollukuduru 0xFF, 0, blend_op); 8974593a28SSravanthi Kollukuduru 9074593a28SSravanthi Kollukuduru DPU_DEBUG("format:%s, alpha_en:%u blend_op:0x%x\n", 9174593a28SSravanthi Kollukuduru drm_get_format_name(format->base.pixel_format, &format_name), 9274593a28SSravanthi Kollukuduru format->alpha_enable, blend_op); 9325fdd593SJeykumar Sankaran } 9425fdd593SJeykumar Sankaran 9525fdd593SJeykumar Sankaran static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) 9625fdd593SJeykumar Sankaran { 9725fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 9825fdd593SJeykumar Sankaran struct dpu_crtc_state *crtc_state; 9925fdd593SJeykumar Sankaran int lm_idx, lm_horiz_position; 10025fdd593SJeykumar Sankaran 10125fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 10225fdd593SJeykumar Sankaran crtc_state = to_dpu_crtc_state(crtc->state); 10325fdd593SJeykumar Sankaran 10425fdd593SJeykumar Sankaran lm_horiz_position = 0; 1059222cdd2SJeykumar Sankaran for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) { 10625fdd593SJeykumar Sankaran const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx]; 1079222cdd2SJeykumar Sankaran struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm; 10825fdd593SJeykumar Sankaran struct dpu_hw_mixer_cfg cfg; 10925fdd593SJeykumar Sankaran 11025fdd593SJeykumar Sankaran if (!lm_roi || !drm_rect_visible(lm_roi)) 11125fdd593SJeykumar Sankaran continue; 11225fdd593SJeykumar Sankaran 11325fdd593SJeykumar Sankaran cfg.out_width = drm_rect_width(lm_roi); 11425fdd593SJeykumar Sankaran cfg.out_height = drm_rect_height(lm_roi); 11525fdd593SJeykumar Sankaran cfg.right_mixer = lm_horiz_position++; 11625fdd593SJeykumar Sankaran cfg.flags = 0; 11725fdd593SJeykumar Sankaran hw_lm->ops.setup_mixer_out(hw_lm, &cfg); 11825fdd593SJeykumar Sankaran } 11925fdd593SJeykumar Sankaran } 12025fdd593SJeykumar Sankaran 12125fdd593SJeykumar Sankaran static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, 12225fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer) 12325fdd593SJeykumar Sankaran { 12425fdd593SJeykumar Sankaran struct drm_plane *plane; 12525fdd593SJeykumar Sankaran struct drm_framebuffer *fb; 12625fdd593SJeykumar Sankaran struct drm_plane_state *state; 12704b96b63SBruce Wang struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 12825fdd593SJeykumar Sankaran struct dpu_plane_state *pstate = NULL; 12925fdd593SJeykumar Sankaran struct dpu_format *format; 13004b96b63SBruce Wang struct dpu_hw_ctl *ctl = mixer->lm_ctl; 13104b96b63SBruce Wang struct dpu_hw_stage_cfg *stage_cfg = &dpu_crtc->stage_cfg; 13225fdd593SJeykumar Sankaran 13325fdd593SJeykumar Sankaran u32 flush_mask; 13425fdd593SJeykumar Sankaran uint32_t stage_idx, lm_idx; 13525fdd593SJeykumar Sankaran int zpos_cnt[DPU_STAGE_MAX + 1] = { 0 }; 13625fdd593SJeykumar Sankaran bool bg_alpha_enable = false; 13725fdd593SJeykumar Sankaran 13825fdd593SJeykumar Sankaran drm_atomic_crtc_for_each_plane(plane, crtc) { 13925fdd593SJeykumar Sankaran state = plane->state; 14025fdd593SJeykumar Sankaran if (!state) 14125fdd593SJeykumar Sankaran continue; 14225fdd593SJeykumar Sankaran 14325fdd593SJeykumar Sankaran pstate = to_dpu_plane_state(state); 14425fdd593SJeykumar Sankaran fb = state->fb; 14525fdd593SJeykumar Sankaran 14625fdd593SJeykumar Sankaran dpu_plane_get_ctl_flush(plane, ctl, &flush_mask); 14725fdd593SJeykumar Sankaran 14825fdd593SJeykumar Sankaran DPU_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n", 14925fdd593SJeykumar Sankaran crtc->base.id, 15025fdd593SJeykumar Sankaran pstate->stage, 15125fdd593SJeykumar Sankaran plane->base.id, 15225fdd593SJeykumar Sankaran dpu_plane_pipe(plane) - SSPP_VIG0, 15325fdd593SJeykumar Sankaran state->fb ? state->fb->base.id : -1); 15425fdd593SJeykumar Sankaran 15525fdd593SJeykumar Sankaran format = to_dpu_format(msm_framebuffer_format(pstate->base.fb)); 15625fdd593SJeykumar Sankaran 15725fdd593SJeykumar Sankaran if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable) 15825fdd593SJeykumar Sankaran bg_alpha_enable = true; 15925fdd593SJeykumar Sankaran 16025fdd593SJeykumar Sankaran stage_idx = zpos_cnt[pstate->stage]++; 16125fdd593SJeykumar Sankaran stage_cfg->stage[pstate->stage][stage_idx] = 16225fdd593SJeykumar Sankaran dpu_plane_pipe(plane); 16325fdd593SJeykumar Sankaran stage_cfg->multirect_index[pstate->stage][stage_idx] = 16425fdd593SJeykumar Sankaran pstate->multirect_index; 16525fdd593SJeykumar Sankaran 16625fdd593SJeykumar Sankaran trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), 16725fdd593SJeykumar Sankaran state, pstate, stage_idx, 16825fdd593SJeykumar Sankaran dpu_plane_pipe(plane) - SSPP_VIG0, 16925fdd593SJeykumar Sankaran format->base.pixel_format, 17025fdd593SJeykumar Sankaran fb ? fb->modifier : 0); 17125fdd593SJeykumar Sankaran 17225fdd593SJeykumar Sankaran /* blend config update */ 1739222cdd2SJeykumar Sankaran for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) { 17474593a28SSravanthi Kollukuduru _dpu_crtc_setup_blend_cfg(mixer + lm_idx, 17574593a28SSravanthi Kollukuduru pstate, format); 17625fdd593SJeykumar Sankaran 17725fdd593SJeykumar Sankaran mixer[lm_idx].flush_mask |= flush_mask; 17825fdd593SJeykumar Sankaran 17925fdd593SJeykumar Sankaran if (bg_alpha_enable && !format->alpha_enable) 18025fdd593SJeykumar Sankaran mixer[lm_idx].mixer_op_mode = 0; 18125fdd593SJeykumar Sankaran else 18225fdd593SJeykumar Sankaran mixer[lm_idx].mixer_op_mode |= 18325fdd593SJeykumar Sankaran 1 << pstate->stage; 18425fdd593SJeykumar Sankaran } 18525fdd593SJeykumar Sankaran } 18625fdd593SJeykumar Sankaran 18725fdd593SJeykumar Sankaran _dpu_crtc_program_lm_output_roi(crtc); 18825fdd593SJeykumar Sankaran } 18925fdd593SJeykumar Sankaran 19025fdd593SJeykumar Sankaran /** 19125fdd593SJeykumar Sankaran * _dpu_crtc_blend_setup - configure crtc mixers 19225fdd593SJeykumar Sankaran * @crtc: Pointer to drm crtc structure 19325fdd593SJeykumar Sankaran */ 19425fdd593SJeykumar Sankaran static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) 19525fdd593SJeykumar Sankaran { 19604b96b63SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 19704b96b63SBruce Wang struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 19804b96b63SBruce Wang struct dpu_crtc_mixer *mixer = cstate->mixers; 19925fdd593SJeykumar Sankaran struct dpu_hw_ctl *ctl; 20025fdd593SJeykumar Sankaran struct dpu_hw_mixer *lm; 20125fdd593SJeykumar Sankaran int i; 20225fdd593SJeykumar Sankaran 20325fdd593SJeykumar Sankaran DPU_DEBUG("%s\n", dpu_crtc->name); 20425fdd593SJeykumar Sankaran 2059222cdd2SJeykumar Sankaran for (i = 0; i < cstate->num_mixers; i++) { 206cf6916f4SJeykumar Sankaran if (!mixer[i].hw_lm || !mixer[i].lm_ctl) { 20725fdd593SJeykumar Sankaran DPU_ERROR("invalid lm or ctl assigned to mixer\n"); 20825fdd593SJeykumar Sankaran return; 20925fdd593SJeykumar Sankaran } 21025fdd593SJeykumar Sankaran mixer[i].mixer_op_mode = 0; 21125fdd593SJeykumar Sankaran mixer[i].flush_mask = 0; 212cf6916f4SJeykumar Sankaran if (mixer[i].lm_ctl->ops.clear_all_blendstages) 213cf6916f4SJeykumar Sankaran mixer[i].lm_ctl->ops.clear_all_blendstages( 214cf6916f4SJeykumar Sankaran mixer[i].lm_ctl); 21525fdd593SJeykumar Sankaran } 21625fdd593SJeykumar Sankaran 21725fdd593SJeykumar Sankaran /* initialize stage cfg */ 21825fdd593SJeykumar Sankaran memset(&dpu_crtc->stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg)); 21925fdd593SJeykumar Sankaran 22025fdd593SJeykumar Sankaran _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer); 22125fdd593SJeykumar Sankaran 2229222cdd2SJeykumar Sankaran for (i = 0; i < cstate->num_mixers; i++) { 223cf6916f4SJeykumar Sankaran ctl = mixer[i].lm_ctl; 22425fdd593SJeykumar Sankaran lm = mixer[i].hw_lm; 22525fdd593SJeykumar Sankaran 22625fdd593SJeykumar Sankaran lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode); 22725fdd593SJeykumar Sankaran 22825fdd593SJeykumar Sankaran mixer[i].flush_mask |= ctl->ops.get_bitmask_mixer(ctl, 22925fdd593SJeykumar Sankaran mixer[i].hw_lm->idx); 23025fdd593SJeykumar Sankaran 23125fdd593SJeykumar Sankaran /* stage config flush mask */ 23225fdd593SJeykumar Sankaran ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); 23325fdd593SJeykumar Sankaran 23425fdd593SJeykumar Sankaran DPU_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n", 23525fdd593SJeykumar Sankaran mixer[i].hw_lm->idx - LM_0, 23625fdd593SJeykumar Sankaran mixer[i].mixer_op_mode, 23725fdd593SJeykumar Sankaran ctl->idx - CTL_0, 23825fdd593SJeykumar Sankaran mixer[i].flush_mask); 23925fdd593SJeykumar Sankaran 24025fdd593SJeykumar Sankaran ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, 24125fdd593SJeykumar Sankaran &dpu_crtc->stage_cfg); 24225fdd593SJeykumar Sankaran } 24325fdd593SJeykumar Sankaran } 24425fdd593SJeykumar Sankaran 24525fdd593SJeykumar Sankaran /** 24625fdd593SJeykumar Sankaran * _dpu_crtc_complete_flip - signal pending page_flip events 24725fdd593SJeykumar Sankaran * Any pending vblank events are added to the vblank_event_list 24825fdd593SJeykumar Sankaran * so that the next vblank interrupt shall signal them. 24925fdd593SJeykumar Sankaran * However PAGE_FLIP events are not handled through the vblank_event_list. 25025fdd593SJeykumar Sankaran * This API signals any pending PAGE_FLIP events requested through 25125fdd593SJeykumar Sankaran * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the dpu_crtc->event. 25225fdd593SJeykumar Sankaran * @crtc: Pointer to drm crtc structure 25325fdd593SJeykumar Sankaran */ 25425fdd593SJeykumar Sankaran static void _dpu_crtc_complete_flip(struct drm_crtc *crtc) 25525fdd593SJeykumar Sankaran { 25625fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 25725fdd593SJeykumar Sankaran struct drm_device *dev = crtc->dev; 25825fdd593SJeykumar Sankaran unsigned long flags; 25925fdd593SJeykumar Sankaran 26025fdd593SJeykumar Sankaran spin_lock_irqsave(&dev->event_lock, flags); 26125fdd593SJeykumar Sankaran if (dpu_crtc->event) { 26225fdd593SJeykumar Sankaran DRM_DEBUG_VBL("%s: send event: %pK\n", dpu_crtc->name, 26325fdd593SJeykumar Sankaran dpu_crtc->event); 26425fdd593SJeykumar Sankaran trace_dpu_crtc_complete_flip(DRMID(crtc)); 26525fdd593SJeykumar Sankaran drm_crtc_send_vblank_event(crtc, dpu_crtc->event); 26625fdd593SJeykumar Sankaran dpu_crtc->event = NULL; 26725fdd593SJeykumar Sankaran } 26825fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dev->event_lock, flags); 26925fdd593SJeykumar Sankaran } 27025fdd593SJeykumar Sankaran 27125fdd593SJeykumar Sankaran enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc) 27225fdd593SJeykumar Sankaran { 27325fdd593SJeykumar Sankaran struct drm_encoder *encoder; 27425fdd593SJeykumar Sankaran 27525fdd593SJeykumar Sankaran if (!crtc || !crtc->dev) { 27625fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 27725fdd593SJeykumar Sankaran return INTF_MODE_NONE; 27825fdd593SJeykumar Sankaran } 27925fdd593SJeykumar Sankaran 2801dfdb0e1SSean Paul WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); 2811dfdb0e1SSean Paul 2824b8c6279SSean Paul /* TODO: Returns the first INTF_MODE, could there be multiple values? */ 2834b8c6279SSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) 28425fdd593SJeykumar Sankaran return dpu_encoder_get_intf_mode(encoder); 28525fdd593SJeykumar Sankaran 28625fdd593SJeykumar Sankaran return INTF_MODE_NONE; 28725fdd593SJeykumar Sankaran } 28825fdd593SJeykumar Sankaran 289e4914867SSean Paul void dpu_crtc_vblank_callback(struct drm_crtc *crtc) 29025fdd593SJeykumar Sankaran { 29125fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 29225fdd593SJeykumar Sankaran 29325fdd593SJeykumar Sankaran /* keep statistics on vblank callback - with auto reset via debugfs */ 29425fdd593SJeykumar Sankaran if (ktime_compare(dpu_crtc->vblank_cb_time, ktime_set(0, 0)) == 0) 29525fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_time = ktime_get(); 29625fdd593SJeykumar Sankaran else 29725fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_count++; 29825fdd593SJeykumar Sankaran _dpu_crtc_complete_flip(crtc); 29925fdd593SJeykumar Sankaran drm_crtc_handle_vblank(crtc); 30025fdd593SJeykumar Sankaran trace_dpu_crtc_vblank_cb(DRMID(crtc)); 30125fdd593SJeykumar Sankaran } 30225fdd593SJeykumar Sankaran 303f449aa6eSSean Paul static void dpu_crtc_release_bw_unlocked(struct drm_crtc *crtc) 304f449aa6eSSean Paul { 305f449aa6eSSean Paul int ret = 0; 306f449aa6eSSean Paul struct drm_modeset_acquire_ctx ctx; 307f449aa6eSSean Paul 308f449aa6eSSean Paul DRM_MODESET_LOCK_ALL_BEGIN(crtc->dev, ctx, 0, ret); 309f449aa6eSSean Paul dpu_core_perf_crtc_release_bw(crtc); 310f449aa6eSSean Paul DRM_MODESET_LOCK_ALL_END(ctx, ret); 311f449aa6eSSean Paul if (ret) 312f449aa6eSSean Paul DRM_ERROR("Failed to acquire modeset locks to release bw, %d\n", 313f449aa6eSSean Paul ret); 314f449aa6eSSean Paul } 315f449aa6eSSean Paul 31625fdd593SJeykumar Sankaran static void dpu_crtc_frame_event_work(struct kthread_work *work) 31725fdd593SJeykumar Sankaran { 31804b96b63SBruce Wang struct dpu_crtc_frame_event *fevent = container_of(work, 31904b96b63SBruce Wang struct dpu_crtc_frame_event, work); 32004b96b63SBruce Wang struct drm_crtc *crtc = fevent->crtc; 32104b96b63SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 32225fdd593SJeykumar Sankaran unsigned long flags; 32325fdd593SJeykumar Sankaran bool frame_done = false; 32425fdd593SJeykumar Sankaran 32525fdd593SJeykumar Sankaran DPU_ATRACE_BEGIN("crtc_frame_event"); 32625fdd593SJeykumar Sankaran 32725fdd593SJeykumar Sankaran DRM_DEBUG_KMS("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event, 32825fdd593SJeykumar Sankaran ktime_to_ns(fevent->ts)); 32925fdd593SJeykumar Sankaran 33025fdd593SJeykumar Sankaran if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE 33125fdd593SJeykumar Sankaran | DPU_ENCODER_FRAME_EVENT_ERROR 33225fdd593SJeykumar Sankaran | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) { 33325fdd593SJeykumar Sankaran 33425fdd593SJeykumar Sankaran if (atomic_read(&dpu_crtc->frame_pending) < 1) { 33525fdd593SJeykumar Sankaran /* this should not happen */ 33625fdd593SJeykumar Sankaran DRM_ERROR("crtc%d ev:%u ts:%lld frame_pending:%d\n", 33725fdd593SJeykumar Sankaran crtc->base.id, 33825fdd593SJeykumar Sankaran fevent->event, 33925fdd593SJeykumar Sankaran ktime_to_ns(fevent->ts), 34025fdd593SJeykumar Sankaran atomic_read(&dpu_crtc->frame_pending)); 34125fdd593SJeykumar Sankaran } else if (atomic_dec_return(&dpu_crtc->frame_pending) == 0) { 34225fdd593SJeykumar Sankaran /* release bandwidth and other resources */ 34325fdd593SJeykumar Sankaran trace_dpu_crtc_frame_event_done(DRMID(crtc), 34425fdd593SJeykumar Sankaran fevent->event); 345f449aa6eSSean Paul dpu_crtc_release_bw_unlocked(crtc); 34625fdd593SJeykumar Sankaran } else { 34725fdd593SJeykumar Sankaran trace_dpu_crtc_frame_event_more_pending(DRMID(crtc), 34825fdd593SJeykumar Sankaran fevent->event); 34925fdd593SJeykumar Sankaran } 35025fdd593SJeykumar Sankaran 35125fdd593SJeykumar Sankaran if (fevent->event & DPU_ENCODER_FRAME_EVENT_DONE) 35225fdd593SJeykumar Sankaran dpu_core_perf_crtc_update(crtc, 0, false); 35325fdd593SJeykumar Sankaran 35425fdd593SJeykumar Sankaran if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE 35525fdd593SJeykumar Sankaran | DPU_ENCODER_FRAME_EVENT_ERROR)) 35625fdd593SJeykumar Sankaran frame_done = true; 35725fdd593SJeykumar Sankaran } 35825fdd593SJeykumar Sankaran 35925fdd593SJeykumar Sankaran if (fevent->event & DPU_ENCODER_FRAME_EVENT_PANEL_DEAD) 36025fdd593SJeykumar Sankaran DPU_ERROR("crtc%d ts:%lld received panel dead event\n", 36125fdd593SJeykumar Sankaran crtc->base.id, ktime_to_ns(fevent->ts)); 36225fdd593SJeykumar Sankaran 36325fdd593SJeykumar Sankaran if (frame_done) 36425fdd593SJeykumar Sankaran complete_all(&dpu_crtc->frame_done_comp); 36525fdd593SJeykumar Sankaran 36625fdd593SJeykumar Sankaran spin_lock_irqsave(&dpu_crtc->spin_lock, flags); 36725fdd593SJeykumar Sankaran list_add_tail(&fevent->list, &dpu_crtc->frame_event_list); 36825fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags); 36925fdd593SJeykumar Sankaran DPU_ATRACE_END("crtc_frame_event"); 37025fdd593SJeykumar Sankaran } 37125fdd593SJeykumar Sankaran 37225fdd593SJeykumar Sankaran /* 37325fdd593SJeykumar Sankaran * dpu_crtc_frame_event_cb - crtc frame event callback API. CRTC module 37425fdd593SJeykumar Sankaran * registers this API to encoder for all frame event callbacks like 37525fdd593SJeykumar Sankaran * frame_error, frame_done, idle_timeout, etc. Encoder may call different events 37625fdd593SJeykumar Sankaran * from different context - IRQ, user thread, commit_thread, etc. Each event 37725fdd593SJeykumar Sankaran * should be carefully reviewed and should be processed in proper task context 37825fdd593SJeykumar Sankaran * to avoid schedulin delay or properly manage the irq context's bottom half 37925fdd593SJeykumar Sankaran * processing. 38025fdd593SJeykumar Sankaran */ 38125fdd593SJeykumar Sankaran static void dpu_crtc_frame_event_cb(void *data, u32 event) 38225fdd593SJeykumar Sankaran { 38325fdd593SJeykumar Sankaran struct drm_crtc *crtc = (struct drm_crtc *)data; 38425fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 38525fdd593SJeykumar Sankaran struct msm_drm_private *priv; 38625fdd593SJeykumar Sankaran struct dpu_crtc_frame_event *fevent; 38725fdd593SJeykumar Sankaran unsigned long flags; 38825fdd593SJeykumar Sankaran u32 crtc_id; 38925fdd593SJeykumar Sankaran 39025fdd593SJeykumar Sankaran /* Nothing to do on idle event */ 39125fdd593SJeykumar Sankaran if (event & DPU_ENCODER_FRAME_EVENT_IDLE) 39225fdd593SJeykumar Sankaran return; 39325fdd593SJeykumar Sankaran 39425fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 39525fdd593SJeykumar Sankaran priv = crtc->dev->dev_private; 39625fdd593SJeykumar Sankaran crtc_id = drm_crtc_index(crtc); 39725fdd593SJeykumar Sankaran 39825fdd593SJeykumar Sankaran trace_dpu_crtc_frame_event_cb(DRMID(crtc), event); 39925fdd593SJeykumar Sankaran 40025fdd593SJeykumar Sankaran spin_lock_irqsave(&dpu_crtc->spin_lock, flags); 40125fdd593SJeykumar Sankaran fevent = list_first_entry_or_null(&dpu_crtc->frame_event_list, 40225fdd593SJeykumar Sankaran struct dpu_crtc_frame_event, list); 40325fdd593SJeykumar Sankaran if (fevent) 40425fdd593SJeykumar Sankaran list_del_init(&fevent->list); 40525fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags); 40625fdd593SJeykumar Sankaran 40725fdd593SJeykumar Sankaran if (!fevent) { 40825fdd593SJeykumar Sankaran DRM_ERROR("crtc%d event %d overflow\n", crtc->base.id, event); 40925fdd593SJeykumar Sankaran return; 41025fdd593SJeykumar Sankaran } 41125fdd593SJeykumar Sankaran 41225fdd593SJeykumar Sankaran fevent->event = event; 41325fdd593SJeykumar Sankaran fevent->crtc = crtc; 41425fdd593SJeykumar Sankaran fevent->ts = ktime_get(); 41525fdd593SJeykumar Sankaran kthread_queue_work(&priv->event_thread[crtc_id].worker, &fevent->work); 41625fdd593SJeykumar Sankaran } 41725fdd593SJeykumar Sankaran 41825fdd593SJeykumar Sankaran void dpu_crtc_complete_commit(struct drm_crtc *crtc, 41925fdd593SJeykumar Sankaran struct drm_crtc_state *old_state) 42025fdd593SJeykumar Sankaran { 42125fdd593SJeykumar Sankaran if (!crtc || !crtc->state) { 42225fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 42325fdd593SJeykumar Sankaran return; 42425fdd593SJeykumar Sankaran } 42525fdd593SJeykumar Sankaran trace_dpu_crtc_complete_commit(DRMID(crtc)); 42625fdd593SJeykumar Sankaran } 42725fdd593SJeykumar Sankaran 42825fdd593SJeykumar Sankaran static void _dpu_crtc_setup_mixer_for_encoder( 42925fdd593SJeykumar Sankaran struct drm_crtc *crtc, 43025fdd593SJeykumar Sankaran struct drm_encoder *enc) 43125fdd593SJeykumar Sankaran { 4329222cdd2SJeykumar Sankaran struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 43325fdd593SJeykumar Sankaran struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); 43425fdd593SJeykumar Sankaran struct dpu_rm *rm = &dpu_kms->rm; 43525fdd593SJeykumar Sankaran struct dpu_crtc_mixer *mixer; 43625fdd593SJeykumar Sankaran struct dpu_hw_ctl *last_valid_ctl = NULL; 43725fdd593SJeykumar Sankaran int i; 43825fdd593SJeykumar Sankaran struct dpu_rm_hw_iter lm_iter, ctl_iter; 43925fdd593SJeykumar Sankaran 44025fdd593SJeykumar Sankaran dpu_rm_init_hw_iter(&lm_iter, enc->base.id, DPU_HW_BLK_LM); 44125fdd593SJeykumar Sankaran dpu_rm_init_hw_iter(&ctl_iter, enc->base.id, DPU_HW_BLK_CTL); 44225fdd593SJeykumar Sankaran 44325fdd593SJeykumar Sankaran /* Set up all the mixers and ctls reserved by this encoder */ 4449222cdd2SJeykumar Sankaran for (i = cstate->num_mixers; i < ARRAY_SIZE(cstate->mixers); i++) { 4459222cdd2SJeykumar Sankaran mixer = &cstate->mixers[i]; 44625fdd593SJeykumar Sankaran 44725fdd593SJeykumar Sankaran if (!dpu_rm_get_hw(rm, &lm_iter)) 44825fdd593SJeykumar Sankaran break; 44925fdd593SJeykumar Sankaran mixer->hw_lm = (struct dpu_hw_mixer *)lm_iter.hw; 45025fdd593SJeykumar Sankaran 45125fdd593SJeykumar Sankaran /* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */ 45225fdd593SJeykumar Sankaran if (!dpu_rm_get_hw(rm, &ctl_iter)) { 45325fdd593SJeykumar Sankaran DPU_DEBUG("no ctl assigned to lm %d, using previous\n", 45425fdd593SJeykumar Sankaran mixer->hw_lm->idx - LM_0); 455cf6916f4SJeykumar Sankaran mixer->lm_ctl = last_valid_ctl; 45625fdd593SJeykumar Sankaran } else { 457cf6916f4SJeykumar Sankaran mixer->lm_ctl = (struct dpu_hw_ctl *)ctl_iter.hw; 458cf6916f4SJeykumar Sankaran last_valid_ctl = mixer->lm_ctl; 45925fdd593SJeykumar Sankaran } 46025fdd593SJeykumar Sankaran 46125fdd593SJeykumar Sankaran /* Shouldn't happen, mixers are always >= ctls */ 462cf6916f4SJeykumar Sankaran if (!mixer->lm_ctl) { 46325fdd593SJeykumar Sankaran DPU_ERROR("no valid ctls found for lm %d\n", 46425fdd593SJeykumar Sankaran mixer->hw_lm->idx - LM_0); 46525fdd593SJeykumar Sankaran return; 46625fdd593SJeykumar Sankaran } 46725fdd593SJeykumar Sankaran 46825fdd593SJeykumar Sankaran mixer->encoder = enc; 46925fdd593SJeykumar Sankaran 4709222cdd2SJeykumar Sankaran cstate->num_mixers++; 47125fdd593SJeykumar Sankaran DPU_DEBUG("setup mixer %d: lm %d\n", 47225fdd593SJeykumar Sankaran i, mixer->hw_lm->idx - LM_0); 47325fdd593SJeykumar Sankaran DPU_DEBUG("setup mixer %d: ctl %d\n", 474cf6916f4SJeykumar Sankaran i, mixer->lm_ctl->idx - CTL_0); 47525fdd593SJeykumar Sankaran } 47625fdd593SJeykumar Sankaran } 47725fdd593SJeykumar Sankaran 47825fdd593SJeykumar Sankaran static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc) 47925fdd593SJeykumar Sankaran { 48025fdd593SJeykumar Sankaran struct drm_encoder *enc; 48125fdd593SJeykumar Sankaran 482a9d629d7SSean Paul WARN_ON(!drm_modeset_is_locked(&crtc->mutex)); 483a9d629d7SSean Paul 48425fdd593SJeykumar Sankaran /* Check for mixers on all encoders attached to this crtc */ 485a9d629d7SSean Paul drm_for_each_encoder_mask(enc, crtc->dev, crtc->state->encoder_mask) 48625fdd593SJeykumar Sankaran _dpu_crtc_setup_mixer_for_encoder(crtc, enc); 48725fdd593SJeykumar Sankaran } 48825fdd593SJeykumar Sankaran 48925fdd593SJeykumar Sankaran static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc, 49025fdd593SJeykumar Sankaran struct drm_crtc_state *state) 49125fdd593SJeykumar Sankaran { 49204b96b63SBruce Wang struct dpu_crtc_state *cstate = to_dpu_crtc_state(state); 49304b96b63SBruce Wang struct drm_display_mode *adj_mode = &state->adjusted_mode; 4943804a982SJordan Crouse u32 crtc_split_width = adj_mode->hdisplay / cstate->num_mixers; 49525fdd593SJeykumar Sankaran int i; 49625fdd593SJeykumar Sankaran 4979222cdd2SJeykumar Sankaran for (i = 0; i < cstate->num_mixers; i++) { 49825fdd593SJeykumar Sankaran struct drm_rect *r = &cstate->lm_bounds[i]; 49925fdd593SJeykumar Sankaran r->x1 = crtc_split_width * i; 50025fdd593SJeykumar Sankaran r->y1 = 0; 50125fdd593SJeykumar Sankaran r->x2 = r->x1 + crtc_split_width; 50235d600ddSJordan Crouse r->y2 = adj_mode->vdisplay; 50325fdd593SJeykumar Sankaran 50425fdd593SJeykumar Sankaran trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i, r); 50525fdd593SJeykumar Sankaran } 50625fdd593SJeykumar Sankaran 50725fdd593SJeykumar Sankaran drm_mode_debug_printmodeline(adj_mode); 50825fdd593SJeykumar Sankaran } 50925fdd593SJeykumar Sankaran 51025fdd593SJeykumar Sankaran static void dpu_crtc_atomic_begin(struct drm_crtc *crtc, 51125fdd593SJeykumar Sankaran struct drm_crtc_state *old_state) 51225fdd593SJeykumar Sankaran { 51325fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 5149222cdd2SJeykumar Sankaran struct dpu_crtc_state *cstate; 51525fdd593SJeykumar Sankaran struct drm_encoder *encoder; 51625fdd593SJeykumar Sankaran struct drm_device *dev; 51725fdd593SJeykumar Sankaran unsigned long flags; 51825fdd593SJeykumar Sankaran struct dpu_crtc_smmu_state_data *smmu_state; 51925fdd593SJeykumar Sankaran 52025fdd593SJeykumar Sankaran if (!crtc) { 52125fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 52225fdd593SJeykumar Sankaran return; 52325fdd593SJeykumar Sankaran } 52425fdd593SJeykumar Sankaran 52525fdd593SJeykumar Sankaran if (!crtc->state->enable) { 52625fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d -> enable %d, skip atomic_begin\n", 52725fdd593SJeykumar Sankaran crtc->base.id, crtc->state->enable); 52825fdd593SJeykumar Sankaran return; 52925fdd593SJeykumar Sankaran } 53025fdd593SJeykumar Sankaran 53125fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d\n", crtc->base.id); 53225fdd593SJeykumar Sankaran 53325fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 5349222cdd2SJeykumar Sankaran cstate = to_dpu_crtc_state(crtc->state); 53525fdd593SJeykumar Sankaran dev = crtc->dev; 53625fdd593SJeykumar Sankaran smmu_state = &dpu_crtc->smmu_state; 53725fdd593SJeykumar Sankaran 5389222cdd2SJeykumar Sankaran if (!cstate->num_mixers) { 53925fdd593SJeykumar Sankaran _dpu_crtc_setup_mixers(crtc); 54025fdd593SJeykumar Sankaran _dpu_crtc_setup_lm_bounds(crtc, crtc->state); 54125fdd593SJeykumar Sankaran } 54225fdd593SJeykumar Sankaran 54325fdd593SJeykumar Sankaran if (dpu_crtc->event) { 54425fdd593SJeykumar Sankaran WARN_ON(dpu_crtc->event); 54525fdd593SJeykumar Sankaran } else { 54625fdd593SJeykumar Sankaran spin_lock_irqsave(&dev->event_lock, flags); 54725fdd593SJeykumar Sankaran dpu_crtc->event = crtc->state->event; 54825fdd593SJeykumar Sankaran crtc->state->event = NULL; 54925fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dev->event_lock, flags); 55025fdd593SJeykumar Sankaran } 55125fdd593SJeykumar Sankaran 55225fdd593SJeykumar Sankaran /* encoder will trigger pending mask now */ 5534b8c6279SSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) 55425fdd593SJeykumar Sankaran dpu_encoder_trigger_kickoff_pending(encoder); 55525fdd593SJeykumar Sankaran 55625fdd593SJeykumar Sankaran /* 55725fdd593SJeykumar Sankaran * If no mixers have been allocated in dpu_crtc_atomic_check(), 55825fdd593SJeykumar Sankaran * it means we are trying to flush a CRTC whose state is disabled: 55925fdd593SJeykumar Sankaran * nothing else needs to be done. 56025fdd593SJeykumar Sankaran */ 5619222cdd2SJeykumar Sankaran if (unlikely(!cstate->num_mixers)) 56225fdd593SJeykumar Sankaran return; 56325fdd593SJeykumar Sankaran 56425fdd593SJeykumar Sankaran _dpu_crtc_blend_setup(crtc); 56525fdd593SJeykumar Sankaran 56625fdd593SJeykumar Sankaran /* 56725fdd593SJeykumar Sankaran * PP_DONE irq is only used by command mode for now. 56825fdd593SJeykumar Sankaran * It is better to request pending before FLUSH and START trigger 56925fdd593SJeykumar Sankaran * to make sure no pp_done irq missed. 57025fdd593SJeykumar Sankaran * This is safe because no pp_done will happen before SW trigger 57125fdd593SJeykumar Sankaran * in command mode. 57225fdd593SJeykumar Sankaran */ 57325fdd593SJeykumar Sankaran } 57425fdd593SJeykumar Sankaran 57525fdd593SJeykumar Sankaran static void dpu_crtc_atomic_flush(struct drm_crtc *crtc, 57625fdd593SJeykumar Sankaran struct drm_crtc_state *old_crtc_state) 57725fdd593SJeykumar Sankaran { 57825fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 57925fdd593SJeykumar Sankaran struct drm_device *dev; 58025fdd593SJeykumar Sankaran struct drm_plane *plane; 58125fdd593SJeykumar Sankaran struct msm_drm_private *priv; 58225fdd593SJeykumar Sankaran struct msm_drm_thread *event_thread; 58325fdd593SJeykumar Sankaran unsigned long flags; 58425fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 58525fdd593SJeykumar Sankaran 58625fdd593SJeykumar Sankaran if (!crtc->state->enable) { 58725fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d -> enable %d, skip atomic_flush\n", 58825fdd593SJeykumar Sankaran crtc->base.id, crtc->state->enable); 58925fdd593SJeykumar Sankaran return; 59025fdd593SJeykumar Sankaran } 59125fdd593SJeykumar Sankaran 59225fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d\n", crtc->base.id); 59325fdd593SJeykumar Sankaran 59425fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 59525fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(crtc->state); 59625fdd593SJeykumar Sankaran dev = crtc->dev; 59725fdd593SJeykumar Sankaran priv = dev->dev_private; 59825fdd593SJeykumar Sankaran 59925fdd593SJeykumar Sankaran if (crtc->index >= ARRAY_SIZE(priv->event_thread)) { 60025fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc index[%d]\n", crtc->index); 60125fdd593SJeykumar Sankaran return; 60225fdd593SJeykumar Sankaran } 60325fdd593SJeykumar Sankaran 60425fdd593SJeykumar Sankaran event_thread = &priv->event_thread[crtc->index]; 60525fdd593SJeykumar Sankaran 60625fdd593SJeykumar Sankaran if (dpu_crtc->event) { 60725fdd593SJeykumar Sankaran DPU_DEBUG("already received dpu_crtc->event\n"); 60825fdd593SJeykumar Sankaran } else { 60925fdd593SJeykumar Sankaran spin_lock_irqsave(&dev->event_lock, flags); 61025fdd593SJeykumar Sankaran dpu_crtc->event = crtc->state->event; 61125fdd593SJeykumar Sankaran crtc->state->event = NULL; 61225fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dev->event_lock, flags); 61325fdd593SJeykumar Sankaran } 61425fdd593SJeykumar Sankaran 61525fdd593SJeykumar Sankaran /* 61625fdd593SJeykumar Sankaran * If no mixers has been allocated in dpu_crtc_atomic_check(), 61725fdd593SJeykumar Sankaran * it means we are trying to flush a CRTC whose state is disabled: 61825fdd593SJeykumar Sankaran * nothing else needs to be done. 61925fdd593SJeykumar Sankaran */ 6209222cdd2SJeykumar Sankaran if (unlikely(!cstate->num_mixers)) 62125fdd593SJeykumar Sankaran return; 62225fdd593SJeykumar Sankaran 62325fdd593SJeykumar Sankaran /* 62425fdd593SJeykumar Sankaran * For planes without commit update, drm framework will not add 62525fdd593SJeykumar Sankaran * those planes to current state since hardware update is not 62625fdd593SJeykumar Sankaran * required. However, if those planes were power collapsed since 62725fdd593SJeykumar Sankaran * last commit cycle, driver has to restore the hardware state 62825fdd593SJeykumar Sankaran * of those planes explicitly here prior to plane flush. 62925fdd593SJeykumar Sankaran */ 63025fdd593SJeykumar Sankaran drm_atomic_crtc_for_each_plane(plane, crtc) 63125fdd593SJeykumar Sankaran dpu_plane_restore(plane); 63225fdd593SJeykumar Sankaran 63325fdd593SJeykumar Sankaran /* update performance setting before crtc kickoff */ 63425fdd593SJeykumar Sankaran dpu_core_perf_crtc_update(crtc, 1, false); 63525fdd593SJeykumar Sankaran 63625fdd593SJeykumar Sankaran /* 63725fdd593SJeykumar Sankaran * Final plane updates: Give each plane a chance to complete all 63825fdd593SJeykumar Sankaran * required writes/flushing before crtc's "flush 63925fdd593SJeykumar Sankaran * everything" call below. 64025fdd593SJeykumar Sankaran */ 64125fdd593SJeykumar Sankaran drm_atomic_crtc_for_each_plane(plane, crtc) { 64225fdd593SJeykumar Sankaran if (dpu_crtc->smmu_state.transition_error) 64325fdd593SJeykumar Sankaran dpu_plane_set_error(plane, true); 64425fdd593SJeykumar Sankaran dpu_plane_flush(plane); 64525fdd593SJeykumar Sankaran } 64625fdd593SJeykumar Sankaran 64725fdd593SJeykumar Sankaran /* Kickoff will be scheduled by outer layer */ 64825fdd593SJeykumar Sankaran } 64925fdd593SJeykumar Sankaran 65025fdd593SJeykumar Sankaran /** 65125fdd593SJeykumar Sankaran * dpu_crtc_destroy_state - state destroy hook 65225fdd593SJeykumar Sankaran * @crtc: drm CRTC 65325fdd593SJeykumar Sankaran * @state: CRTC state object to release 65425fdd593SJeykumar Sankaran */ 65525fdd593SJeykumar Sankaran static void dpu_crtc_destroy_state(struct drm_crtc *crtc, 65625fdd593SJeykumar Sankaran struct drm_crtc_state *state) 65725fdd593SJeykumar Sankaran { 65825fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 65925fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 66025fdd593SJeykumar Sankaran 66125fdd593SJeykumar Sankaran if (!crtc || !state) { 66225fdd593SJeykumar Sankaran DPU_ERROR("invalid argument(s)\n"); 66325fdd593SJeykumar Sankaran return; 66425fdd593SJeykumar Sankaran } 66525fdd593SJeykumar Sankaran 66625fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 66725fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(state); 66825fdd593SJeykumar Sankaran 66925fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d\n", crtc->base.id); 67025fdd593SJeykumar Sankaran 67125fdd593SJeykumar Sankaran __drm_atomic_helper_crtc_destroy_state(state); 67225fdd593SJeykumar Sankaran 67325fdd593SJeykumar Sankaran kfree(cstate); 67425fdd593SJeykumar Sankaran } 67525fdd593SJeykumar Sankaran 67625fdd593SJeykumar Sankaran static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc) 67725fdd593SJeykumar Sankaran { 67804b96b63SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 67925fdd593SJeykumar Sankaran int ret, rc = 0; 68025fdd593SJeykumar Sankaran 68125fdd593SJeykumar Sankaran if (!atomic_read(&dpu_crtc->frame_pending)) { 68225fdd593SJeykumar Sankaran DPU_DEBUG("no frames pending\n"); 68325fdd593SJeykumar Sankaran return 0; 68425fdd593SJeykumar Sankaran } 68525fdd593SJeykumar Sankaran 68625fdd593SJeykumar Sankaran DPU_ATRACE_BEGIN("frame done completion wait"); 68725fdd593SJeykumar Sankaran ret = wait_for_completion_timeout(&dpu_crtc->frame_done_comp, 68825fdd593SJeykumar Sankaran msecs_to_jiffies(DPU_FRAME_DONE_TIMEOUT)); 68925fdd593SJeykumar Sankaran if (!ret) { 69025fdd593SJeykumar Sankaran DRM_ERROR("frame done wait timed out, ret:%d\n", ret); 69125fdd593SJeykumar Sankaran rc = -ETIMEDOUT; 69225fdd593SJeykumar Sankaran } 69325fdd593SJeykumar Sankaran DPU_ATRACE_END("frame done completion wait"); 69425fdd593SJeykumar Sankaran 69525fdd593SJeykumar Sankaran return rc; 69625fdd593SJeykumar Sankaran } 69725fdd593SJeykumar Sankaran 69850bcc689SSean Paul void dpu_crtc_commit_kickoff(struct drm_crtc *crtc, bool async) 69925fdd593SJeykumar Sankaran { 70025fdd593SJeykumar Sankaran struct drm_encoder *encoder; 70104b96b63SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 70204b96b63SBruce Wang struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc); 70304b96b63SBruce Wang struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state); 70425fdd593SJeykumar Sankaran int ret; 70525fdd593SJeykumar Sankaran 70625fdd593SJeykumar Sankaran /* 70725fdd593SJeykumar Sankaran * If no mixers has been allocated in dpu_crtc_atomic_check(), 70825fdd593SJeykumar Sankaran * it means we are trying to start a CRTC whose state is disabled: 70925fdd593SJeykumar Sankaran * nothing else needs to be done. 71025fdd593SJeykumar Sankaran */ 7119222cdd2SJeykumar Sankaran if (unlikely(!cstate->num_mixers)) 71225fdd593SJeykumar Sankaran return; 71325fdd593SJeykumar Sankaran 71425fdd593SJeykumar Sankaran DPU_ATRACE_BEGIN("crtc_commit"); 71525fdd593SJeykumar Sankaran 71625fdd593SJeykumar Sankaran /* 7174b8c6279SSean Paul * Encoder will flush/start now, unless it has a tx pending. If so, it 7184b8c6279SSean Paul * may delay and flush at an irq event (e.g. ppdone) 71925fdd593SJeykumar Sankaran */ 7204b8c6279SSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, 7214b8c6279SSean Paul crtc->state->encoder_mask) { 7224b8c6279SSean Paul struct dpu_encoder_kickoff_params params = { 0 }; 72350bcc689SSean Paul dpu_encoder_prepare_for_kickoff(encoder, ¶ms, async); 72425fdd593SJeykumar Sankaran } 72525fdd593SJeykumar Sankaran 72650bcc689SSean Paul 72750bcc689SSean Paul if (!async) { 72825fdd593SJeykumar Sankaran /* wait for frame_event_done completion */ 72925fdd593SJeykumar Sankaran DPU_ATRACE_BEGIN("wait_for_frame_done_event"); 73025fdd593SJeykumar Sankaran ret = _dpu_crtc_wait_for_frame_done(crtc); 73125fdd593SJeykumar Sankaran DPU_ATRACE_END("wait_for_frame_done_event"); 73225fdd593SJeykumar Sankaran if (ret) { 73325fdd593SJeykumar Sankaran DPU_ERROR("crtc%d wait for frame done failed;frame_pending%d\n", 73425fdd593SJeykumar Sankaran crtc->base.id, 73525fdd593SJeykumar Sankaran atomic_read(&dpu_crtc->frame_pending)); 73625fdd593SJeykumar Sankaran goto end; 73725fdd593SJeykumar Sankaran } 73825fdd593SJeykumar Sankaran 73925fdd593SJeykumar Sankaran if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) { 74025fdd593SJeykumar Sankaran /* acquire bandwidth and other resources */ 74125fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d first commit\n", crtc->base.id); 74225fdd593SJeykumar Sankaran } else 74325fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d commit\n", crtc->base.id); 74425fdd593SJeykumar Sankaran 74525fdd593SJeykumar Sankaran dpu_crtc->play_count++; 74650bcc689SSean Paul } 74725fdd593SJeykumar Sankaran 74825fdd593SJeykumar Sankaran dpu_vbif_clear_errors(dpu_kms); 74925fdd593SJeykumar Sankaran 7504b8c6279SSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) 75150bcc689SSean Paul dpu_encoder_kickoff(encoder, async); 75225fdd593SJeykumar Sankaran 75325fdd593SJeykumar Sankaran end: 75450bcc689SSean Paul if (!async) 75525fdd593SJeykumar Sankaran reinit_completion(&dpu_crtc->frame_done_comp); 75625fdd593SJeykumar Sankaran DPU_ATRACE_END("crtc_commit"); 75725fdd593SJeykumar Sankaran } 75825fdd593SJeykumar Sankaran 759ff5952a7SSean Paul static void dpu_crtc_reset(struct drm_crtc *crtc) 760ff5952a7SSean Paul { 761ff5952a7SSean Paul struct dpu_crtc_state *cstate; 762ff5952a7SSean Paul 763ff5952a7SSean Paul if (crtc->state) 764ff5952a7SSean Paul dpu_crtc_destroy_state(crtc, crtc->state); 765ff5952a7SSean Paul 766ff5952a7SSean Paul crtc->state = kzalloc(sizeof(*cstate), GFP_KERNEL); 767ff5952a7SSean Paul if (crtc->state) 768ff5952a7SSean Paul crtc->state->crtc = crtc; 769ff5952a7SSean Paul } 770ff5952a7SSean Paul 77125fdd593SJeykumar Sankaran /** 77225fdd593SJeykumar Sankaran * dpu_crtc_duplicate_state - state duplicate hook 77325fdd593SJeykumar Sankaran * @crtc: Pointer to drm crtc structure 77425fdd593SJeykumar Sankaran * @Returns: Pointer to new drm_crtc_state structure 77525fdd593SJeykumar Sankaran */ 77625fdd593SJeykumar Sankaran static struct drm_crtc_state *dpu_crtc_duplicate_state(struct drm_crtc *crtc) 77725fdd593SJeykumar Sankaran { 77825fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 77925fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate, *old_cstate; 78025fdd593SJeykumar Sankaran 78125fdd593SJeykumar Sankaran if (!crtc || !crtc->state) { 78225fdd593SJeykumar Sankaran DPU_ERROR("invalid argument(s)\n"); 78325fdd593SJeykumar Sankaran return NULL; 78425fdd593SJeykumar Sankaran } 78525fdd593SJeykumar Sankaran 78625fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 78725fdd593SJeykumar Sankaran old_cstate = to_dpu_crtc_state(crtc->state); 78825fdd593SJeykumar Sankaran cstate = kmemdup(old_cstate, sizeof(*old_cstate), GFP_KERNEL); 78925fdd593SJeykumar Sankaran if (!cstate) { 79025fdd593SJeykumar Sankaran DPU_ERROR("failed to allocate state\n"); 79125fdd593SJeykumar Sankaran return NULL; 79225fdd593SJeykumar Sankaran } 79325fdd593SJeykumar Sankaran 79425fdd593SJeykumar Sankaran /* duplicate base helper */ 79525fdd593SJeykumar Sankaran __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base); 79625fdd593SJeykumar Sankaran 79725fdd593SJeykumar Sankaran return &cstate->base; 79825fdd593SJeykumar Sankaran } 79925fdd593SJeykumar Sankaran 800f7aafc8dSSean Paul static void dpu_crtc_disable(struct drm_crtc *crtc, 801f7aafc8dSSean Paul struct drm_crtc_state *old_crtc_state) 80225fdd593SJeykumar Sankaran { 80325fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 80425fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 80525fdd593SJeykumar Sankaran struct drm_display_mode *mode; 80625fdd593SJeykumar Sankaran struct drm_encoder *encoder; 80725fdd593SJeykumar Sankaran struct msm_drm_private *priv; 8082f2eb723SRajesh Yadav unsigned long flags; 80925fdd593SJeykumar Sankaran 81025fdd593SJeykumar Sankaran if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) { 81125fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 81225fdd593SJeykumar Sankaran return; 81325fdd593SJeykumar Sankaran } 81425fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 81525fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(crtc->state); 81625fdd593SJeykumar Sankaran mode = &cstate->base.adjusted_mode; 81725fdd593SJeykumar Sankaran priv = crtc->dev->dev_private; 81825fdd593SJeykumar Sankaran 81925fdd593SJeykumar Sankaran DRM_DEBUG_KMS("crtc%d\n", crtc->base.id); 82025fdd593SJeykumar Sankaran 8212f2eb723SRajesh Yadav /* Disable/save vblank irq handling */ 8222f2eb723SRajesh Yadav drm_crtc_vblank_off(crtc); 8232f2eb723SRajesh Yadav 824a796ba2cSSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, 825a796ba2cSSean Paul old_crtc_state->encoder_mask) 826a796ba2cSSean Paul dpu_encoder_assign_crtc(encoder, NULL); 827a796ba2cSSean Paul 82825fdd593SJeykumar Sankaran /* wait for frame_event_done completion */ 82925fdd593SJeykumar Sankaran if (_dpu_crtc_wait_for_frame_done(crtc)) 83025fdd593SJeykumar Sankaran DPU_ERROR("crtc%d wait for frame done failed;frame_pending%d\n", 83125fdd593SJeykumar Sankaran crtc->base.id, 83225fdd593SJeykumar Sankaran atomic_read(&dpu_crtc->frame_pending)); 83325fdd593SJeykumar Sankaran 83425fdd593SJeykumar Sankaran trace_dpu_crtc_disable(DRMID(crtc), false, dpu_crtc); 83525fdd593SJeykumar Sankaran dpu_crtc->enabled = false; 83625fdd593SJeykumar Sankaran 83725fdd593SJeykumar Sankaran if (atomic_read(&dpu_crtc->frame_pending)) { 83825fdd593SJeykumar Sankaran trace_dpu_crtc_disable_frame_pending(DRMID(crtc), 83925fdd593SJeykumar Sankaran atomic_read(&dpu_crtc->frame_pending)); 84025fdd593SJeykumar Sankaran dpu_core_perf_crtc_release_bw(crtc); 84125fdd593SJeykumar Sankaran atomic_set(&dpu_crtc->frame_pending, 0); 84225fdd593SJeykumar Sankaran } 84325fdd593SJeykumar Sankaran 84425fdd593SJeykumar Sankaran dpu_core_perf_crtc_update(crtc, 0, true); 84525fdd593SJeykumar Sankaran 8464b8c6279SSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) 84725fdd593SJeykumar Sankaran dpu_encoder_register_frame_event_callback(encoder, NULL, NULL); 84825fdd593SJeykumar Sankaran 8499222cdd2SJeykumar Sankaran memset(cstate->mixers, 0, sizeof(cstate->mixers)); 8509222cdd2SJeykumar Sankaran cstate->num_mixers = 0; 85125fdd593SJeykumar Sankaran 85225fdd593SJeykumar Sankaran /* disable clk & bw control until clk & bw properties are set */ 85325fdd593SJeykumar Sankaran cstate->bw_control = false; 85425fdd593SJeykumar Sankaran cstate->bw_split_vote = false; 85525fdd593SJeykumar Sankaran 8562f2eb723SRajesh Yadav if (crtc->state->event && !crtc->state->active) { 8572f2eb723SRajesh Yadav spin_lock_irqsave(&crtc->dev->event_lock, flags); 8582f2eb723SRajesh Yadav drm_crtc_send_vblank_event(crtc, crtc->state->event); 8592f2eb723SRajesh Yadav crtc->state->event = NULL; 8602f2eb723SRajesh Yadav spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 8612f2eb723SRajesh Yadav } 862b77d0f0dSSean Paul 863b77d0f0dSSean Paul pm_runtime_put_sync(crtc->dev->dev); 86425fdd593SJeykumar Sankaran } 86525fdd593SJeykumar Sankaran 86625fdd593SJeykumar Sankaran static void dpu_crtc_enable(struct drm_crtc *crtc, 86725fdd593SJeykumar Sankaran struct drm_crtc_state *old_crtc_state) 86825fdd593SJeykumar Sankaran { 86925fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 87025fdd593SJeykumar Sankaran struct drm_encoder *encoder; 87125fdd593SJeykumar Sankaran struct msm_drm_private *priv; 87225fdd593SJeykumar Sankaran 87325fdd593SJeykumar Sankaran if (!crtc || !crtc->dev || !crtc->dev->dev_private) { 87425fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 87525fdd593SJeykumar Sankaran return; 87625fdd593SJeykumar Sankaran } 87725fdd593SJeykumar Sankaran priv = crtc->dev->dev_private; 87825fdd593SJeykumar Sankaran 879b77d0f0dSSean Paul pm_runtime_get_sync(crtc->dev->dev); 880b77d0f0dSSean Paul 88125fdd593SJeykumar Sankaran DRM_DEBUG_KMS("crtc%d\n", crtc->base.id); 88225fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 88325fdd593SJeykumar Sankaran 8844b8c6279SSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) 88525fdd593SJeykumar Sankaran dpu_encoder_register_frame_event_callback(encoder, 88625fdd593SJeykumar Sankaran dpu_crtc_frame_event_cb, (void *)crtc); 88725fdd593SJeykumar Sankaran 88825fdd593SJeykumar Sankaran trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc); 88925fdd593SJeykumar Sankaran dpu_crtc->enabled = true; 89025fdd593SJeykumar Sankaran 891a796ba2cSSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) 892a796ba2cSSean Paul dpu_encoder_assign_crtc(encoder, crtc); 893a796ba2cSSean Paul 8942f2eb723SRajesh Yadav /* Enable/restore vblank irq handling */ 8952f2eb723SRajesh Yadav drm_crtc_vblank_on(crtc); 89625fdd593SJeykumar Sankaran } 89725fdd593SJeykumar Sankaran 89825fdd593SJeykumar Sankaran struct plane_state { 89925fdd593SJeykumar Sankaran struct dpu_plane_state *dpu_pstate; 90025fdd593SJeykumar Sankaran const struct drm_plane_state *drm_pstate; 90125fdd593SJeykumar Sankaran int stage; 90225fdd593SJeykumar Sankaran u32 pipe_id; 90325fdd593SJeykumar Sankaran }; 90425fdd593SJeykumar Sankaran 90525fdd593SJeykumar Sankaran static int dpu_crtc_atomic_check(struct drm_crtc *crtc, 90625fdd593SJeykumar Sankaran struct drm_crtc_state *state) 90725fdd593SJeykumar Sankaran { 90825fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 90925fdd593SJeykumar Sankaran struct plane_state *pstates; 91025fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 91125fdd593SJeykumar Sankaran 91225fdd593SJeykumar Sankaran const struct drm_plane_state *pstate; 91325fdd593SJeykumar Sankaran struct drm_plane *plane; 91425fdd593SJeykumar Sankaran struct drm_display_mode *mode; 91525fdd593SJeykumar Sankaran 91625fdd593SJeykumar Sankaran int cnt = 0, rc = 0, mixer_width, i, z_pos; 91725fdd593SJeykumar Sankaran 91825fdd593SJeykumar Sankaran struct dpu_multirect_plane_states multirect_plane[DPU_STAGE_MAX * 2]; 91925fdd593SJeykumar Sankaran int multirect_count = 0; 92025fdd593SJeykumar Sankaran const struct drm_plane_state *pipe_staged[SSPP_MAX]; 92125fdd593SJeykumar Sankaran int left_zpos_cnt = 0, right_zpos_cnt = 0; 92225fdd593SJeykumar Sankaran struct drm_rect crtc_rect = { 0 }; 92325fdd593SJeykumar Sankaran 92425fdd593SJeykumar Sankaran if (!crtc) { 92525fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc\n"); 92625fdd593SJeykumar Sankaran return -EINVAL; 92725fdd593SJeykumar Sankaran } 92825fdd593SJeykumar Sankaran 92925fdd593SJeykumar Sankaran pstates = kzalloc(sizeof(*pstates) * DPU_STAGE_MAX * 4, GFP_KERNEL); 93025fdd593SJeykumar Sankaran 93125fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc); 93225fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(state); 93325fdd593SJeykumar Sankaran 93425fdd593SJeykumar Sankaran if (!state->enable || !state->active) { 93525fdd593SJeykumar Sankaran DPU_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n", 93625fdd593SJeykumar Sankaran crtc->base.id, state->enable, state->active); 93725fdd593SJeykumar Sankaran goto end; 93825fdd593SJeykumar Sankaran } 93925fdd593SJeykumar Sankaran 94025fdd593SJeykumar Sankaran mode = &state->adjusted_mode; 94125fdd593SJeykumar Sankaran DPU_DEBUG("%s: check", dpu_crtc->name); 94225fdd593SJeykumar Sankaran 94325fdd593SJeykumar Sankaran /* force a full mode set if active state changed */ 94425fdd593SJeykumar Sankaran if (state->active_changed) 94525fdd593SJeykumar Sankaran state->mode_changed = true; 94625fdd593SJeykumar Sankaran 94725fdd593SJeykumar Sankaran memset(pipe_staged, 0, sizeof(pipe_staged)); 94825fdd593SJeykumar Sankaran 9493804a982SJordan Crouse mixer_width = mode->hdisplay / cstate->num_mixers; 95025fdd593SJeykumar Sankaran 95125fdd593SJeykumar Sankaran _dpu_crtc_setup_lm_bounds(crtc, state); 95225fdd593SJeykumar Sankaran 95325fdd593SJeykumar Sankaran crtc_rect.x2 = mode->hdisplay; 95425fdd593SJeykumar Sankaran crtc_rect.y2 = mode->vdisplay; 95525fdd593SJeykumar Sankaran 95625fdd593SJeykumar Sankaran /* get plane state for all drm planes associated with crtc state */ 95725fdd593SJeykumar Sankaran drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { 95825fdd593SJeykumar Sankaran struct drm_rect dst, clip = crtc_rect; 95925fdd593SJeykumar Sankaran 96025fdd593SJeykumar Sankaran if (IS_ERR_OR_NULL(pstate)) { 96125fdd593SJeykumar Sankaran rc = PTR_ERR(pstate); 96225fdd593SJeykumar Sankaran DPU_ERROR("%s: failed to get plane%d state, %d\n", 96325fdd593SJeykumar Sankaran dpu_crtc->name, plane->base.id, rc); 96425fdd593SJeykumar Sankaran goto end; 96525fdd593SJeykumar Sankaran } 96625fdd593SJeykumar Sankaran if (cnt >= DPU_STAGE_MAX * 4) 96725fdd593SJeykumar Sankaran continue; 96825fdd593SJeykumar Sankaran 96925fdd593SJeykumar Sankaran pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate); 97025fdd593SJeykumar Sankaran pstates[cnt].drm_pstate = pstate; 97125fdd593SJeykumar Sankaran pstates[cnt].stage = pstate->normalized_zpos; 97225fdd593SJeykumar Sankaran pstates[cnt].pipe_id = dpu_plane_pipe(plane); 97325fdd593SJeykumar Sankaran 97425fdd593SJeykumar Sankaran if (pipe_staged[pstates[cnt].pipe_id]) { 97525fdd593SJeykumar Sankaran multirect_plane[multirect_count].r0 = 97625fdd593SJeykumar Sankaran pipe_staged[pstates[cnt].pipe_id]; 97725fdd593SJeykumar Sankaran multirect_plane[multirect_count].r1 = pstate; 97825fdd593SJeykumar Sankaran multirect_count++; 97925fdd593SJeykumar Sankaran 98025fdd593SJeykumar Sankaran pipe_staged[pstates[cnt].pipe_id] = NULL; 98125fdd593SJeykumar Sankaran } else { 98225fdd593SJeykumar Sankaran pipe_staged[pstates[cnt].pipe_id] = pstate; 98325fdd593SJeykumar Sankaran } 98425fdd593SJeykumar Sankaran 98525fdd593SJeykumar Sankaran cnt++; 98625fdd593SJeykumar Sankaran 98725fdd593SJeykumar Sankaran dst = drm_plane_state_dest(pstate); 98896fc56a7SSean Paul if (!drm_rect_intersect(&clip, &dst)) { 98925fdd593SJeykumar Sankaran DPU_ERROR("invalid vertical/horizontal destination\n"); 99025fdd593SJeykumar Sankaran DPU_ERROR("display: " DRM_RECT_FMT " plane: " 99125fdd593SJeykumar Sankaran DRM_RECT_FMT "\n", DRM_RECT_ARG(&crtc_rect), 99225fdd593SJeykumar Sankaran DRM_RECT_ARG(&dst)); 99325fdd593SJeykumar Sankaran rc = -E2BIG; 99425fdd593SJeykumar Sankaran goto end; 99525fdd593SJeykumar Sankaran } 99625fdd593SJeykumar Sankaran } 99725fdd593SJeykumar Sankaran 99825fdd593SJeykumar Sankaran for (i = 1; i < SSPP_MAX; i++) { 99925fdd593SJeykumar Sankaran if (pipe_staged[i]) { 100025fdd593SJeykumar Sankaran dpu_plane_clear_multirect(pipe_staged[i]); 100125fdd593SJeykumar Sankaran 100225fdd593SJeykumar Sankaran if (is_dpu_plane_virtual(pipe_staged[i]->plane)) { 100325fdd593SJeykumar Sankaran DPU_ERROR( 100425fdd593SJeykumar Sankaran "r1 only virt plane:%d not supported\n", 100525fdd593SJeykumar Sankaran pipe_staged[i]->plane->base.id); 100625fdd593SJeykumar Sankaran rc = -EINVAL; 100725fdd593SJeykumar Sankaran goto end; 100825fdd593SJeykumar Sankaran } 100925fdd593SJeykumar Sankaran } 101025fdd593SJeykumar Sankaran } 101125fdd593SJeykumar Sankaran 101225fdd593SJeykumar Sankaran z_pos = -1; 101325fdd593SJeykumar Sankaran for (i = 0; i < cnt; i++) { 101425fdd593SJeykumar Sankaran /* reset counts at every new blend stage */ 101525fdd593SJeykumar Sankaran if (pstates[i].stage != z_pos) { 101625fdd593SJeykumar Sankaran left_zpos_cnt = 0; 101725fdd593SJeykumar Sankaran right_zpos_cnt = 0; 101825fdd593SJeykumar Sankaran z_pos = pstates[i].stage; 101925fdd593SJeykumar Sankaran } 102025fdd593SJeykumar Sankaran 102125fdd593SJeykumar Sankaran /* verify z_pos setting before using it */ 102225fdd593SJeykumar Sankaran if (z_pos >= DPU_STAGE_MAX - DPU_STAGE_0) { 102325fdd593SJeykumar Sankaran DPU_ERROR("> %d plane stages assigned\n", 102425fdd593SJeykumar Sankaran DPU_STAGE_MAX - DPU_STAGE_0); 102525fdd593SJeykumar Sankaran rc = -EINVAL; 102625fdd593SJeykumar Sankaran goto end; 102725fdd593SJeykumar Sankaran } else if (pstates[i].drm_pstate->crtc_x < mixer_width) { 102825fdd593SJeykumar Sankaran if (left_zpos_cnt == 2) { 102925fdd593SJeykumar Sankaran DPU_ERROR("> 2 planes @ stage %d on left\n", 103025fdd593SJeykumar Sankaran z_pos); 103125fdd593SJeykumar Sankaran rc = -EINVAL; 103225fdd593SJeykumar Sankaran goto end; 103325fdd593SJeykumar Sankaran } 103425fdd593SJeykumar Sankaran left_zpos_cnt++; 103525fdd593SJeykumar Sankaran 103625fdd593SJeykumar Sankaran } else { 103725fdd593SJeykumar Sankaran if (right_zpos_cnt == 2) { 103825fdd593SJeykumar Sankaran DPU_ERROR("> 2 planes @ stage %d on right\n", 103925fdd593SJeykumar Sankaran z_pos); 104025fdd593SJeykumar Sankaran rc = -EINVAL; 104125fdd593SJeykumar Sankaran goto end; 104225fdd593SJeykumar Sankaran } 104325fdd593SJeykumar Sankaran right_zpos_cnt++; 104425fdd593SJeykumar Sankaran } 104525fdd593SJeykumar Sankaran 104625fdd593SJeykumar Sankaran pstates[i].dpu_pstate->stage = z_pos + DPU_STAGE_0; 104725fdd593SJeykumar Sankaran DPU_DEBUG("%s: zpos %d", dpu_crtc->name, z_pos); 104825fdd593SJeykumar Sankaran } 104925fdd593SJeykumar Sankaran 105025fdd593SJeykumar Sankaran for (i = 0; i < multirect_count; i++) { 105125fdd593SJeykumar Sankaran if (dpu_plane_validate_multirect_v2(&multirect_plane[i])) { 105225fdd593SJeykumar Sankaran DPU_ERROR( 105325fdd593SJeykumar Sankaran "multirect validation failed for planes (%d - %d)\n", 105425fdd593SJeykumar Sankaran multirect_plane[i].r0->plane->base.id, 105525fdd593SJeykumar Sankaran multirect_plane[i].r1->plane->base.id); 105625fdd593SJeykumar Sankaran rc = -EINVAL; 105725fdd593SJeykumar Sankaran goto end; 105825fdd593SJeykumar Sankaran } 105925fdd593SJeykumar Sankaran } 106025fdd593SJeykumar Sankaran 106125fdd593SJeykumar Sankaran rc = dpu_core_perf_crtc_check(crtc, state); 106225fdd593SJeykumar Sankaran if (rc) { 106325fdd593SJeykumar Sankaran DPU_ERROR("crtc%d failed performance check %d\n", 106425fdd593SJeykumar Sankaran crtc->base.id, rc); 106525fdd593SJeykumar Sankaran goto end; 106625fdd593SJeykumar Sankaran } 106725fdd593SJeykumar Sankaran 106825fdd593SJeykumar Sankaran /* validate source split: 106925fdd593SJeykumar Sankaran * use pstates sorted by stage to check planes on same stage 107025fdd593SJeykumar Sankaran * we assume that all pipes are in source split so its valid to compare 107125fdd593SJeykumar Sankaran * without taking into account left/right mixer placement 107225fdd593SJeykumar Sankaran */ 107325fdd593SJeykumar Sankaran for (i = 1; i < cnt; i++) { 107425fdd593SJeykumar Sankaran struct plane_state *prv_pstate, *cur_pstate; 107525fdd593SJeykumar Sankaran struct drm_rect left_rect, right_rect; 107625fdd593SJeykumar Sankaran int32_t left_pid, right_pid; 107725fdd593SJeykumar Sankaran int32_t stage; 107825fdd593SJeykumar Sankaran 107925fdd593SJeykumar Sankaran prv_pstate = &pstates[i - 1]; 108025fdd593SJeykumar Sankaran cur_pstate = &pstates[i]; 108125fdd593SJeykumar Sankaran if (prv_pstate->stage != cur_pstate->stage) 108225fdd593SJeykumar Sankaran continue; 108325fdd593SJeykumar Sankaran 108425fdd593SJeykumar Sankaran stage = cur_pstate->stage; 108525fdd593SJeykumar Sankaran 108625fdd593SJeykumar Sankaran left_pid = prv_pstate->dpu_pstate->base.plane->base.id; 108725fdd593SJeykumar Sankaran left_rect = drm_plane_state_dest(prv_pstate->drm_pstate); 108825fdd593SJeykumar Sankaran 108925fdd593SJeykumar Sankaran right_pid = cur_pstate->dpu_pstate->base.plane->base.id; 109025fdd593SJeykumar Sankaran right_rect = drm_plane_state_dest(cur_pstate->drm_pstate); 109125fdd593SJeykumar Sankaran 109225fdd593SJeykumar Sankaran if (right_rect.x1 < left_rect.x1) { 109325fdd593SJeykumar Sankaran swap(left_pid, right_pid); 109425fdd593SJeykumar Sankaran swap(left_rect, right_rect); 109525fdd593SJeykumar Sankaran } 109625fdd593SJeykumar Sankaran 109725fdd593SJeykumar Sankaran /** 109825fdd593SJeykumar Sankaran * - planes are enumerated in pipe-priority order such that 109925fdd593SJeykumar Sankaran * planes with lower drm_id must be left-most in a shared 110025fdd593SJeykumar Sankaran * blend-stage when using source split. 110125fdd593SJeykumar Sankaran * - planes in source split must be contiguous in width 110225fdd593SJeykumar Sankaran * - planes in source split must have same dest yoff and height 110325fdd593SJeykumar Sankaran */ 110425fdd593SJeykumar Sankaran if (right_pid < left_pid) { 110525fdd593SJeykumar Sankaran DPU_ERROR( 110625fdd593SJeykumar Sankaran "invalid src split cfg. priority mismatch. stage: %d left: %d right: %d\n", 110725fdd593SJeykumar Sankaran stage, left_pid, right_pid); 110825fdd593SJeykumar Sankaran rc = -EINVAL; 110925fdd593SJeykumar Sankaran goto end; 111025fdd593SJeykumar Sankaran } else if (right_rect.x1 != drm_rect_width(&left_rect)) { 111125fdd593SJeykumar Sankaran DPU_ERROR("non-contiguous coordinates for src split. " 111225fdd593SJeykumar Sankaran "stage: %d left: " DRM_RECT_FMT " right: " 111325fdd593SJeykumar Sankaran DRM_RECT_FMT "\n", stage, 111425fdd593SJeykumar Sankaran DRM_RECT_ARG(&left_rect), 111525fdd593SJeykumar Sankaran DRM_RECT_ARG(&right_rect)); 111625fdd593SJeykumar Sankaran rc = -EINVAL; 111725fdd593SJeykumar Sankaran goto end; 111825fdd593SJeykumar Sankaran } else if (left_rect.y1 != right_rect.y1 || 111925fdd593SJeykumar Sankaran drm_rect_height(&left_rect) != drm_rect_height(&right_rect)) { 112025fdd593SJeykumar Sankaran DPU_ERROR("source split at stage: %d. invalid " 112125fdd593SJeykumar Sankaran "yoff/height: left: " DRM_RECT_FMT " right: " 112225fdd593SJeykumar Sankaran DRM_RECT_FMT "\n", stage, 112325fdd593SJeykumar Sankaran DRM_RECT_ARG(&left_rect), 112425fdd593SJeykumar Sankaran DRM_RECT_ARG(&right_rect)); 112525fdd593SJeykumar Sankaran rc = -EINVAL; 112625fdd593SJeykumar Sankaran goto end; 112725fdd593SJeykumar Sankaran } 112825fdd593SJeykumar Sankaran } 112925fdd593SJeykumar Sankaran 113025fdd593SJeykumar Sankaran end: 113125fdd593SJeykumar Sankaran kfree(pstates); 113225fdd593SJeykumar Sankaran return rc; 113325fdd593SJeykumar Sankaran } 113425fdd593SJeykumar Sankaran 113525fdd593SJeykumar Sankaran int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) 113625fdd593SJeykumar Sankaran { 11377a007a12SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 1138a796ba2cSSean Paul struct drm_encoder *enc; 1139a796ba2cSSean Paul 1140a796ba2cSSean Paul trace_dpu_crtc_vblank(DRMID(&dpu_crtc->base), en, dpu_crtc); 1141a796ba2cSSean Paul 1142a796ba2cSSean Paul /* 1143a796ba2cSSean Paul * Normally we would iterate through encoder_mask in crtc state to find 1144a796ba2cSSean Paul * attached encoders. In this case, we might be disabling vblank _after_ 1145a796ba2cSSean Paul * encoder_mask has been cleared. 1146a796ba2cSSean Paul * 1147a796ba2cSSean Paul * Instead, we "assign" a crtc to the encoder in enable and clear it in 1148a796ba2cSSean Paul * disable (which is also after encoder_mask is cleared). So instead of 1149a796ba2cSSean Paul * using encoder mask, we'll ask the encoder to toggle itself iff it's 1150a796ba2cSSean Paul * currently assigned to our crtc. 1151a796ba2cSSean Paul * 1152a796ba2cSSean Paul * Note also that this function cannot be called while crtc is disabled 1153a796ba2cSSean Paul * since we use drm_crtc_vblank_on/off. So we don't need to worry 1154a796ba2cSSean Paul * about the assigned crtcs being inconsistent with the current state 1155a796ba2cSSean Paul * (which means no need to worry about modeset locks). 1156a796ba2cSSean Paul */ 1157a796ba2cSSean Paul list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) { 1158a796ba2cSSean Paul trace_dpu_crtc_vblank_enable(DRMID(crtc), DRMID(enc), en, 1159a796ba2cSSean Paul dpu_crtc); 1160a796ba2cSSean Paul 1161a796ba2cSSean Paul dpu_encoder_toggle_vblank_for_crtc(enc, crtc, en); 1162a796ba2cSSean Paul } 116325fdd593SJeykumar Sankaran 116425fdd593SJeykumar Sankaran return 0; 116525fdd593SJeykumar Sankaran } 116625fdd593SJeykumar Sankaran 116725fdd593SJeykumar Sankaran #ifdef CONFIG_DEBUG_FS 116825fdd593SJeykumar Sankaran static int _dpu_debugfs_status_show(struct seq_file *s, void *data) 116925fdd593SJeykumar Sankaran { 117025fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc; 117125fdd593SJeykumar Sankaran struct dpu_plane_state *pstate = NULL; 117225fdd593SJeykumar Sankaran struct dpu_crtc_mixer *m; 117325fdd593SJeykumar Sankaran 117425fdd593SJeykumar Sankaran struct drm_crtc *crtc; 117525fdd593SJeykumar Sankaran struct drm_plane *plane; 117625fdd593SJeykumar Sankaran struct drm_display_mode *mode; 117725fdd593SJeykumar Sankaran struct drm_framebuffer *fb; 117825fdd593SJeykumar Sankaran struct drm_plane_state *state; 117925fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate; 118025fdd593SJeykumar Sankaran 118125fdd593SJeykumar Sankaran int i, out_width; 118225fdd593SJeykumar Sankaran 118325fdd593SJeykumar Sankaran dpu_crtc = s->private; 118425fdd593SJeykumar Sankaran crtc = &dpu_crtc->base; 11859222cdd2SJeykumar Sankaran 11869222cdd2SJeykumar Sankaran drm_modeset_lock_all(crtc->dev); 118725fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(crtc->state); 118825fdd593SJeykumar Sankaran 118925fdd593SJeykumar Sankaran mode = &crtc->state->adjusted_mode; 11903804a982SJordan Crouse out_width = mode->hdisplay / cstate->num_mixers; 119125fdd593SJeykumar Sankaran 119225fdd593SJeykumar Sankaran seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id, 119325fdd593SJeykumar Sankaran mode->hdisplay, mode->vdisplay); 119425fdd593SJeykumar Sankaran 119525fdd593SJeykumar Sankaran seq_puts(s, "\n"); 119625fdd593SJeykumar Sankaran 11979222cdd2SJeykumar Sankaran for (i = 0; i < cstate->num_mixers; ++i) { 11989222cdd2SJeykumar Sankaran m = &cstate->mixers[i]; 119925fdd593SJeykumar Sankaran if (!m->hw_lm) 120025fdd593SJeykumar Sankaran seq_printf(s, "\tmixer[%d] has no lm\n", i); 1201cf6916f4SJeykumar Sankaran else if (!m->lm_ctl) 120225fdd593SJeykumar Sankaran seq_printf(s, "\tmixer[%d] has no ctl\n", i); 120325fdd593SJeykumar Sankaran else 120425fdd593SJeykumar Sankaran seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n", 1205cf6916f4SJeykumar Sankaran m->hw_lm->idx - LM_0, m->lm_ctl->idx - CTL_0, 120625fdd593SJeykumar Sankaran out_width, mode->vdisplay); 120725fdd593SJeykumar Sankaran } 120825fdd593SJeykumar Sankaran 120925fdd593SJeykumar Sankaran seq_puts(s, "\n"); 121025fdd593SJeykumar Sankaran 121125fdd593SJeykumar Sankaran drm_atomic_crtc_for_each_plane(plane, crtc) { 121225fdd593SJeykumar Sankaran pstate = to_dpu_plane_state(plane->state); 121325fdd593SJeykumar Sankaran state = plane->state; 121425fdd593SJeykumar Sankaran 121525fdd593SJeykumar Sankaran if (!pstate || !state) 121625fdd593SJeykumar Sankaran continue; 121725fdd593SJeykumar Sankaran 121825fdd593SJeykumar Sankaran seq_printf(s, "\tplane:%u stage:%d\n", plane->base.id, 121925fdd593SJeykumar Sankaran pstate->stage); 122025fdd593SJeykumar Sankaran 122125fdd593SJeykumar Sankaran if (plane->state->fb) { 122225fdd593SJeykumar Sankaran fb = plane->state->fb; 122325fdd593SJeykumar Sankaran 122425fdd593SJeykumar Sankaran seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u ", 122525fdd593SJeykumar Sankaran fb->base.id, (char *) &fb->format->format, 122625fdd593SJeykumar Sankaran fb->width, fb->height); 122725fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(fb->format->cpp); ++i) 122825fdd593SJeykumar Sankaran seq_printf(s, "cpp[%d]:%u ", 122925fdd593SJeykumar Sankaran i, fb->format->cpp[i]); 123025fdd593SJeykumar Sankaran seq_puts(s, "\n\t"); 123125fdd593SJeykumar Sankaran 123225fdd593SJeykumar Sankaran seq_printf(s, "modifier:%8llu ", fb->modifier); 123325fdd593SJeykumar Sankaran seq_puts(s, "\n"); 123425fdd593SJeykumar Sankaran 123525fdd593SJeykumar Sankaran seq_puts(s, "\t"); 123625fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) 123725fdd593SJeykumar Sankaran seq_printf(s, "pitches[%d]:%8u ", i, 123825fdd593SJeykumar Sankaran fb->pitches[i]); 123925fdd593SJeykumar Sankaran seq_puts(s, "\n"); 124025fdd593SJeykumar Sankaran 124125fdd593SJeykumar Sankaran seq_puts(s, "\t"); 124225fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) 124325fdd593SJeykumar Sankaran seq_printf(s, "offsets[%d]:%8u ", i, 124425fdd593SJeykumar Sankaran fb->offsets[i]); 124525fdd593SJeykumar Sankaran seq_puts(s, "\n"); 124625fdd593SJeykumar Sankaran } 124725fdd593SJeykumar Sankaran 124825fdd593SJeykumar Sankaran seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n", 124925fdd593SJeykumar Sankaran state->src_x, state->src_y, state->src_w, state->src_h); 125025fdd593SJeykumar Sankaran 125125fdd593SJeykumar Sankaran seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", 125225fdd593SJeykumar Sankaran state->crtc_x, state->crtc_y, state->crtc_w, 125325fdd593SJeykumar Sankaran state->crtc_h); 125425fdd593SJeykumar Sankaran seq_printf(s, "\tmultirect: mode: %d index: %d\n", 125525fdd593SJeykumar Sankaran pstate->multirect_mode, pstate->multirect_index); 125625fdd593SJeykumar Sankaran 125725fdd593SJeykumar Sankaran seq_puts(s, "\n"); 125825fdd593SJeykumar Sankaran } 125925fdd593SJeykumar Sankaran if (dpu_crtc->vblank_cb_count) { 126025fdd593SJeykumar Sankaran ktime_t diff = ktime_sub(ktime_get(), dpu_crtc->vblank_cb_time); 126125fdd593SJeykumar Sankaran s64 diff_ms = ktime_to_ms(diff); 126225fdd593SJeykumar Sankaran s64 fps = diff_ms ? div_s64( 126325fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_count * 1000, diff_ms) : 0; 126425fdd593SJeykumar Sankaran 126525fdd593SJeykumar Sankaran seq_printf(s, 126625fdd593SJeykumar Sankaran "vblank fps:%lld count:%u total:%llums total_framecount:%llu\n", 126725fdd593SJeykumar Sankaran fps, dpu_crtc->vblank_cb_count, 126825fdd593SJeykumar Sankaran ktime_to_ms(diff), dpu_crtc->play_count); 126925fdd593SJeykumar Sankaran 127025fdd593SJeykumar Sankaran /* reset time & count for next measurement */ 127125fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_count = 0; 127225fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_time = ktime_set(0, 0); 127325fdd593SJeykumar Sankaran } 127425fdd593SJeykumar Sankaran 12759222cdd2SJeykumar Sankaran drm_modeset_unlock_all(crtc->dev); 127625fdd593SJeykumar Sankaran 127725fdd593SJeykumar Sankaran return 0; 127825fdd593SJeykumar Sankaran } 127925fdd593SJeykumar Sankaran 128025fdd593SJeykumar Sankaran static int _dpu_debugfs_status_open(struct inode *inode, struct file *file) 128125fdd593SJeykumar Sankaran { 128225fdd593SJeykumar Sankaran return single_open(file, _dpu_debugfs_status_show, inode->i_private); 128325fdd593SJeykumar Sankaran } 128425fdd593SJeykumar Sankaran 128525fdd593SJeykumar Sankaran #define DEFINE_DPU_DEBUGFS_SEQ_FOPS(__prefix) \ 128625fdd593SJeykumar Sankaran static int __prefix ## _open(struct inode *inode, struct file *file) \ 128725fdd593SJeykumar Sankaran { \ 128825fdd593SJeykumar Sankaran return single_open(file, __prefix ## _show, inode->i_private); \ 128925fdd593SJeykumar Sankaran } \ 129025fdd593SJeykumar Sankaran static const struct file_operations __prefix ## _fops = { \ 129125fdd593SJeykumar Sankaran .owner = THIS_MODULE, \ 129225fdd593SJeykumar Sankaran .open = __prefix ## _open, \ 129325fdd593SJeykumar Sankaran .release = single_release, \ 129425fdd593SJeykumar Sankaran .read = seq_read, \ 129525fdd593SJeykumar Sankaran .llseek = seq_lseek, \ 129625fdd593SJeykumar Sankaran } 129725fdd593SJeykumar Sankaran 129825fdd593SJeykumar Sankaran static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v) 129925fdd593SJeykumar Sankaran { 130025fdd593SJeykumar Sankaran struct drm_crtc *crtc = (struct drm_crtc *) s->private; 130125fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 130225fdd593SJeykumar Sankaran int i; 130325fdd593SJeykumar Sankaran 130425fdd593SJeykumar Sankaran seq_printf(s, "client type: %d\n", dpu_crtc_get_client_type(crtc)); 130525fdd593SJeykumar Sankaran seq_printf(s, "intf_mode: %d\n", dpu_crtc_get_intf_mode(crtc)); 130625fdd593SJeykumar Sankaran seq_printf(s, "core_clk_rate: %llu\n", 130725fdd593SJeykumar Sankaran dpu_crtc->cur_perf.core_clk_rate); 1308aeb7b49aSSean Paul for (i = DPU_CORE_PERF_DATA_BUS_ID_MNOC; 1309aeb7b49aSSean Paul i < DPU_CORE_PERF_DATA_BUS_ID_MAX; i++) { 13105e1228d7SSean Paul seq_printf(s, "bw_ctl[%d]: %llu\n", i, 131125fdd593SJeykumar Sankaran dpu_crtc->cur_perf.bw_ctl[i]); 13125e1228d7SSean Paul seq_printf(s, "max_per_pipe_ib[%d]: %llu\n", i, 131325fdd593SJeykumar Sankaran dpu_crtc->cur_perf.max_per_pipe_ib[i]); 131425fdd593SJeykumar Sankaran } 131525fdd593SJeykumar Sankaran 131625fdd593SJeykumar Sankaran return 0; 131725fdd593SJeykumar Sankaran } 131825fdd593SJeykumar Sankaran DEFINE_DPU_DEBUGFS_SEQ_FOPS(dpu_crtc_debugfs_state); 131925fdd593SJeykumar Sankaran 132025fdd593SJeykumar Sankaran static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc) 132125fdd593SJeykumar Sankaran { 13223d688410SJordan Crouse struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 132325fdd593SJeykumar Sankaran 132425fdd593SJeykumar Sankaran static const struct file_operations debugfs_status_fops = { 132525fdd593SJeykumar Sankaran .open = _dpu_debugfs_status_open, 132625fdd593SJeykumar Sankaran .read = seq_read, 132725fdd593SJeykumar Sankaran .llseek = seq_lseek, 132825fdd593SJeykumar Sankaran .release = single_release, 132925fdd593SJeykumar Sankaran }; 133025fdd593SJeykumar Sankaran 133125fdd593SJeykumar Sankaran dpu_crtc->debugfs_root = debugfs_create_dir(dpu_crtc->name, 133225fdd593SJeykumar Sankaran crtc->dev->primary->debugfs_root); 133325fdd593SJeykumar Sankaran if (!dpu_crtc->debugfs_root) 133425fdd593SJeykumar Sankaran return -ENOMEM; 133525fdd593SJeykumar Sankaran 133625fdd593SJeykumar Sankaran /* don't error check these */ 133725fdd593SJeykumar Sankaran debugfs_create_file("status", 0400, 133825fdd593SJeykumar Sankaran dpu_crtc->debugfs_root, 133925fdd593SJeykumar Sankaran dpu_crtc, &debugfs_status_fops); 134025fdd593SJeykumar Sankaran debugfs_create_file("state", 0600, 134125fdd593SJeykumar Sankaran dpu_crtc->debugfs_root, 134225fdd593SJeykumar Sankaran &dpu_crtc->base, 134325fdd593SJeykumar Sankaran &dpu_crtc_debugfs_state_fops); 134425fdd593SJeykumar Sankaran 134525fdd593SJeykumar Sankaran return 0; 134625fdd593SJeykumar Sankaran } 134725fdd593SJeykumar Sankaran #else 134825fdd593SJeykumar Sankaran static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc) 134925fdd593SJeykumar Sankaran { 135025fdd593SJeykumar Sankaran return 0; 135125fdd593SJeykumar Sankaran } 135225fdd593SJeykumar Sankaran #endif /* CONFIG_DEBUG_FS */ 135325fdd593SJeykumar Sankaran 135425fdd593SJeykumar Sankaran static int dpu_crtc_late_register(struct drm_crtc *crtc) 135525fdd593SJeykumar Sankaran { 135625fdd593SJeykumar Sankaran return _dpu_crtc_init_debugfs(crtc); 135725fdd593SJeykumar Sankaran } 135825fdd593SJeykumar Sankaran 135925fdd593SJeykumar Sankaran static void dpu_crtc_early_unregister(struct drm_crtc *crtc) 136025fdd593SJeykumar Sankaran { 13613d688410SJordan Crouse struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc); 13623d688410SJordan Crouse 13633d688410SJordan Crouse debugfs_remove_recursive(dpu_crtc->debugfs_root); 136425fdd593SJeykumar Sankaran } 136525fdd593SJeykumar Sankaran 136625fdd593SJeykumar Sankaran static const struct drm_crtc_funcs dpu_crtc_funcs = { 136725fdd593SJeykumar Sankaran .set_config = drm_atomic_helper_set_config, 136825fdd593SJeykumar Sankaran .destroy = dpu_crtc_destroy, 136925fdd593SJeykumar Sankaran .page_flip = drm_atomic_helper_page_flip, 1370ff5952a7SSean Paul .reset = dpu_crtc_reset, 137125fdd593SJeykumar Sankaran .atomic_duplicate_state = dpu_crtc_duplicate_state, 137225fdd593SJeykumar Sankaran .atomic_destroy_state = dpu_crtc_destroy_state, 137325fdd593SJeykumar Sankaran .late_register = dpu_crtc_late_register, 137425fdd593SJeykumar Sankaran .early_unregister = dpu_crtc_early_unregister, 137525fdd593SJeykumar Sankaran }; 137625fdd593SJeykumar Sankaran 137725fdd593SJeykumar Sankaran static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = { 1378f7aafc8dSSean Paul .atomic_disable = dpu_crtc_disable, 137925fdd593SJeykumar Sankaran .atomic_enable = dpu_crtc_enable, 138025fdd593SJeykumar Sankaran .atomic_check = dpu_crtc_atomic_check, 138125fdd593SJeykumar Sankaran .atomic_begin = dpu_crtc_atomic_begin, 138225fdd593SJeykumar Sankaran .atomic_flush = dpu_crtc_atomic_flush, 138325fdd593SJeykumar Sankaran }; 138425fdd593SJeykumar Sankaran 138525fdd593SJeykumar Sankaran /* initialize crtc */ 138607ca1fc0SSravanthi Kollukuduru struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane, 138707ca1fc0SSravanthi Kollukuduru struct drm_plane *cursor) 138825fdd593SJeykumar Sankaran { 138925fdd593SJeykumar Sankaran struct drm_crtc *crtc = NULL; 139025fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = NULL; 139125fdd593SJeykumar Sankaran struct msm_drm_private *priv = NULL; 139225fdd593SJeykumar Sankaran struct dpu_kms *kms = NULL; 1393c17aeda0SJordan Crouse int i; 139425fdd593SJeykumar Sankaran 139525fdd593SJeykumar Sankaran priv = dev->dev_private; 139625fdd593SJeykumar Sankaran kms = to_dpu_kms(priv->kms); 139725fdd593SJeykumar Sankaran 139825fdd593SJeykumar Sankaran dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL); 139925fdd593SJeykumar Sankaran if (!dpu_crtc) 140025fdd593SJeykumar Sankaran return ERR_PTR(-ENOMEM); 140125fdd593SJeykumar Sankaran 140225fdd593SJeykumar Sankaran crtc = &dpu_crtc->base; 140325fdd593SJeykumar Sankaran crtc->dev = dev; 140425fdd593SJeykumar Sankaran 140525fdd593SJeykumar Sankaran spin_lock_init(&dpu_crtc->spin_lock); 140625fdd593SJeykumar Sankaran atomic_set(&dpu_crtc->frame_pending, 0); 140725fdd593SJeykumar Sankaran 140825fdd593SJeykumar Sankaran init_completion(&dpu_crtc->frame_done_comp); 140925fdd593SJeykumar Sankaran 141025fdd593SJeykumar Sankaran INIT_LIST_HEAD(&dpu_crtc->frame_event_list); 141125fdd593SJeykumar Sankaran 141225fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(dpu_crtc->frame_events); i++) { 141325fdd593SJeykumar Sankaran INIT_LIST_HEAD(&dpu_crtc->frame_events[i].list); 141425fdd593SJeykumar Sankaran list_add(&dpu_crtc->frame_events[i].list, 141525fdd593SJeykumar Sankaran &dpu_crtc->frame_event_list); 141625fdd593SJeykumar Sankaran kthread_init_work(&dpu_crtc->frame_events[i].work, 141725fdd593SJeykumar Sankaran dpu_crtc_frame_event_work); 141825fdd593SJeykumar Sankaran } 141925fdd593SJeykumar Sankaran 142007ca1fc0SSravanthi Kollukuduru drm_crtc_init_with_planes(dev, crtc, plane, cursor, &dpu_crtc_funcs, 142125fdd593SJeykumar Sankaran NULL); 142225fdd593SJeykumar Sankaran 142325fdd593SJeykumar Sankaran drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs); 142425fdd593SJeykumar Sankaran plane->crtc = crtc; 142525fdd593SJeykumar Sankaran 142625fdd593SJeykumar Sankaran /* save user friendly CRTC name for later */ 142725fdd593SJeykumar Sankaran snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id); 142825fdd593SJeykumar Sankaran 142925fdd593SJeykumar Sankaran /* initialize event handling */ 1430c17aeda0SJordan Crouse spin_lock_init(&dpu_crtc->event_lock); 143125fdd593SJeykumar Sankaran 143225fdd593SJeykumar Sankaran DPU_DEBUG("%s: successfully initialized crtc\n", dpu_crtc->name); 143325fdd593SJeykumar Sankaran return crtc; 143425fdd593SJeykumar Sankaran } 1435