1caab277bSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
225fdd593SJeykumar Sankaran /*
3*173b2472SJessica Zhang * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
478d9b458SJessica Zhang * Copyright (c) 2014-2021 The Linux Foundation. All rights reserved.
525fdd593SJeykumar Sankaran * Copyright (C) 2013 Red Hat
625fdd593SJeykumar Sankaran * Author: Rob Clark <robdclark@gmail.com>
725fdd593SJeykumar Sankaran */
825fdd593SJeykumar Sankaran
925fdd593SJeykumar Sankaran #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
1025fdd593SJeykumar Sankaran #include <linux/sort.h>
1125fdd593SJeykumar Sankaran #include <linux/debugfs.h>
1225fdd593SJeykumar Sankaran #include <linux/ktime.h>
134259ff7aSKalyan Thota #include <linux/bits.h>
14feea39a8SSam Ravnborg
15351f950dSMaxime Ripard #include <drm/drm_atomic.h>
1690bb087fSVille Syrjälä #include <drm/drm_blend.h>
1725fdd593SJeykumar Sankaran #include <drm/drm_crtc.h>
1825fdd593SJeykumar Sankaran #include <drm/drm_flip_work.h>
19720cf96dSVille Syrjälä #include <drm/drm_framebuffer.h>
20fcd70cd3SDaniel Vetter #include <drm/drm_mode.h>
21fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h>
2225fdd593SJeykumar Sankaran #include <drm/drm_rect.h>
23feea39a8SSam Ravnborg #include <drm/drm_vblank.h>
2411226978SVinod Polimera #include <drm/drm_self_refresh_helper.h>
2525fdd593SJeykumar Sankaran
2625fdd593SJeykumar Sankaran #include "dpu_kms.h"
2725fdd593SJeykumar Sankaran #include "dpu_hw_lm.h"
2825fdd593SJeykumar Sankaran #include "dpu_hw_ctl.h"
294259ff7aSKalyan Thota #include "dpu_hw_dspp.h"
3025fdd593SJeykumar Sankaran #include "dpu_crtc.h"
3125fdd593SJeykumar Sankaran #include "dpu_plane.h"
3225fdd593SJeykumar Sankaran #include "dpu_encoder.h"
3325fdd593SJeykumar Sankaran #include "dpu_vbif.h"
3425fdd593SJeykumar Sankaran #include "dpu_core_perf.h"
3525fdd593SJeykumar Sankaran #include "dpu_trace.h"
3625fdd593SJeykumar Sankaran
3725fdd593SJeykumar Sankaran /* layer mixer index on dpu_crtc */
3825fdd593SJeykumar Sankaran #define LEFT_MIXER 0
3925fdd593SJeykumar Sankaran #define RIGHT_MIXER 1
4025fdd593SJeykumar Sankaran
4170df9610SSean Paul /* timeout in ms waiting for frame done */
4270df9610SSean Paul #define DPU_CRTC_FRAME_DONE_TIMEOUT_MS 60
4370df9610SSean Paul
444259ff7aSKalyan Thota #define CONVERT_S3_15(val) \
454259ff7aSKalyan Thota (((((u64)val) & ~BIT_ULL(63)) >> 17) & GENMASK_ULL(17, 0))
464259ff7aSKalyan Thota
_dpu_crtc_get_kms(struct drm_crtc * crtc)4758fba464SSean Paul static struct dpu_kms *_dpu_crtc_get_kms(struct drm_crtc *crtc)
4825fdd593SJeykumar Sankaran {
4904b96b63SBruce Wang struct msm_drm_private *priv = crtc->dev->dev_private;
5025fdd593SJeykumar Sankaran
5125fdd593SJeykumar Sankaran return to_dpu_kms(priv->kms);
5225fdd593SJeykumar Sankaran }
5325fdd593SJeykumar Sankaran
dpu_crtc_destroy(struct drm_crtc * crtc)5425fdd593SJeykumar Sankaran static void dpu_crtc_destroy(struct drm_crtc *crtc)
5525fdd593SJeykumar Sankaran {
5625fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
5725fdd593SJeykumar Sankaran
5825fdd593SJeykumar Sankaran if (!crtc)
5925fdd593SJeykumar Sankaran return;
6025fdd593SJeykumar Sankaran
6125fdd593SJeykumar Sankaran drm_crtc_cleanup(crtc);
6225fdd593SJeykumar Sankaran kfree(dpu_crtc);
6325fdd593SJeykumar Sankaran }
6425fdd593SJeykumar Sankaran
get_encoder_from_crtc(struct drm_crtc * crtc)6573743e72SKalyan Thota static struct drm_encoder *get_encoder_from_crtc(struct drm_crtc *crtc)
6673743e72SKalyan Thota {
6773743e72SKalyan Thota struct drm_device *dev = crtc->dev;
6873743e72SKalyan Thota struct drm_encoder *encoder;
6973743e72SKalyan Thota
7073743e72SKalyan Thota drm_for_each_encoder(encoder, dev)
7173743e72SKalyan Thota if (encoder->crtc == crtc)
7273743e72SKalyan Thota return encoder;
7373743e72SKalyan Thota
7473743e72SKalyan Thota return NULL;
7573743e72SKalyan Thota }
7673743e72SKalyan Thota
dpu_crtc_parse_crc_source(const char * src_name)7778d9b458SJessica Zhang static enum dpu_crtc_crc_source dpu_crtc_parse_crc_source(const char *src_name)
7878d9b458SJessica Zhang {
7978d9b458SJessica Zhang if (!src_name ||
8078d9b458SJessica Zhang !strcmp(src_name, "none"))
8178d9b458SJessica Zhang return DPU_CRTC_CRC_SOURCE_NONE;
8278d9b458SJessica Zhang if (!strcmp(src_name, "auto") ||
8378d9b458SJessica Zhang !strcmp(src_name, "lm"))
8478d9b458SJessica Zhang return DPU_CRTC_CRC_SOURCE_LAYER_MIXER;
85b1665047SJessica Zhang if (!strcmp(src_name, "encoder"))
86b1665047SJessica Zhang return DPU_CRTC_CRC_SOURCE_ENCODER;
8778d9b458SJessica Zhang
8878d9b458SJessica Zhang return DPU_CRTC_CRC_SOURCE_INVALID;
8978d9b458SJessica Zhang }
9078d9b458SJessica Zhang
dpu_crtc_verify_crc_source(struct drm_crtc * crtc,const char * src_name,size_t * values_cnt)9178d9b458SJessica Zhang static int dpu_crtc_verify_crc_source(struct drm_crtc *crtc,
9278d9b458SJessica Zhang const char *src_name, size_t *values_cnt)
9378d9b458SJessica Zhang {
9478d9b458SJessica Zhang enum dpu_crtc_crc_source source = dpu_crtc_parse_crc_source(src_name);
9578d9b458SJessica Zhang struct dpu_crtc_state *crtc_state = to_dpu_crtc_state(crtc->state);
9678d9b458SJessica Zhang
9778d9b458SJessica Zhang if (source < 0) {
9878d9b458SJessica Zhang DRM_DEBUG_DRIVER("Invalid source %s for CRTC%d\n", src_name, crtc->index);
9978d9b458SJessica Zhang return -EINVAL;
10078d9b458SJessica Zhang }
10178d9b458SJessica Zhang
102b1665047SJessica Zhang if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER) {
10378d9b458SJessica Zhang *values_cnt = crtc_state->num_mixers;
104b1665047SJessica Zhang } else if (source == DPU_CRTC_CRC_SOURCE_ENCODER) {
105b1665047SJessica Zhang struct drm_encoder *drm_enc;
106b1665047SJessica Zhang
107b1665047SJessica Zhang *values_cnt = 0;
108b1665047SJessica Zhang
109b1665047SJessica Zhang drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask)
110b1665047SJessica Zhang *values_cnt += dpu_encoder_get_crc_values_cnt(drm_enc);
111b1665047SJessica Zhang }
11278d9b458SJessica Zhang
11378d9b458SJessica Zhang return 0;
11478d9b458SJessica Zhang }
11578d9b458SJessica Zhang
dpu_crtc_setup_lm_misr(struct dpu_crtc_state * crtc_state)11658fc5d18SJessica Zhang static void dpu_crtc_setup_lm_misr(struct dpu_crtc_state *crtc_state)
11758fc5d18SJessica Zhang {
11858fc5d18SJessica Zhang struct dpu_crtc_mixer *m;
11958fc5d18SJessica Zhang int i;
12058fc5d18SJessica Zhang
12158fc5d18SJessica Zhang for (i = 0; i < crtc_state->num_mixers; ++i) {
12258fc5d18SJessica Zhang m = &crtc_state->mixers[i];
12358fc5d18SJessica Zhang
12458fc5d18SJessica Zhang if (!m->hw_lm || !m->hw_lm->ops.setup_misr)
12558fc5d18SJessica Zhang continue;
12658fc5d18SJessica Zhang
12758fc5d18SJessica Zhang /* Calculate MISR over 1 frame */
128*173b2472SJessica Zhang m->hw_lm->ops.setup_misr(m->hw_lm);
12958fc5d18SJessica Zhang }
13058fc5d18SJessica Zhang }
13158fc5d18SJessica Zhang
dpu_crtc_setup_encoder_misr(struct drm_crtc * crtc)132b1665047SJessica Zhang static void dpu_crtc_setup_encoder_misr(struct drm_crtc *crtc)
133b1665047SJessica Zhang {
134b1665047SJessica Zhang struct drm_encoder *drm_enc;
135b1665047SJessica Zhang
136b1665047SJessica Zhang drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask)
137b1665047SJessica Zhang dpu_encoder_setup_misr(drm_enc);
138b1665047SJessica Zhang }
139b1665047SJessica Zhang
dpu_crtc_set_crc_source(struct drm_crtc * crtc,const char * src_name)14078d9b458SJessica Zhang static int dpu_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
14178d9b458SJessica Zhang {
14278d9b458SJessica Zhang enum dpu_crtc_crc_source source = dpu_crtc_parse_crc_source(src_name);
14378d9b458SJessica Zhang enum dpu_crtc_crc_source current_source;
14478d9b458SJessica Zhang struct dpu_crtc_state *crtc_state;
14578d9b458SJessica Zhang struct drm_device *drm_dev = crtc->dev;
14678d9b458SJessica Zhang
14778d9b458SJessica Zhang bool was_enabled;
14878d9b458SJessica Zhang bool enable = false;
14958fc5d18SJessica Zhang int ret = 0;
15078d9b458SJessica Zhang
15178d9b458SJessica Zhang if (source < 0) {
15278d9b458SJessica Zhang DRM_DEBUG_DRIVER("Invalid CRC source %s for CRTC%d\n", src_name, crtc->index);
15378d9b458SJessica Zhang return -EINVAL;
15478d9b458SJessica Zhang }
15578d9b458SJessica Zhang
15678d9b458SJessica Zhang ret = drm_modeset_lock(&crtc->mutex, NULL);
15778d9b458SJessica Zhang
15878d9b458SJessica Zhang if (ret)
15978d9b458SJessica Zhang return ret;
16078d9b458SJessica Zhang
16178d9b458SJessica Zhang enable = (source != DPU_CRTC_CRC_SOURCE_NONE);
16278d9b458SJessica Zhang crtc_state = to_dpu_crtc_state(crtc->state);
16378d9b458SJessica Zhang
16478d9b458SJessica Zhang spin_lock_irq(&drm_dev->event_lock);
16578d9b458SJessica Zhang current_source = crtc_state->crc_source;
16678d9b458SJessica Zhang spin_unlock_irq(&drm_dev->event_lock);
16778d9b458SJessica Zhang
16878d9b458SJessica Zhang was_enabled = (current_source != DPU_CRTC_CRC_SOURCE_NONE);
16978d9b458SJessica Zhang
17078d9b458SJessica Zhang if (!was_enabled && enable) {
17178d9b458SJessica Zhang ret = drm_crtc_vblank_get(crtc);
17278d9b458SJessica Zhang
17378d9b458SJessica Zhang if (ret)
17478d9b458SJessica Zhang goto cleanup;
17578d9b458SJessica Zhang
17678d9b458SJessica Zhang } else if (was_enabled && !enable) {
17778d9b458SJessica Zhang drm_crtc_vblank_put(crtc);
17878d9b458SJessica Zhang }
17978d9b458SJessica Zhang
18078d9b458SJessica Zhang spin_lock_irq(&drm_dev->event_lock);
18178d9b458SJessica Zhang crtc_state->crc_source = source;
18278d9b458SJessica Zhang spin_unlock_irq(&drm_dev->event_lock);
18378d9b458SJessica Zhang
18478d9b458SJessica Zhang crtc_state->crc_frame_skip_count = 0;
18578d9b458SJessica Zhang
18658fc5d18SJessica Zhang if (source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER)
18758fc5d18SJessica Zhang dpu_crtc_setup_lm_misr(crtc_state);
188b1665047SJessica Zhang else if (source == DPU_CRTC_CRC_SOURCE_ENCODER)
189b1665047SJessica Zhang dpu_crtc_setup_encoder_misr(crtc);
19058fc5d18SJessica Zhang else
19158fc5d18SJessica Zhang ret = -EINVAL;
19278d9b458SJessica Zhang
19378d9b458SJessica Zhang cleanup:
19478d9b458SJessica Zhang drm_modeset_unlock(&crtc->mutex);
19578d9b458SJessica Zhang
19678d9b458SJessica Zhang return ret;
19778d9b458SJessica Zhang }
19878d9b458SJessica Zhang
dpu_crtc_get_vblank_counter(struct drm_crtc * crtc)19973743e72SKalyan Thota static u32 dpu_crtc_get_vblank_counter(struct drm_crtc *crtc)
20073743e72SKalyan Thota {
201885455d6SMark Yacoub struct drm_encoder *encoder = get_encoder_from_crtc(crtc);
20273743e72SKalyan Thota if (!encoder) {
20373743e72SKalyan Thota DRM_ERROR("no encoder found for crtc %d\n", crtc->index);
204885455d6SMark Yacoub return 0;
20573743e72SKalyan Thota }
20673743e72SKalyan Thota
207885455d6SMark Yacoub return dpu_encoder_get_vsync_count(encoder);
20873743e72SKalyan Thota }
20973743e72SKalyan Thota
dpu_crtc_get_lm_crc(struct drm_crtc * crtc,struct dpu_crtc_state * crtc_state)21058fc5d18SJessica Zhang static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc,
21158fc5d18SJessica Zhang struct dpu_crtc_state *crtc_state)
21278d9b458SJessica Zhang {
21378d9b458SJessica Zhang struct dpu_crtc_mixer *m;
21400326bfaSRob Clark u32 crcs[CRTC_DUAL_MIXERS];
21578d9b458SJessica Zhang
21678d9b458SJessica Zhang int rc = 0;
21758fc5d18SJessica Zhang int i;
21878d9b458SJessica Zhang
21900326bfaSRob Clark BUILD_BUG_ON(ARRAY_SIZE(crcs) != ARRAY_SIZE(crtc_state->mixers));
22078d9b458SJessica Zhang
22178d9b458SJessica Zhang for (i = 0; i < crtc_state->num_mixers; ++i) {
22278d9b458SJessica Zhang
22378d9b458SJessica Zhang m = &crtc_state->mixers[i];
22478d9b458SJessica Zhang
22578d9b458SJessica Zhang if (!m->hw_lm || !m->hw_lm->ops.collect_misr)
22678d9b458SJessica Zhang continue;
22778d9b458SJessica Zhang
22878d9b458SJessica Zhang rc = m->hw_lm->ops.collect_misr(m->hw_lm, &crcs[i]);
22978d9b458SJessica Zhang
23078d9b458SJessica Zhang if (rc) {
2313ce8bdcaSJessica Zhang if (rc != -ENODATA)
23278d9b458SJessica Zhang DRM_DEBUG_DRIVER("MISR read failed\n");
23378d9b458SJessica Zhang return rc;
23478d9b458SJessica Zhang }
23500326bfaSRob Clark }
23600326bfaSRob Clark
23700326bfaSRob Clark return drm_crtc_add_crc_entry(crtc, true,
23800326bfaSRob Clark drm_crtc_accurate_vblank_count(crtc), crcs);
23900326bfaSRob Clark }
24078d9b458SJessica Zhang
dpu_crtc_get_encoder_crc(struct drm_crtc * crtc)241b1665047SJessica Zhang static int dpu_crtc_get_encoder_crc(struct drm_crtc *crtc)
242b1665047SJessica Zhang {
243b1665047SJessica Zhang struct drm_encoder *drm_enc;
244b1665047SJessica Zhang int rc, pos = 0;
245b1665047SJessica Zhang u32 crcs[INTF_MAX];
246b1665047SJessica Zhang
247b1665047SJessica Zhang drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc->state->encoder_mask) {
248b1665047SJessica Zhang rc = dpu_encoder_get_crc(drm_enc, crcs, pos);
249b1665047SJessica Zhang if (rc < 0) {
250b1665047SJessica Zhang if (rc != -ENODATA)
251b1665047SJessica Zhang DRM_DEBUG_DRIVER("MISR read failed\n");
252b1665047SJessica Zhang
253b1665047SJessica Zhang return rc;
254b1665047SJessica Zhang }
255b1665047SJessica Zhang
256b1665047SJessica Zhang pos += rc;
257b1665047SJessica Zhang }
258b1665047SJessica Zhang
259b1665047SJessica Zhang return drm_crtc_add_crc_entry(crtc, true,
260b1665047SJessica Zhang drm_crtc_accurate_vblank_count(crtc), crcs);
261b1665047SJessica Zhang }
262b1665047SJessica Zhang
dpu_crtc_get_crc(struct drm_crtc * crtc)26358fc5d18SJessica Zhang static int dpu_crtc_get_crc(struct drm_crtc *crtc)
26458fc5d18SJessica Zhang {
26558fc5d18SJessica Zhang struct dpu_crtc_state *crtc_state = to_dpu_crtc_state(crtc->state);
26658fc5d18SJessica Zhang
26758fc5d18SJessica Zhang /* Skip first 2 frames in case of "uncooked" CRCs */
26858fc5d18SJessica Zhang if (crtc_state->crc_frame_skip_count < 2) {
26958fc5d18SJessica Zhang crtc_state->crc_frame_skip_count++;
27058fc5d18SJessica Zhang return 0;
27158fc5d18SJessica Zhang }
27258fc5d18SJessica Zhang
27358fc5d18SJessica Zhang if (crtc_state->crc_source == DPU_CRTC_CRC_SOURCE_LAYER_MIXER)
27458fc5d18SJessica Zhang return dpu_crtc_get_lm_crc(crtc, crtc_state);
275b1665047SJessica Zhang else if (crtc_state->crc_source == DPU_CRTC_CRC_SOURCE_ENCODER)
276b1665047SJessica Zhang return dpu_crtc_get_encoder_crc(crtc);
27758fc5d18SJessica Zhang
27858fc5d18SJessica Zhang return -EINVAL;
27958fc5d18SJessica Zhang }
28058fc5d18SJessica Zhang
dpu_crtc_get_scanout_position(struct drm_crtc * crtc,bool in_vblank_irq,int * vpos,int * hpos,ktime_t * stime,ktime_t * etime,const struct drm_display_mode * mode)28173743e72SKalyan Thota static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc,
28273743e72SKalyan Thota bool in_vblank_irq,
28373743e72SKalyan Thota int *vpos, int *hpos,
28473743e72SKalyan Thota ktime_t *stime, ktime_t *etime,
28573743e72SKalyan Thota const struct drm_display_mode *mode)
28673743e72SKalyan Thota {
28773743e72SKalyan Thota unsigned int pipe = crtc->index;
28873743e72SKalyan Thota struct drm_encoder *encoder;
28973743e72SKalyan Thota int line, vsw, vbp, vactive_start, vactive_end, vfp_end;
29073743e72SKalyan Thota
29173743e72SKalyan Thota encoder = get_encoder_from_crtc(crtc);
29273743e72SKalyan Thota if (!encoder) {
29373743e72SKalyan Thota DRM_ERROR("no encoder found for crtc %d\n", pipe);
29473743e72SKalyan Thota return false;
29573743e72SKalyan Thota }
29673743e72SKalyan Thota
29773743e72SKalyan Thota vsw = mode->crtc_vsync_end - mode->crtc_vsync_start;
29873743e72SKalyan Thota vbp = mode->crtc_vtotal - mode->crtc_vsync_end;
29973743e72SKalyan Thota
30073743e72SKalyan Thota /*
30173743e72SKalyan Thota * the line counter is 1 at the start of the VSYNC pulse and VTOTAL at
30273743e72SKalyan Thota * the end of VFP. Translate the porch values relative to the line
30373743e72SKalyan Thota * counter positions.
30473743e72SKalyan Thota */
30573743e72SKalyan Thota
30673743e72SKalyan Thota vactive_start = vsw + vbp + 1;
30773743e72SKalyan Thota vactive_end = vactive_start + mode->crtc_vdisplay;
30873743e72SKalyan Thota
30973743e72SKalyan Thota /* last scan line before VSYNC */
31073743e72SKalyan Thota vfp_end = mode->crtc_vtotal;
31173743e72SKalyan Thota
31273743e72SKalyan Thota if (stime)
31373743e72SKalyan Thota *stime = ktime_get();
31473743e72SKalyan Thota
31573743e72SKalyan Thota line = dpu_encoder_get_linecount(encoder);
31673743e72SKalyan Thota
31773743e72SKalyan Thota if (line < vactive_start)
31873743e72SKalyan Thota line -= vactive_start;
31973743e72SKalyan Thota else if (line > vactive_end)
32073743e72SKalyan Thota line = line - vfp_end - vactive_start;
32173743e72SKalyan Thota else
32273743e72SKalyan Thota line -= vactive_start;
32373743e72SKalyan Thota
32473743e72SKalyan Thota *vpos = line;
32573743e72SKalyan Thota *hpos = 0;
32673743e72SKalyan Thota
32773743e72SKalyan Thota if (etime)
32873743e72SKalyan Thota *etime = ktime_get();
32973743e72SKalyan Thota
33073743e72SKalyan Thota return true;
33173743e72SKalyan Thota }
33273743e72SKalyan Thota
_dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer * mixer,struct dpu_plane_state * pstate,struct dpu_format * format)33325fdd593SJeykumar Sankaran static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
33474593a28SSravanthi Kollukuduru struct dpu_plane_state *pstate, struct dpu_format *format)
33525fdd593SJeykumar Sankaran {
33625fdd593SJeykumar Sankaran struct dpu_hw_mixer *lm = mixer->hw_lm;
33774593a28SSravanthi Kollukuduru uint32_t blend_op;
338f964cfb7SDmitry Baryshkov uint32_t fg_alpha, bg_alpha;
339f964cfb7SDmitry Baryshkov
340f964cfb7SDmitry Baryshkov fg_alpha = pstate->base.alpha >> 8;
341f964cfb7SDmitry Baryshkov bg_alpha = 0xff - fg_alpha;
34225fdd593SJeykumar Sankaran
34325fdd593SJeykumar Sankaran /* default to opaque blending */
344f964cfb7SDmitry Baryshkov if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
345f964cfb7SDmitry Baryshkov !format->alpha_enable) {
34674593a28SSravanthi Kollukuduru blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
34774593a28SSravanthi Kollukuduru DPU_BLEND_BG_ALPHA_BG_CONST;
348f964cfb7SDmitry Baryshkov } else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
349f964cfb7SDmitry Baryshkov blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
350f964cfb7SDmitry Baryshkov DPU_BLEND_BG_ALPHA_FG_PIXEL;
351f964cfb7SDmitry Baryshkov if (fg_alpha != 0xff) {
352f964cfb7SDmitry Baryshkov bg_alpha = fg_alpha;
353f964cfb7SDmitry Baryshkov blend_op |= DPU_BLEND_BG_MOD_ALPHA |
354f964cfb7SDmitry Baryshkov DPU_BLEND_BG_INV_MOD_ALPHA;
355f964cfb7SDmitry Baryshkov } else {
356f964cfb7SDmitry Baryshkov blend_op |= DPU_BLEND_BG_INV_ALPHA;
357f964cfb7SDmitry Baryshkov }
358f964cfb7SDmitry Baryshkov } else {
35974593a28SSravanthi Kollukuduru /* coverage blending */
36074593a28SSravanthi Kollukuduru blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL |
361f964cfb7SDmitry Baryshkov DPU_BLEND_BG_ALPHA_FG_PIXEL;
362f964cfb7SDmitry Baryshkov if (fg_alpha != 0xff) {
363f964cfb7SDmitry Baryshkov bg_alpha = fg_alpha;
364f964cfb7SDmitry Baryshkov blend_op |= DPU_BLEND_FG_MOD_ALPHA |
365f964cfb7SDmitry Baryshkov DPU_BLEND_FG_INV_MOD_ALPHA |
366f964cfb7SDmitry Baryshkov DPU_BLEND_BG_MOD_ALPHA |
367f964cfb7SDmitry Baryshkov DPU_BLEND_BG_INV_MOD_ALPHA;
368f964cfb7SDmitry Baryshkov } else {
369f964cfb7SDmitry Baryshkov blend_op |= DPU_BLEND_BG_INV_ALPHA;
370f964cfb7SDmitry Baryshkov }
37174593a28SSravanthi Kollukuduru }
37274593a28SSravanthi Kollukuduru
37374593a28SSravanthi Kollukuduru lm->ops.setup_blend_config(lm, pstate->stage,
374f964cfb7SDmitry Baryshkov fg_alpha, bg_alpha, blend_op);
37574593a28SSravanthi Kollukuduru
3765b702d78SStephen Boyd DRM_DEBUG_ATOMIC("format:%p4cc, alpha_en:%u blend_op:0x%x\n",
37792f1d09cSSakari Ailus &format->base.pixel_format, format->alpha_enable, blend_op);
37825fdd593SJeykumar Sankaran }
37925fdd593SJeykumar Sankaran
_dpu_crtc_program_lm_output_roi(struct drm_crtc * crtc)38025fdd593SJeykumar Sankaran static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc)
38125fdd593SJeykumar Sankaran {
38225fdd593SJeykumar Sankaran struct dpu_crtc_state *crtc_state;
38325fdd593SJeykumar Sankaran int lm_idx, lm_horiz_position;
38425fdd593SJeykumar Sankaran
38525fdd593SJeykumar Sankaran crtc_state = to_dpu_crtc_state(crtc->state);
38625fdd593SJeykumar Sankaran
38725fdd593SJeykumar Sankaran lm_horiz_position = 0;
3889222cdd2SJeykumar Sankaran for (lm_idx = 0; lm_idx < crtc_state->num_mixers; lm_idx++) {
38925fdd593SJeykumar Sankaran const struct drm_rect *lm_roi = &crtc_state->lm_bounds[lm_idx];
3909222cdd2SJeykumar Sankaran struct dpu_hw_mixer *hw_lm = crtc_state->mixers[lm_idx].hw_lm;
39125fdd593SJeykumar Sankaran struct dpu_hw_mixer_cfg cfg;
39225fdd593SJeykumar Sankaran
39325fdd593SJeykumar Sankaran if (!lm_roi || !drm_rect_visible(lm_roi))
39425fdd593SJeykumar Sankaran continue;
39525fdd593SJeykumar Sankaran
39625fdd593SJeykumar Sankaran cfg.out_width = drm_rect_width(lm_roi);
39725fdd593SJeykumar Sankaran cfg.out_height = drm_rect_height(lm_roi);
39825fdd593SJeykumar Sankaran cfg.right_mixer = lm_horiz_position++;
39925fdd593SJeykumar Sankaran cfg.flags = 0;
40025fdd593SJeykumar Sankaran hw_lm->ops.setup_mixer_out(hw_lm, &cfg);
40125fdd593SJeykumar Sankaran }
40225fdd593SJeykumar Sankaran }
40325fdd593SJeykumar Sankaran
_dpu_crtc_blend_setup_pipe(struct drm_crtc * crtc,struct drm_plane * plane,struct dpu_crtc_mixer * mixer,u32 num_mixers,enum dpu_stage stage,struct dpu_format * format,uint64_t modifier,struct dpu_sw_pipe * pipe,unsigned int stage_idx,struct dpu_hw_stage_cfg * stage_cfg)404dc0b5a61SDmitry Baryshkov static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc,
405dc0b5a61SDmitry Baryshkov struct drm_plane *plane,
406dc0b5a61SDmitry Baryshkov struct dpu_crtc_mixer *mixer,
407dc0b5a61SDmitry Baryshkov u32 num_mixers,
408dc0b5a61SDmitry Baryshkov enum dpu_stage stage,
409dc0b5a61SDmitry Baryshkov struct dpu_format *format,
410dc0b5a61SDmitry Baryshkov uint64_t modifier,
411dc0b5a61SDmitry Baryshkov struct dpu_sw_pipe *pipe,
412dc0b5a61SDmitry Baryshkov unsigned int stage_idx,
413dc0b5a61SDmitry Baryshkov struct dpu_hw_stage_cfg *stage_cfg
414dc0b5a61SDmitry Baryshkov )
415dc0b5a61SDmitry Baryshkov {
416dc0b5a61SDmitry Baryshkov uint32_t lm_idx;
417dc0b5a61SDmitry Baryshkov enum dpu_sspp sspp_idx;
418dc0b5a61SDmitry Baryshkov struct drm_plane_state *state;
419dc0b5a61SDmitry Baryshkov
420dc0b5a61SDmitry Baryshkov sspp_idx = pipe->sspp->idx;
421dc0b5a61SDmitry Baryshkov
422dc0b5a61SDmitry Baryshkov state = plane->state;
423dc0b5a61SDmitry Baryshkov
424dc0b5a61SDmitry Baryshkov trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane),
425dc0b5a61SDmitry Baryshkov state, to_dpu_plane_state(state), stage_idx,
426dc0b5a61SDmitry Baryshkov format->base.pixel_format,
427dc0b5a61SDmitry Baryshkov modifier);
428dc0b5a61SDmitry Baryshkov
429b7bb8967SAbhinav Kumar DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d multirect_idx %d\n",
430dc0b5a61SDmitry Baryshkov crtc->base.id,
431dc0b5a61SDmitry Baryshkov stage,
432dc0b5a61SDmitry Baryshkov plane->base.id,
433dc0b5a61SDmitry Baryshkov sspp_idx - SSPP_NONE,
434b7bb8967SAbhinav Kumar state->fb ? state->fb->base.id : -1,
435b7bb8967SAbhinav Kumar pipe->multirect_index);
436dc0b5a61SDmitry Baryshkov
437dc0b5a61SDmitry Baryshkov stage_cfg->stage[stage][stage_idx] = sspp_idx;
438dc0b5a61SDmitry Baryshkov stage_cfg->multirect_index[stage][stage_idx] = pipe->multirect_index;
439dc0b5a61SDmitry Baryshkov
440dc0b5a61SDmitry Baryshkov /* blend config update */
441dc0b5a61SDmitry Baryshkov for (lm_idx = 0; lm_idx < num_mixers; lm_idx++)
442dc0b5a61SDmitry Baryshkov mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl, sspp_idx);
443dc0b5a61SDmitry Baryshkov }
444dc0b5a61SDmitry Baryshkov
_dpu_crtc_blend_setup_mixer(struct drm_crtc * crtc,struct dpu_crtc * dpu_crtc,struct dpu_crtc_mixer * mixer,struct dpu_hw_stage_cfg * stage_cfg)44525fdd593SJeykumar Sankaran static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
44653c064a1SDmitry Baryshkov struct dpu_crtc *dpu_crtc, struct dpu_crtc_mixer *mixer,
44753c064a1SDmitry Baryshkov struct dpu_hw_stage_cfg *stage_cfg)
44825fdd593SJeykumar Sankaran {
44925fdd593SJeykumar Sankaran struct drm_plane *plane;
45025fdd593SJeykumar Sankaran struct drm_framebuffer *fb;
45125fdd593SJeykumar Sankaran struct drm_plane_state *state;
45204b96b63SBruce Wang struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
45325fdd593SJeykumar Sankaran struct dpu_plane_state *pstate = NULL;
45425fdd593SJeykumar Sankaran struct dpu_format *format;
45504b96b63SBruce Wang struct dpu_hw_ctl *ctl = mixer->lm_ctl;
45625fdd593SJeykumar Sankaran
457dc0b5a61SDmitry Baryshkov uint32_t lm_idx;
45825fdd593SJeykumar Sankaran bool bg_alpha_enable = false;
459b3652e87SKrishna Manikandan DECLARE_BITMAP(fetch_active, SSPP_MAX);
46025fdd593SJeykumar Sankaran
461b3652e87SKrishna Manikandan memset(fetch_active, 0, sizeof(fetch_active));
46225fdd593SJeykumar Sankaran drm_atomic_crtc_for_each_plane(plane, crtc) {
46325fdd593SJeykumar Sankaran state = plane->state;
46425fdd593SJeykumar Sankaran if (!state)
46525fdd593SJeykumar Sankaran continue;
46625fdd593SJeykumar Sankaran
467cb77085bSRob Clark if (!state->visible)
468cb77085bSRob Clark continue;
469cb77085bSRob Clark
47025fdd593SJeykumar Sankaran pstate = to_dpu_plane_state(state);
47125fdd593SJeykumar Sankaran fb = state->fb;
47225fdd593SJeykumar Sankaran
47325fdd593SJeykumar Sankaran format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));
47425fdd593SJeykumar Sankaran
47525fdd593SJeykumar Sankaran if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
47625fdd593SJeykumar Sankaran bg_alpha_enable = true;
47725fdd593SJeykumar Sankaran
478dc0b5a61SDmitry Baryshkov set_bit(pstate->pipe.sspp->idx, fetch_active);
479dc0b5a61SDmitry Baryshkov _dpu_crtc_blend_setup_pipe(crtc, plane,
480dc0b5a61SDmitry Baryshkov mixer, cstate->num_mixers,
481dc0b5a61SDmitry Baryshkov pstate->stage,
482dc0b5a61SDmitry Baryshkov format, fb ? fb->modifier : 0,
483dc0b5a61SDmitry Baryshkov &pstate->pipe, 0, stage_cfg);
48425fdd593SJeykumar Sankaran
48580e8ae3bSDmitry Baryshkov if (pstate->r_pipe.sspp) {
48680e8ae3bSDmitry Baryshkov set_bit(pstate->r_pipe.sspp->idx, fetch_active);
48780e8ae3bSDmitry Baryshkov _dpu_crtc_blend_setup_pipe(crtc, plane,
48880e8ae3bSDmitry Baryshkov mixer, cstate->num_mixers,
48980e8ae3bSDmitry Baryshkov pstate->stage,
49080e8ae3bSDmitry Baryshkov format, fb ? fb->modifier : 0,
49180e8ae3bSDmitry Baryshkov &pstate->r_pipe, 1, stage_cfg);
49280e8ae3bSDmitry Baryshkov }
49380e8ae3bSDmitry Baryshkov
49425fdd593SJeykumar Sankaran /* blend config update */
4959222cdd2SJeykumar Sankaran for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
496dc0b5a61SDmitry Baryshkov _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format);
49725fdd593SJeykumar Sankaran
49825fdd593SJeykumar Sankaran if (bg_alpha_enable && !format->alpha_enable)
49925fdd593SJeykumar Sankaran mixer[lm_idx].mixer_op_mode = 0;
50025fdd593SJeykumar Sankaran else
50125fdd593SJeykumar Sankaran mixer[lm_idx].mixer_op_mode |=
50225fdd593SJeykumar Sankaran 1 << pstate->stage;
50325fdd593SJeykumar Sankaran }
50425fdd593SJeykumar Sankaran }
50525fdd593SJeykumar Sankaran
506b3652e87SKrishna Manikandan if (ctl->ops.set_active_pipes)
507b3652e87SKrishna Manikandan ctl->ops.set_active_pipes(ctl, fetch_active);
508b3652e87SKrishna Manikandan
50925fdd593SJeykumar Sankaran _dpu_crtc_program_lm_output_roi(crtc);
51025fdd593SJeykumar Sankaran }
51125fdd593SJeykumar Sankaran
51225fdd593SJeykumar Sankaran /**
51325fdd593SJeykumar Sankaran * _dpu_crtc_blend_setup - configure crtc mixers
51425fdd593SJeykumar Sankaran * @crtc: Pointer to drm crtc structure
51525fdd593SJeykumar Sankaran */
_dpu_crtc_blend_setup(struct drm_crtc * crtc)51625fdd593SJeykumar Sankaran static void _dpu_crtc_blend_setup(struct drm_crtc *crtc)
51725fdd593SJeykumar Sankaran {
51804b96b63SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
51904b96b63SBruce Wang struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
52004b96b63SBruce Wang struct dpu_crtc_mixer *mixer = cstate->mixers;
52125fdd593SJeykumar Sankaran struct dpu_hw_ctl *ctl;
52225fdd593SJeykumar Sankaran struct dpu_hw_mixer *lm;
52353c064a1SDmitry Baryshkov struct dpu_hw_stage_cfg stage_cfg;
52425fdd593SJeykumar Sankaran int i;
52525fdd593SJeykumar Sankaran
5265b702d78SStephen Boyd DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name);
52725fdd593SJeykumar Sankaran
5289222cdd2SJeykumar Sankaran for (i = 0; i < cstate->num_mixers; i++) {
52925fdd593SJeykumar Sankaran mixer[i].mixer_op_mode = 0;
530cf6916f4SJeykumar Sankaran if (mixer[i].lm_ctl->ops.clear_all_blendstages)
531cf6916f4SJeykumar Sankaran mixer[i].lm_ctl->ops.clear_all_blendstages(
532cf6916f4SJeykumar Sankaran mixer[i].lm_ctl);
53325fdd593SJeykumar Sankaran }
53425fdd593SJeykumar Sankaran
53525fdd593SJeykumar Sankaran /* initialize stage cfg */
53653c064a1SDmitry Baryshkov memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg));
53725fdd593SJeykumar Sankaran
53853c064a1SDmitry Baryshkov _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg);
53925fdd593SJeykumar Sankaran
5409222cdd2SJeykumar Sankaran for (i = 0; i < cstate->num_mixers; i++) {
541cf6916f4SJeykumar Sankaran ctl = mixer[i].lm_ctl;
54225fdd593SJeykumar Sankaran lm = mixer[i].hw_lm;
54325fdd593SJeykumar Sankaran
54425fdd593SJeykumar Sankaran lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode);
54525fdd593SJeykumar Sankaran
5463cde792aSDmitry Baryshkov /* stage config flush mask */
5473cde792aSDmitry Baryshkov ctl->ops.update_pending_flush_mixer(ctl,
54825fdd593SJeykumar Sankaran mixer[i].hw_lm->idx);
54925fdd593SJeykumar Sankaran
5503cde792aSDmitry Baryshkov DRM_DEBUG_ATOMIC("lm %d, op_mode 0x%X, ctl %d\n",
55125fdd593SJeykumar Sankaran mixer[i].hw_lm->idx - LM_0,
55225fdd593SJeykumar Sankaran mixer[i].mixer_op_mode,
5533cde792aSDmitry Baryshkov ctl->idx - CTL_0);
55425fdd593SJeykumar Sankaran
55525fdd593SJeykumar Sankaran ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx,
55653c064a1SDmitry Baryshkov &stage_cfg);
55725fdd593SJeykumar Sankaran }
55825fdd593SJeykumar Sankaran }
55925fdd593SJeykumar Sankaran
56025fdd593SJeykumar Sankaran /**
56125fdd593SJeykumar Sankaran * _dpu_crtc_complete_flip - signal pending page_flip events
56225fdd593SJeykumar Sankaran * Any pending vblank events are added to the vblank_event_list
56325fdd593SJeykumar Sankaran * so that the next vblank interrupt shall signal them.
56425fdd593SJeykumar Sankaran * However PAGE_FLIP events are not handled through the vblank_event_list.
56525fdd593SJeykumar Sankaran * This API signals any pending PAGE_FLIP events requested through
56625fdd593SJeykumar Sankaran * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the dpu_crtc->event.
56725fdd593SJeykumar Sankaran * @crtc: Pointer to drm crtc structure
56825fdd593SJeykumar Sankaran */
_dpu_crtc_complete_flip(struct drm_crtc * crtc)56925fdd593SJeykumar Sankaran static void _dpu_crtc_complete_flip(struct drm_crtc *crtc)
57025fdd593SJeykumar Sankaran {
57125fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
57225fdd593SJeykumar Sankaran struct drm_device *dev = crtc->dev;
57325fdd593SJeykumar Sankaran unsigned long flags;
57425fdd593SJeykumar Sankaran
57525fdd593SJeykumar Sankaran spin_lock_irqsave(&dev->event_lock, flags);
57625fdd593SJeykumar Sankaran if (dpu_crtc->event) {
57725fdd593SJeykumar Sankaran DRM_DEBUG_VBL("%s: send event: %pK\n", dpu_crtc->name,
57825fdd593SJeykumar Sankaran dpu_crtc->event);
57925fdd593SJeykumar Sankaran trace_dpu_crtc_complete_flip(DRMID(crtc));
58025fdd593SJeykumar Sankaran drm_crtc_send_vblank_event(crtc, dpu_crtc->event);
58125fdd593SJeykumar Sankaran dpu_crtc->event = NULL;
58225fdd593SJeykumar Sankaran }
58325fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dev->event_lock, flags);
58425fdd593SJeykumar Sankaran }
58525fdd593SJeykumar Sankaran
dpu_crtc_get_intf_mode(struct drm_crtc * crtc)58625fdd593SJeykumar Sankaran enum dpu_intf_mode dpu_crtc_get_intf_mode(struct drm_crtc *crtc)
58725fdd593SJeykumar Sankaran {
58825fdd593SJeykumar Sankaran struct drm_encoder *encoder;
58925fdd593SJeykumar Sankaran
590ab198a7aSSean Paul /*
591ab198a7aSSean Paul * TODO: This function is called from dpu debugfs and as part of atomic
592ab198a7aSSean Paul * check. When called from debugfs, the crtc->mutex must be held to
593ab198a7aSSean Paul * read crtc->state. However reading crtc->state from atomic check isn't
594ab198a7aSSean Paul * allowed (unless you have a good reason, a big comment, and a deep
595ab198a7aSSean Paul * understanding of how the atomic/modeset locks work (<- and this is
596ab198a7aSSean Paul * probably not possible)). So we'll keep the WARN_ON here for now, but
597ab198a7aSSean Paul * really we need to figure out a better way to track our operating mode
598ab198a7aSSean Paul */
5991dfdb0e1SSean Paul WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
6001dfdb0e1SSean Paul
6014b8c6279SSean Paul /* TODO: Returns the first INTF_MODE, could there be multiple values? */
6024b8c6279SSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
60325fdd593SJeykumar Sankaran return dpu_encoder_get_intf_mode(encoder);
60425fdd593SJeykumar Sankaran
60525fdd593SJeykumar Sankaran return INTF_MODE_NONE;
60625fdd593SJeykumar Sankaran }
60725fdd593SJeykumar Sankaran
dpu_crtc_vblank_callback(struct drm_crtc * crtc)608e4914867SSean Paul void dpu_crtc_vblank_callback(struct drm_crtc *crtc)
60925fdd593SJeykumar Sankaran {
61025fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
61125fdd593SJeykumar Sankaran
61225fdd593SJeykumar Sankaran /* keep statistics on vblank callback - with auto reset via debugfs */
61325fdd593SJeykumar Sankaran if (ktime_compare(dpu_crtc->vblank_cb_time, ktime_set(0, 0)) == 0)
61425fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_time = ktime_get();
61525fdd593SJeykumar Sankaran else
61625fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_count++;
61778d9b458SJessica Zhang
61878d9b458SJessica Zhang dpu_crtc_get_crc(crtc);
61978d9b458SJessica Zhang
62025fdd593SJeykumar Sankaran drm_crtc_handle_vblank(crtc);
62125fdd593SJeykumar Sankaran trace_dpu_crtc_vblank_cb(DRMID(crtc));
62225fdd593SJeykumar Sankaran }
62325fdd593SJeykumar Sankaran
dpu_crtc_frame_event_work(struct kthread_work * work)62425fdd593SJeykumar Sankaran static void dpu_crtc_frame_event_work(struct kthread_work *work)
62525fdd593SJeykumar Sankaran {
62604b96b63SBruce Wang struct dpu_crtc_frame_event *fevent = container_of(work,
62704b96b63SBruce Wang struct dpu_crtc_frame_event, work);
62804b96b63SBruce Wang struct drm_crtc *crtc = fevent->crtc;
62904b96b63SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
63025fdd593SJeykumar Sankaran unsigned long flags;
63125fdd593SJeykumar Sankaran bool frame_done = false;
63225fdd593SJeykumar Sankaran
63325fdd593SJeykumar Sankaran DPU_ATRACE_BEGIN("crtc_frame_event");
63425fdd593SJeykumar Sankaran
6355b702d78SStephen Boyd DRM_DEBUG_ATOMIC("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event,
63625fdd593SJeykumar Sankaran ktime_to_ns(fevent->ts));
63725fdd593SJeykumar Sankaran
63825fdd593SJeykumar Sankaran if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE
63925fdd593SJeykumar Sankaran | DPU_ENCODER_FRAME_EVENT_ERROR
64025fdd593SJeykumar Sankaran | DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)) {
64125fdd593SJeykumar Sankaran
64225fdd593SJeykumar Sankaran if (atomic_read(&dpu_crtc->frame_pending) < 1) {
64341a52059SRob Clark /* ignore vblank when not pending */
64425fdd593SJeykumar Sankaran } else if (atomic_dec_return(&dpu_crtc->frame_pending) == 0) {
64525fdd593SJeykumar Sankaran /* release bandwidth and other resources */
64625fdd593SJeykumar Sankaran trace_dpu_crtc_frame_event_done(DRMID(crtc),
64725fdd593SJeykumar Sankaran fevent->event);
648241b507cSRob Clark dpu_core_perf_crtc_release_bw(crtc);
64925fdd593SJeykumar Sankaran } else {
65025fdd593SJeykumar Sankaran trace_dpu_crtc_frame_event_more_pending(DRMID(crtc),
65125fdd593SJeykumar Sankaran fevent->event);
65225fdd593SJeykumar Sankaran }
65325fdd593SJeykumar Sankaran
65425fdd593SJeykumar Sankaran if (fevent->event & (DPU_ENCODER_FRAME_EVENT_DONE
65525fdd593SJeykumar Sankaran | DPU_ENCODER_FRAME_EVENT_ERROR))
65625fdd593SJeykumar Sankaran frame_done = true;
65725fdd593SJeykumar Sankaran }
65825fdd593SJeykumar Sankaran
65925fdd593SJeykumar Sankaran if (fevent->event & DPU_ENCODER_FRAME_EVENT_PANEL_DEAD)
66025fdd593SJeykumar Sankaran DPU_ERROR("crtc%d ts:%lld received panel dead event\n",
66125fdd593SJeykumar Sankaran crtc->base.id, ktime_to_ns(fevent->ts));
66225fdd593SJeykumar Sankaran
66325fdd593SJeykumar Sankaran if (frame_done)
66425fdd593SJeykumar Sankaran complete_all(&dpu_crtc->frame_done_comp);
66525fdd593SJeykumar Sankaran
66625fdd593SJeykumar Sankaran spin_lock_irqsave(&dpu_crtc->spin_lock, flags);
66725fdd593SJeykumar Sankaran list_add_tail(&fevent->list, &dpu_crtc->frame_event_list);
66825fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
66925fdd593SJeykumar Sankaran DPU_ATRACE_END("crtc_frame_event");
67025fdd593SJeykumar Sankaran }
67125fdd593SJeykumar Sankaran
67225fdd593SJeykumar Sankaran /*
67325fdd593SJeykumar Sankaran * dpu_crtc_frame_event_cb - crtc frame event callback API. CRTC module
67425fdd593SJeykumar Sankaran * registers this API to encoder for all frame event callbacks like
67525fdd593SJeykumar Sankaran * frame_error, frame_done, idle_timeout, etc. Encoder may call different events
67625fdd593SJeykumar Sankaran * from different context - IRQ, user thread, commit_thread, etc. Each event
67725fdd593SJeykumar Sankaran * should be carefully reviewed and should be processed in proper task context
67825fdd593SJeykumar Sankaran * to avoid schedulin delay or properly manage the irq context's bottom half
67925fdd593SJeykumar Sankaran * processing.
68025fdd593SJeykumar Sankaran */
dpu_crtc_frame_event_cb(void * data,u32 event)68125fdd593SJeykumar Sankaran static void dpu_crtc_frame_event_cb(void *data, u32 event)
68225fdd593SJeykumar Sankaran {
68325fdd593SJeykumar Sankaran struct drm_crtc *crtc = (struct drm_crtc *)data;
68425fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc;
68525fdd593SJeykumar Sankaran struct msm_drm_private *priv;
68625fdd593SJeykumar Sankaran struct dpu_crtc_frame_event *fevent;
68725fdd593SJeykumar Sankaran unsigned long flags;
68825fdd593SJeykumar Sankaran u32 crtc_id;
68925fdd593SJeykumar Sankaran
69025fdd593SJeykumar Sankaran /* Nothing to do on idle event */
69125fdd593SJeykumar Sankaran if (event & DPU_ENCODER_FRAME_EVENT_IDLE)
69225fdd593SJeykumar Sankaran return;
69325fdd593SJeykumar Sankaran
69425fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc);
69525fdd593SJeykumar Sankaran priv = crtc->dev->dev_private;
69625fdd593SJeykumar Sankaran crtc_id = drm_crtc_index(crtc);
69725fdd593SJeykumar Sankaran
69825fdd593SJeykumar Sankaran trace_dpu_crtc_frame_event_cb(DRMID(crtc), event);
69925fdd593SJeykumar Sankaran
70025fdd593SJeykumar Sankaran spin_lock_irqsave(&dpu_crtc->spin_lock, flags);
70125fdd593SJeykumar Sankaran fevent = list_first_entry_or_null(&dpu_crtc->frame_event_list,
70225fdd593SJeykumar Sankaran struct dpu_crtc_frame_event, list);
70325fdd593SJeykumar Sankaran if (fevent)
70425fdd593SJeykumar Sankaran list_del_init(&fevent->list);
70525fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dpu_crtc->spin_lock, flags);
70625fdd593SJeykumar Sankaran
70725fdd593SJeykumar Sankaran if (!fevent) {
7085e16372bSRob Clark DRM_ERROR_RATELIMITED("crtc%d event %d overflow\n", crtc->base.id, event);
70925fdd593SJeykumar Sankaran return;
71025fdd593SJeykumar Sankaran }
71125fdd593SJeykumar Sankaran
71225fdd593SJeykumar Sankaran fevent->event = event;
71325fdd593SJeykumar Sankaran fevent->crtc = crtc;
71425fdd593SJeykumar Sankaran fevent->ts = ktime_get();
7151041dee2SBernard kthread_queue_work(priv->event_thread[crtc_id].worker, &fevent->work);
71625fdd593SJeykumar Sankaran }
71725fdd593SJeykumar Sankaran
dpu_crtc_complete_commit(struct drm_crtc * crtc)71880b4b4a7SRob Clark void dpu_crtc_complete_commit(struct drm_crtc *crtc)
71925fdd593SJeykumar Sankaran {
72025fdd593SJeykumar Sankaran trace_dpu_crtc_complete_commit(DRMID(crtc));
721716f0d4cSDmitry Baryshkov dpu_core_perf_crtc_update(crtc, 0);
722fd630ae9SRob Clark _dpu_crtc_complete_flip(crtc);
72325fdd593SJeykumar Sankaran }
72425fdd593SJeykumar Sankaran
_dpu_crtc_setup_lm_bounds(struct drm_crtc * crtc,struct drm_crtc_state * state)72525fdd593SJeykumar Sankaran static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
72625fdd593SJeykumar Sankaran struct drm_crtc_state *state)
72725fdd593SJeykumar Sankaran {
72804b96b63SBruce Wang struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
72904b96b63SBruce Wang struct drm_display_mode *adj_mode = &state->adjusted_mode;
7303804a982SJordan Crouse u32 crtc_split_width = adj_mode->hdisplay / cstate->num_mixers;
73125fdd593SJeykumar Sankaran int i;
73225fdd593SJeykumar Sankaran
7339222cdd2SJeykumar Sankaran for (i = 0; i < cstate->num_mixers; i++) {
73425fdd593SJeykumar Sankaran struct drm_rect *r = &cstate->lm_bounds[i];
73525fdd593SJeykumar Sankaran r->x1 = crtc_split_width * i;
73625fdd593SJeykumar Sankaran r->y1 = 0;
73725fdd593SJeykumar Sankaran r->x2 = r->x1 + crtc_split_width;
73835d600ddSJordan Crouse r->y2 = adj_mode->vdisplay;
73925fdd593SJeykumar Sankaran
74025fdd593SJeykumar Sankaran trace_dpu_crtc_setup_lm_bounds(DRMID(crtc), i, r);
74125fdd593SJeykumar Sankaran }
74225fdd593SJeykumar Sankaran }
74325fdd593SJeykumar Sankaran
_dpu_crtc_get_pcc_coeff(struct drm_crtc_state * state,struct dpu_hw_pcc_cfg * cfg)7444259ff7aSKalyan Thota static void _dpu_crtc_get_pcc_coeff(struct drm_crtc_state *state,
7454259ff7aSKalyan Thota struct dpu_hw_pcc_cfg *cfg)
7464259ff7aSKalyan Thota {
7474259ff7aSKalyan Thota struct drm_color_ctm *ctm;
7484259ff7aSKalyan Thota
7494259ff7aSKalyan Thota memset(cfg, 0, sizeof(struct dpu_hw_pcc_cfg));
7504259ff7aSKalyan Thota
7514259ff7aSKalyan Thota ctm = (struct drm_color_ctm *)state->ctm->data;
7524259ff7aSKalyan Thota
7534259ff7aSKalyan Thota if (!ctm)
7544259ff7aSKalyan Thota return;
7554259ff7aSKalyan Thota
7564259ff7aSKalyan Thota cfg->r.r = CONVERT_S3_15(ctm->matrix[0]);
7574259ff7aSKalyan Thota cfg->g.r = CONVERT_S3_15(ctm->matrix[1]);
7584259ff7aSKalyan Thota cfg->b.r = CONVERT_S3_15(ctm->matrix[2]);
7594259ff7aSKalyan Thota
7604259ff7aSKalyan Thota cfg->r.g = CONVERT_S3_15(ctm->matrix[3]);
7614259ff7aSKalyan Thota cfg->g.g = CONVERT_S3_15(ctm->matrix[4]);
7624259ff7aSKalyan Thota cfg->b.g = CONVERT_S3_15(ctm->matrix[5]);
7634259ff7aSKalyan Thota
7644259ff7aSKalyan Thota cfg->r.b = CONVERT_S3_15(ctm->matrix[6]);
7654259ff7aSKalyan Thota cfg->g.b = CONVERT_S3_15(ctm->matrix[7]);
7664259ff7aSKalyan Thota cfg->b.b = CONVERT_S3_15(ctm->matrix[8]);
7674259ff7aSKalyan Thota }
7684259ff7aSKalyan Thota
_dpu_crtc_setup_cp_blocks(struct drm_crtc * crtc)7694259ff7aSKalyan Thota static void _dpu_crtc_setup_cp_blocks(struct drm_crtc *crtc)
7704259ff7aSKalyan Thota {
7714259ff7aSKalyan Thota struct drm_crtc_state *state = crtc->state;
7724259ff7aSKalyan Thota struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
7734259ff7aSKalyan Thota struct dpu_crtc_mixer *mixer = cstate->mixers;
7744259ff7aSKalyan Thota struct dpu_hw_pcc_cfg cfg;
7754259ff7aSKalyan Thota struct dpu_hw_ctl *ctl;
7764259ff7aSKalyan Thota struct dpu_hw_dspp *dspp;
7774259ff7aSKalyan Thota int i;
7784259ff7aSKalyan Thota
7794259ff7aSKalyan Thota
7807efd4edcSJessica Zhang if (!state->color_mgmt_changed && !drm_atomic_crtc_needs_modeset(state))
7814259ff7aSKalyan Thota return;
7824259ff7aSKalyan Thota
7834259ff7aSKalyan Thota for (i = 0; i < cstate->num_mixers; i++) {
7844259ff7aSKalyan Thota ctl = mixer[i].lm_ctl;
7854259ff7aSKalyan Thota dspp = mixer[i].hw_dspp;
7864259ff7aSKalyan Thota
7874259ff7aSKalyan Thota if (!dspp || !dspp->ops.setup_pcc)
7884259ff7aSKalyan Thota continue;
7894259ff7aSKalyan Thota
7904259ff7aSKalyan Thota if (!state->ctm) {
7914259ff7aSKalyan Thota dspp->ops.setup_pcc(dspp, NULL);
7924259ff7aSKalyan Thota } else {
7934259ff7aSKalyan Thota _dpu_crtc_get_pcc_coeff(state, &cfg);
7944259ff7aSKalyan Thota dspp->ops.setup_pcc(dspp, &cfg);
7954259ff7aSKalyan Thota }
7964259ff7aSKalyan Thota
7974259ff7aSKalyan Thota /* stage config flush mask */
7983cde792aSDmitry Baryshkov ctl->ops.update_pending_flush_dspp(ctl,
79983a58b20SKalyan Thota mixer[i].hw_dspp->idx, DPU_DSPP_PCC);
8004259ff7aSKalyan Thota }
8014259ff7aSKalyan Thota }
8024259ff7aSKalyan Thota
dpu_crtc_atomic_begin(struct drm_crtc * crtc,struct drm_atomic_state * state)80325fdd593SJeykumar Sankaran static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
804f6ebe9f9SMaxime Ripard struct drm_atomic_state *state)
80525fdd593SJeykumar Sankaran {
806e12e5263SRob Clark struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
80725fdd593SJeykumar Sankaran struct drm_encoder *encoder;
80825fdd593SJeykumar Sankaran
80925fdd593SJeykumar Sankaran if (!crtc->state->enable) {
8105b702d78SStephen Boyd DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_begin\n",
81125fdd593SJeykumar Sankaran crtc->base.id, crtc->state->enable);
81225fdd593SJeykumar Sankaran return;
81325fdd593SJeykumar Sankaran }
81425fdd593SJeykumar Sankaran
8155b702d78SStephen Boyd DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
81625fdd593SJeykumar Sankaran
81725fdd593SJeykumar Sankaran _dpu_crtc_setup_lm_bounds(crtc, crtc->state);
81825fdd593SJeykumar Sankaran
81925fdd593SJeykumar Sankaran /* encoder will trigger pending mask now */
8204b8c6279SSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
82125fdd593SJeykumar Sankaran dpu_encoder_trigger_kickoff_pending(encoder);
82225fdd593SJeykumar Sankaran
82325fdd593SJeykumar Sankaran /*
82425fdd593SJeykumar Sankaran * If no mixers have been allocated in dpu_crtc_atomic_check(),
82525fdd593SJeykumar Sankaran * it means we are trying to flush a CRTC whose state is disabled:
82625fdd593SJeykumar Sankaran * nothing else needs to be done.
82725fdd593SJeykumar Sankaran */
8289222cdd2SJeykumar Sankaran if (unlikely(!cstate->num_mixers))
82925fdd593SJeykumar Sankaran return;
83025fdd593SJeykumar Sankaran
83125fdd593SJeykumar Sankaran _dpu_crtc_blend_setup(crtc);
83225fdd593SJeykumar Sankaran
8334259ff7aSKalyan Thota _dpu_crtc_setup_cp_blocks(crtc);
8344259ff7aSKalyan Thota
83525fdd593SJeykumar Sankaran /*
83625fdd593SJeykumar Sankaran * PP_DONE irq is only used by command mode for now.
83725fdd593SJeykumar Sankaran * It is better to request pending before FLUSH and START trigger
83825fdd593SJeykumar Sankaran * to make sure no pp_done irq missed.
83925fdd593SJeykumar Sankaran * This is safe because no pp_done will happen before SW trigger
84025fdd593SJeykumar Sankaran * in command mode.
84125fdd593SJeykumar Sankaran */
84225fdd593SJeykumar Sankaran }
84325fdd593SJeykumar Sankaran
dpu_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_atomic_state * state)84425fdd593SJeykumar Sankaran static void dpu_crtc_atomic_flush(struct drm_crtc *crtc,
845f6ebe9f9SMaxime Ripard struct drm_atomic_state *state)
84625fdd593SJeykumar Sankaran {
84725fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc;
84825fdd593SJeykumar Sankaran struct drm_device *dev;
84925fdd593SJeykumar Sankaran struct drm_plane *plane;
85025fdd593SJeykumar Sankaran struct msm_drm_private *priv;
85125fdd593SJeykumar Sankaran unsigned long flags;
85225fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate;
85325fdd593SJeykumar Sankaran
85425fdd593SJeykumar Sankaran if (!crtc->state->enable) {
8555b702d78SStephen Boyd DRM_DEBUG_ATOMIC("crtc%d -> enable %d, skip atomic_flush\n",
85625fdd593SJeykumar Sankaran crtc->base.id, crtc->state->enable);
85725fdd593SJeykumar Sankaran return;
85825fdd593SJeykumar Sankaran }
85925fdd593SJeykumar Sankaran
8605b702d78SStephen Boyd DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
86125fdd593SJeykumar Sankaran
86225fdd593SJeykumar Sankaran dpu_crtc = to_dpu_crtc(crtc);
86325fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(crtc->state);
86425fdd593SJeykumar Sankaran dev = crtc->dev;
86525fdd593SJeykumar Sankaran priv = dev->dev_private;
86625fdd593SJeykumar Sankaran
86725fdd593SJeykumar Sankaran if (crtc->index >= ARRAY_SIZE(priv->event_thread)) {
86825fdd593SJeykumar Sankaran DPU_ERROR("invalid crtc index[%d]\n", crtc->index);
86925fdd593SJeykumar Sankaran return;
87025fdd593SJeykumar Sankaran }
87125fdd593SJeykumar Sankaran
872e12e5263SRob Clark WARN_ON(dpu_crtc->event);
87325fdd593SJeykumar Sankaran spin_lock_irqsave(&dev->event_lock, flags);
87425fdd593SJeykumar Sankaran dpu_crtc->event = crtc->state->event;
87525fdd593SJeykumar Sankaran crtc->state->event = NULL;
87625fdd593SJeykumar Sankaran spin_unlock_irqrestore(&dev->event_lock, flags);
87725fdd593SJeykumar Sankaran
87825fdd593SJeykumar Sankaran /*
87925fdd593SJeykumar Sankaran * If no mixers has been allocated in dpu_crtc_atomic_check(),
88025fdd593SJeykumar Sankaran * it means we are trying to flush a CRTC whose state is disabled:
88125fdd593SJeykumar Sankaran * nothing else needs to be done.
88225fdd593SJeykumar Sankaran */
8839222cdd2SJeykumar Sankaran if (unlikely(!cstate->num_mixers))
88425fdd593SJeykumar Sankaran return;
88525fdd593SJeykumar Sankaran
88625fdd593SJeykumar Sankaran /* update performance setting before crtc kickoff */
887716f0d4cSDmitry Baryshkov dpu_core_perf_crtc_update(crtc, 1);
88825fdd593SJeykumar Sankaran
88925fdd593SJeykumar Sankaran /*
89025fdd593SJeykumar Sankaran * Final plane updates: Give each plane a chance to complete all
89125fdd593SJeykumar Sankaran * required writes/flushing before crtc's "flush
89225fdd593SJeykumar Sankaran * everything" call below.
89325fdd593SJeykumar Sankaran */
89425fdd593SJeykumar Sankaran drm_atomic_crtc_for_each_plane(plane, crtc) {
89525fdd593SJeykumar Sankaran if (dpu_crtc->smmu_state.transition_error)
89625fdd593SJeykumar Sankaran dpu_plane_set_error(plane, true);
89725fdd593SJeykumar Sankaran dpu_plane_flush(plane);
89825fdd593SJeykumar Sankaran }
89925fdd593SJeykumar Sankaran
90025fdd593SJeykumar Sankaran /* Kickoff will be scheduled by outer layer */
90125fdd593SJeykumar Sankaran }
90225fdd593SJeykumar Sankaran
90325fdd593SJeykumar Sankaran /**
90425fdd593SJeykumar Sankaran * dpu_crtc_destroy_state - state destroy hook
90525fdd593SJeykumar Sankaran * @crtc: drm CRTC
90625fdd593SJeykumar Sankaran * @state: CRTC state object to release
90725fdd593SJeykumar Sankaran */
dpu_crtc_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)90825fdd593SJeykumar Sankaran static void dpu_crtc_destroy_state(struct drm_crtc *crtc,
90925fdd593SJeykumar Sankaran struct drm_crtc_state *state)
91025fdd593SJeykumar Sankaran {
911e12e5263SRob Clark struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
91225fdd593SJeykumar Sankaran
9135b702d78SStephen Boyd DRM_DEBUG_ATOMIC("crtc%d\n", crtc->base.id);
91425fdd593SJeykumar Sankaran
91525fdd593SJeykumar Sankaran __drm_atomic_helper_crtc_destroy_state(state);
91625fdd593SJeykumar Sankaran
91725fdd593SJeykumar Sankaran kfree(cstate);
91825fdd593SJeykumar Sankaran }
91925fdd593SJeykumar Sankaran
_dpu_crtc_wait_for_frame_done(struct drm_crtc * crtc)92025fdd593SJeykumar Sankaran static int _dpu_crtc_wait_for_frame_done(struct drm_crtc *crtc)
92125fdd593SJeykumar Sankaran {
92204b96b63SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
92325fdd593SJeykumar Sankaran int ret, rc = 0;
92425fdd593SJeykumar Sankaran
92525fdd593SJeykumar Sankaran if (!atomic_read(&dpu_crtc->frame_pending)) {
9265b702d78SStephen Boyd DRM_DEBUG_ATOMIC("no frames pending\n");
92725fdd593SJeykumar Sankaran return 0;
92825fdd593SJeykumar Sankaran }
92925fdd593SJeykumar Sankaran
93025fdd593SJeykumar Sankaran DPU_ATRACE_BEGIN("frame done completion wait");
93125fdd593SJeykumar Sankaran ret = wait_for_completion_timeout(&dpu_crtc->frame_done_comp,
93270df9610SSean Paul msecs_to_jiffies(DPU_CRTC_FRAME_DONE_TIMEOUT_MS));
93325fdd593SJeykumar Sankaran if (!ret) {
93425fdd593SJeykumar Sankaran DRM_ERROR("frame done wait timed out, ret:%d\n", ret);
93525fdd593SJeykumar Sankaran rc = -ETIMEDOUT;
93625fdd593SJeykumar Sankaran }
93725fdd593SJeykumar Sankaran DPU_ATRACE_END("frame done completion wait");
93825fdd593SJeykumar Sankaran
93925fdd593SJeykumar Sankaran return rc;
94025fdd593SJeykumar Sankaran }
94125fdd593SJeykumar Sankaran
dpu_crtc_commit_kickoff(struct drm_crtc * crtc)942b4bb9f15SRob Clark void dpu_crtc_commit_kickoff(struct drm_crtc *crtc)
94325fdd593SJeykumar Sankaran {
94425fdd593SJeykumar Sankaran struct drm_encoder *encoder;
94504b96b63SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
94604b96b63SBruce Wang struct dpu_kms *dpu_kms = _dpu_crtc_get_kms(crtc);
94704b96b63SBruce Wang struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
94825fdd593SJeykumar Sankaran
94925fdd593SJeykumar Sankaran /*
95025fdd593SJeykumar Sankaran * If no mixers has been allocated in dpu_crtc_atomic_check(),
95125fdd593SJeykumar Sankaran * it means we are trying to start a CRTC whose state is disabled:
95225fdd593SJeykumar Sankaran * nothing else needs to be done.
95325fdd593SJeykumar Sankaran */
9549222cdd2SJeykumar Sankaran if (unlikely(!cstate->num_mixers))
95525fdd593SJeykumar Sankaran return;
95625fdd593SJeykumar Sankaran
95725fdd593SJeykumar Sankaran DPU_ATRACE_BEGIN("crtc_commit");
95825fdd593SJeykumar Sankaran
959f2969c49SAbhinav Kumar drm_for_each_encoder_mask(encoder, crtc->dev,
960f2969c49SAbhinav Kumar crtc->state->encoder_mask) {
961f2969c49SAbhinav Kumar if (!dpu_encoder_is_valid_for_commit(encoder)) {
962f2969c49SAbhinav Kumar DRM_DEBUG_ATOMIC("invalid FB not kicking off crtc\n");
963f2969c49SAbhinav Kumar goto end;
964f2969c49SAbhinav Kumar }
965f2969c49SAbhinav Kumar }
96625fdd593SJeykumar Sankaran /*
9674b8c6279SSean Paul * Encoder will flush/start now, unless it has a tx pending. If so, it
9684b8c6279SSean Paul * may delay and flush at an irq event (e.g. ppdone)
96925fdd593SJeykumar Sankaran */
9704b8c6279SSean Paul drm_for_each_encoder_mask(encoder, crtc->dev,
971d3db61caSBruce Wang crtc->state->encoder_mask)
9720c91ed51SRob Clark dpu_encoder_prepare_for_kickoff(encoder);
97350bcc689SSean Paul
97425fdd593SJeykumar Sankaran if (atomic_inc_return(&dpu_crtc->frame_pending) == 1) {
97525fdd593SJeykumar Sankaran /* acquire bandwidth and other resources */
9765b702d78SStephen Boyd DRM_DEBUG_ATOMIC("crtc%d first commit\n", crtc->base.id);
97725fdd593SJeykumar Sankaran } else
9785b702d78SStephen Boyd DRM_DEBUG_ATOMIC("crtc%d commit\n", crtc->base.id);
97925fdd593SJeykumar Sankaran
98025fdd593SJeykumar Sankaran dpu_crtc->play_count++;
98125fdd593SJeykumar Sankaran
98225fdd593SJeykumar Sankaran dpu_vbif_clear_errors(dpu_kms);
98325fdd593SJeykumar Sankaran
9844b8c6279SSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
985b4bb9f15SRob Clark dpu_encoder_kickoff(encoder);
98625fdd593SJeykumar Sankaran
98725fdd593SJeykumar Sankaran reinit_completion(&dpu_crtc->frame_done_comp);
988f2969c49SAbhinav Kumar
989f2969c49SAbhinav Kumar end:
99025fdd593SJeykumar Sankaran DPU_ATRACE_END("crtc_commit");
99125fdd593SJeykumar Sankaran }
99225fdd593SJeykumar Sankaran
dpu_crtc_reset(struct drm_crtc * crtc)993ff5952a7SSean Paul static void dpu_crtc_reset(struct drm_crtc *crtc)
99425fdd593SJeykumar Sankaran {
9951cff7440SMaarten Lankhorst struct dpu_crtc_state *cstate = kzalloc(sizeof(*cstate), GFP_KERNEL);
99625fdd593SJeykumar Sankaran
997ff5952a7SSean Paul if (crtc->state)
998ff5952a7SSean Paul dpu_crtc_destroy_state(crtc, crtc->state);
99925fdd593SJeykumar Sankaran
1000c96988b7SJiasheng Jiang if (cstate)
10011cff7440SMaarten Lankhorst __drm_atomic_helper_crtc_reset(crtc, &cstate->base);
1002c96988b7SJiasheng Jiang else
1003c96988b7SJiasheng Jiang __drm_atomic_helper_crtc_reset(crtc, NULL);
100425fdd593SJeykumar Sankaran }
100525fdd593SJeykumar Sankaran
100625fdd593SJeykumar Sankaran /**
100725fdd593SJeykumar Sankaran * dpu_crtc_duplicate_state - state duplicate hook
100825fdd593SJeykumar Sankaran * @crtc: Pointer to drm crtc structure
100925fdd593SJeykumar Sankaran */
dpu_crtc_duplicate_state(struct drm_crtc * crtc)101025fdd593SJeykumar Sankaran static struct drm_crtc_state *dpu_crtc_duplicate_state(struct drm_crtc *crtc)
101125fdd593SJeykumar Sankaran {
1012e12e5263SRob Clark struct dpu_crtc_state *cstate, *old_cstate = to_dpu_crtc_state(crtc->state);
101325fdd593SJeykumar Sankaran
101425fdd593SJeykumar Sankaran cstate = kmemdup(old_cstate, sizeof(*old_cstate), GFP_KERNEL);
101525fdd593SJeykumar Sankaran if (!cstate) {
101625fdd593SJeykumar Sankaran DPU_ERROR("failed to allocate state\n");
101725fdd593SJeykumar Sankaran return NULL;
101825fdd593SJeykumar Sankaran }
101925fdd593SJeykumar Sankaran
102025fdd593SJeykumar Sankaran /* duplicate base helper */
102125fdd593SJeykumar Sankaran __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base);
102225fdd593SJeykumar Sankaran
102325fdd593SJeykumar Sankaran return &cstate->base;
102425fdd593SJeykumar Sankaran }
102525fdd593SJeykumar Sankaran
dpu_crtc_atomic_print_state(struct drm_printer * p,const struct drm_crtc_state * state)102653b53337SDmitry Baryshkov static void dpu_crtc_atomic_print_state(struct drm_printer *p,
102753b53337SDmitry Baryshkov const struct drm_crtc_state *state)
102853b53337SDmitry Baryshkov {
102953b53337SDmitry Baryshkov const struct dpu_crtc_state *cstate = to_dpu_crtc_state(state);
103053b53337SDmitry Baryshkov int i;
103153b53337SDmitry Baryshkov
103253b53337SDmitry Baryshkov for (i = 0; i < cstate->num_mixers; i++) {
103353b53337SDmitry Baryshkov drm_printf(p, "\tlm[%d]=%d\n", i, cstate->mixers[i].hw_lm->idx - LM_0);
103453b53337SDmitry Baryshkov drm_printf(p, "\tctl[%d]=%d\n", i, cstate->mixers[i].lm_ctl->idx - CTL_0);
103553b53337SDmitry Baryshkov if (cstate->mixers[i].hw_dspp)
103653b53337SDmitry Baryshkov drm_printf(p, "\tdspp[%d]=%d\n", i, cstate->mixers[i].hw_dspp->idx - DSPP_0);
103753b53337SDmitry Baryshkov }
103853b53337SDmitry Baryshkov }
103953b53337SDmitry Baryshkov
dpu_crtc_disable(struct drm_crtc * crtc,struct drm_atomic_state * state)1040f7aafc8dSSean Paul static void dpu_crtc_disable(struct drm_crtc *crtc,
1041351f950dSMaxime Ripard struct drm_atomic_state *state)
104225fdd593SJeykumar Sankaran {
1043351f950dSMaxime Ripard struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1044351f950dSMaxime Ripard crtc);
1045e12e5263SRob Clark struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1046e12e5263SRob Clark struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc->state);
104725fdd593SJeykumar Sankaran struct drm_encoder *encoder;
10482f2eb723SRajesh Yadav unsigned long flags;
1049241b507cSRob Clark bool release_bandwidth = false;
105025fdd593SJeykumar Sankaran
105125fdd593SJeykumar Sankaran DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
105225fdd593SJeykumar Sankaran
1053f7e0b3c2SVinod Polimera /* If disable is triggered while in self refresh mode,
1054f7e0b3c2SVinod Polimera * reset the encoder software state so that in enable
1055f7e0b3c2SVinod Polimera * it won't trigger a warn while assigning crtc.
1056f7e0b3c2SVinod Polimera */
1057f7e0b3c2SVinod Polimera if (old_crtc_state->self_refresh_active) {
1058f7e0b3c2SVinod Polimera drm_for_each_encoder_mask(encoder, crtc->dev,
1059f7e0b3c2SVinod Polimera old_crtc_state->encoder_mask) {
1060f7e0b3c2SVinod Polimera dpu_encoder_assign_crtc(encoder, NULL);
1061f7e0b3c2SVinod Polimera }
106211226978SVinod Polimera return;
1063f7e0b3c2SVinod Polimera }
106411226978SVinod Polimera
10652f2eb723SRajesh Yadav /* Disable/save vblank irq handling */
10662f2eb723SRajesh Yadav drm_crtc_vblank_off(crtc);
10672f2eb723SRajesh Yadav
1068a796ba2cSSean Paul drm_for_each_encoder_mask(encoder, crtc->dev,
1069241b507cSRob Clark old_crtc_state->encoder_mask) {
1070241b507cSRob Clark /* in video mode, we hold an extra bandwidth reference
1071241b507cSRob Clark * as we cannot drop bandwidth at frame-done if any
1072241b507cSRob Clark * crtc is being used in video mode.
1073241b507cSRob Clark */
1074241b507cSRob Clark if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
1075241b507cSRob Clark release_bandwidth = true;
1076f7e0b3c2SVinod Polimera
1077f7e0b3c2SVinod Polimera /*
1078f7e0b3c2SVinod Polimera * If disable is triggered during psr active(e.g: screen dim in PSR),
1079f7e0b3c2SVinod Polimera * we will need encoder->crtc connection to process the device sleep &
1080f7e0b3c2SVinod Polimera * preserve it during psr sequence.
1081f7e0b3c2SVinod Polimera */
1082f7e0b3c2SVinod Polimera if (!crtc->state->self_refresh_active)
1083a796ba2cSSean Paul dpu_encoder_assign_crtc(encoder, NULL);
1084241b507cSRob Clark }
108525fdd593SJeykumar Sankaran
108625fdd593SJeykumar Sankaran /* wait for frame_event_done completion */
108725fdd593SJeykumar Sankaran if (_dpu_crtc_wait_for_frame_done(crtc))
108825fdd593SJeykumar Sankaran DPU_ERROR("crtc%d wait for frame done failed;frame_pending%d\n",
108925fdd593SJeykumar Sankaran crtc->base.id,
109025fdd593SJeykumar Sankaran atomic_read(&dpu_crtc->frame_pending));
109125fdd593SJeykumar Sankaran
109225fdd593SJeykumar Sankaran trace_dpu_crtc_disable(DRMID(crtc), false, dpu_crtc);
109325fdd593SJeykumar Sankaran dpu_crtc->enabled = false;
109425fdd593SJeykumar Sankaran
109525fdd593SJeykumar Sankaran if (atomic_read(&dpu_crtc->frame_pending)) {
109625fdd593SJeykumar Sankaran trace_dpu_crtc_disable_frame_pending(DRMID(crtc),
109725fdd593SJeykumar Sankaran atomic_read(&dpu_crtc->frame_pending));
1098241b507cSRob Clark if (release_bandwidth)
109925fdd593SJeykumar Sankaran dpu_core_perf_crtc_release_bw(crtc);
110025fdd593SJeykumar Sankaran atomic_set(&dpu_crtc->frame_pending, 0);
110125fdd593SJeykumar Sankaran }
110225fdd593SJeykumar Sankaran
1103716f0d4cSDmitry Baryshkov dpu_core_perf_crtc_update(crtc, 0);
110425fdd593SJeykumar Sankaran
11054b8c6279SSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
110625fdd593SJeykumar Sankaran dpu_encoder_register_frame_event_callback(encoder, NULL, NULL);
110725fdd593SJeykumar Sankaran
11089222cdd2SJeykumar Sankaran memset(cstate->mixers, 0, sizeof(cstate->mixers));
11099222cdd2SJeykumar Sankaran cstate->num_mixers = 0;
111025fdd593SJeykumar Sankaran
111125fdd593SJeykumar Sankaran /* disable clk & bw control until clk & bw properties are set */
111225fdd593SJeykumar Sankaran cstate->bw_control = false;
111325fdd593SJeykumar Sankaran cstate->bw_split_vote = false;
111425fdd593SJeykumar Sankaran
11152f2eb723SRajesh Yadav if (crtc->state->event && !crtc->state->active) {
11162f2eb723SRajesh Yadav spin_lock_irqsave(&crtc->dev->event_lock, flags);
11172f2eb723SRajesh Yadav drm_crtc_send_vblank_event(crtc, crtc->state->event);
11182f2eb723SRajesh Yadav crtc->state->event = NULL;
11192f2eb723SRajesh Yadav spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
11202f2eb723SRajesh Yadav }
1121b77d0f0dSSean Paul
1122b77d0f0dSSean Paul pm_runtime_put_sync(crtc->dev->dev);
112325fdd593SJeykumar Sankaran }
112425fdd593SJeykumar Sankaran
dpu_crtc_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)112525fdd593SJeykumar Sankaran static void dpu_crtc_enable(struct drm_crtc *crtc,
1126351f950dSMaxime Ripard struct drm_atomic_state *state)
112725fdd593SJeykumar Sankaran {
1128e12e5263SRob Clark struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
112925fdd593SJeykumar Sankaran struct drm_encoder *encoder;
113035c719daSRob Clark bool request_bandwidth = false;
1131f7e0b3c2SVinod Polimera struct drm_crtc_state *old_crtc_state;
1132f7e0b3c2SVinod Polimera
1133f7e0b3c2SVinod Polimera old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
113425fdd593SJeykumar Sankaran
1135b77d0f0dSSean Paul pm_runtime_get_sync(crtc->dev->dev);
1136b77d0f0dSSean Paul
113725fdd593SJeykumar Sankaran DRM_DEBUG_KMS("crtc%d\n", crtc->base.id);
113825fdd593SJeykumar Sankaran
1139241b507cSRob Clark drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask) {
1140241b507cSRob Clark /* in video mode, we hold an extra bandwidth reference
1141241b507cSRob Clark * as we cannot drop bandwidth at frame-done if any
1142241b507cSRob Clark * crtc is being used in video mode.
1143241b507cSRob Clark */
1144241b507cSRob Clark if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
1145241b507cSRob Clark request_bandwidth = true;
114625fdd593SJeykumar Sankaran dpu_encoder_register_frame_event_callback(encoder,
114725fdd593SJeykumar Sankaran dpu_crtc_frame_event_cb, (void *)crtc);
1148241b507cSRob Clark }
1149241b507cSRob Clark
1150241b507cSRob Clark if (request_bandwidth)
1151241b507cSRob Clark atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref);
115225fdd593SJeykumar Sankaran
115325fdd593SJeykumar Sankaran trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc);
115425fdd593SJeykumar Sankaran dpu_crtc->enabled = true;
115525fdd593SJeykumar Sankaran
1156f7e0b3c2SVinod Polimera if (!old_crtc_state->self_refresh_active) {
1157a796ba2cSSean Paul drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
1158a796ba2cSSean Paul dpu_encoder_assign_crtc(encoder, crtc);
1159f7e0b3c2SVinod Polimera }
116025fdd593SJeykumar Sankaran
11612f2eb723SRajesh Yadav /* Enable/restore vblank irq handling */
11622f2eb723SRajesh Yadav drm_crtc_vblank_on(crtc);
116325fdd593SJeykumar Sankaran }
116425fdd593SJeykumar Sankaran
dpu_crtc_needs_dirtyfb(struct drm_crtc_state * cstate)11659e4dde28SRob Clark static bool dpu_crtc_needs_dirtyfb(struct drm_crtc_state *cstate)
11669e4dde28SRob Clark {
11679e4dde28SRob Clark struct drm_crtc *crtc = cstate->crtc;
11689e4dde28SRob Clark struct drm_encoder *encoder;
11699e4dde28SRob Clark
1170501bd8deSVinod Polimera if (cstate->self_refresh_active)
1171501bd8deSVinod Polimera return true;
1172501bd8deSVinod Polimera
11739e4dde28SRob Clark drm_for_each_encoder_mask (encoder, crtc->dev, cstate->encoder_mask) {
11749e4dde28SRob Clark if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_CMD) {
11759e4dde28SRob Clark return true;
11769e4dde28SRob Clark }
11779e4dde28SRob Clark }
11789e4dde28SRob Clark
11799e4dde28SRob Clark return false;
11809e4dde28SRob Clark }
11819e4dde28SRob Clark
dpu_crtc_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * state)118225fdd593SJeykumar Sankaran static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
118329b77ad7SMaxime Ripard struct drm_atomic_state *state)
118425fdd593SJeykumar Sankaran {
118529b77ad7SMaxime Ripard struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
118629b77ad7SMaxime Ripard crtc);
1187e12e5263SRob Clark struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
118829b77ad7SMaxime Ripard struct dpu_crtc_state *cstate = to_dpu_crtc_state(crtc_state);
118925fdd593SJeykumar Sankaran
119025fdd593SJeykumar Sankaran const struct drm_plane_state *pstate;
119125fdd593SJeykumar Sankaran struct drm_plane *plane;
119225fdd593SJeykumar Sankaran
1193e35f68d1SDmitry Baryshkov int rc = 0;
119425fdd593SJeykumar Sankaran
11959e4dde28SRob Clark bool needs_dirtyfb = dpu_crtc_needs_dirtyfb(crtc_state);
119625fdd593SJeykumar Sankaran
1197c6c65568SVinod Polimera if (!crtc_state->enable || !drm_atomic_crtc_effectively_active(crtc_state)) {
11985b702d78SStephen Boyd DRM_DEBUG_ATOMIC("crtc%d -> enable %d, active %d, skip atomic_check\n",
119929b77ad7SMaxime Ripard crtc->base.id, crtc_state->enable,
120029b77ad7SMaxime Ripard crtc_state->active);
1201a29c8c02SKalyan Thota memset(&cstate->new_perf, 0, sizeof(cstate->new_perf));
1202e35f68d1SDmitry Baryshkov return 0;
120325fdd593SJeykumar Sankaran }
120425fdd593SJeykumar Sankaran
12055b702d78SStephen Boyd DRM_DEBUG_ATOMIC("%s: check\n", dpu_crtc->name);
120625fdd593SJeykumar Sankaran
120725fdd593SJeykumar Sankaran /* force a full mode set if active state changed */
120829b77ad7SMaxime Ripard if (crtc_state->active_changed)
120929b77ad7SMaxime Ripard crtc_state->mode_changed = true;
121025fdd593SJeykumar Sankaran
1211e35f68d1SDmitry Baryshkov if (cstate->num_mixers)
121229b77ad7SMaxime Ripard _dpu_crtc_setup_lm_bounds(crtc, crtc_state);
121325fdd593SJeykumar Sankaran
1214bbc2c7bdSDmitry Baryshkov /* FIXME: move this to dpu_plane_atomic_check? */
121529b77ad7SMaxime Ripard drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
12169e4dde28SRob Clark struct dpu_plane_state *dpu_pstate = to_dpu_plane_state(pstate);
121725fdd593SJeykumar Sankaran
121825fdd593SJeykumar Sankaran if (IS_ERR_OR_NULL(pstate)) {
121925fdd593SJeykumar Sankaran rc = PTR_ERR(pstate);
122025fdd593SJeykumar Sankaran DPU_ERROR("%s: failed to get plane%d state, %d\n",
122125fdd593SJeykumar Sankaran dpu_crtc->name, plane->base.id, rc);
1222e35f68d1SDmitry Baryshkov return rc;
122325fdd593SJeykumar Sankaran }
122425fdd593SJeykumar Sankaran
1225cb77085bSRob Clark if (!pstate->visible)
1226cb77085bSRob Clark continue;
1227cb77085bSRob Clark
12289e4dde28SRob Clark dpu_pstate->needs_dirtyfb = needs_dirtyfb;
122925fdd593SJeykumar Sankaran }
123025fdd593SJeykumar Sankaran
1231241b507cSRob Clark atomic_inc(&_dpu_crtc_get_kms(crtc)->bandwidth_ref);
1232241b507cSRob Clark
123329b77ad7SMaxime Ripard rc = dpu_core_perf_crtc_check(crtc, crtc_state);
123425fdd593SJeykumar Sankaran if (rc) {
123525fdd593SJeykumar Sankaran DPU_ERROR("crtc%d failed performance check %d\n",
123625fdd593SJeykumar Sankaran crtc->base.id, rc);
123725fdd593SJeykumar Sankaran return rc;
123825fdd593SJeykumar Sankaran }
123925fdd593SJeykumar Sankaran
1240e35f68d1SDmitry Baryshkov return 0;
1241e35f68d1SDmitry Baryshkov }
1242e35f68d1SDmitry Baryshkov
dpu_crtc_vblank(struct drm_crtc * crtc,bool en)124325fdd593SJeykumar Sankaran int dpu_crtc_vblank(struct drm_crtc *crtc, bool en)
124425fdd593SJeykumar Sankaran {
12457a007a12SBruce Wang struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
1246a796ba2cSSean Paul struct drm_encoder *enc;
124725fdd593SJeykumar Sankaran
124825fdd593SJeykumar Sankaran trace_dpu_crtc_vblank(DRMID(&dpu_crtc->base), en, dpu_crtc);
1249a796ba2cSSean Paul
1250a796ba2cSSean Paul /*
1251a796ba2cSSean Paul * Normally we would iterate through encoder_mask in crtc state to find
1252a796ba2cSSean Paul * attached encoders. In this case, we might be disabling vblank _after_
1253a796ba2cSSean Paul * encoder_mask has been cleared.
1254a796ba2cSSean Paul *
1255a796ba2cSSean Paul * Instead, we "assign" a crtc to the encoder in enable and clear it in
1256a796ba2cSSean Paul * disable (which is also after encoder_mask is cleared). So instead of
1257a796ba2cSSean Paul * using encoder mask, we'll ask the encoder to toggle itself iff it's
1258a796ba2cSSean Paul * currently assigned to our crtc.
1259a796ba2cSSean Paul *
1260a796ba2cSSean Paul * Note also that this function cannot be called while crtc is disabled
1261a796ba2cSSean Paul * since we use drm_crtc_vblank_on/off. So we don't need to worry
1262a796ba2cSSean Paul * about the assigned crtcs being inconsistent with the current state
1263a796ba2cSSean Paul * (which means no need to worry about modeset locks).
1264a796ba2cSSean Paul */
1265a796ba2cSSean Paul list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) {
1266a796ba2cSSean Paul trace_dpu_crtc_vblank_enable(DRMID(crtc), DRMID(enc), en,
1267a796ba2cSSean Paul dpu_crtc);
1268a796ba2cSSean Paul
1269a796ba2cSSean Paul dpu_encoder_toggle_vblank_for_crtc(enc, crtc, en);
127025fdd593SJeykumar Sankaran }
127125fdd593SJeykumar Sankaran
127225fdd593SJeykumar Sankaran return 0;
127325fdd593SJeykumar Sankaran }
127425fdd593SJeykumar Sankaran
127525fdd593SJeykumar Sankaran #ifdef CONFIG_DEBUG_FS
_dpu_debugfs_status_show(struct seq_file * s,void * data)127625fdd593SJeykumar Sankaran static int _dpu_debugfs_status_show(struct seq_file *s, void *data)
127725fdd593SJeykumar Sankaran {
127825fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc;
127925fdd593SJeykumar Sankaran struct dpu_plane_state *pstate = NULL;
128025fdd593SJeykumar Sankaran struct dpu_crtc_mixer *m;
128125fdd593SJeykumar Sankaran
128225fdd593SJeykumar Sankaran struct drm_crtc *crtc;
128325fdd593SJeykumar Sankaran struct drm_plane *plane;
128425fdd593SJeykumar Sankaran struct drm_display_mode *mode;
128525fdd593SJeykumar Sankaran struct drm_framebuffer *fb;
128625fdd593SJeykumar Sankaran struct drm_plane_state *state;
128725fdd593SJeykumar Sankaran struct dpu_crtc_state *cstate;
128825fdd593SJeykumar Sankaran
128925fdd593SJeykumar Sankaran int i, out_width;
129025fdd593SJeykumar Sankaran
129125fdd593SJeykumar Sankaran dpu_crtc = s->private;
129225fdd593SJeykumar Sankaran crtc = &dpu_crtc->base;
12939222cdd2SJeykumar Sankaran
12949222cdd2SJeykumar Sankaran drm_modeset_lock_all(crtc->dev);
129525fdd593SJeykumar Sankaran cstate = to_dpu_crtc_state(crtc->state);
129625fdd593SJeykumar Sankaran
129725fdd593SJeykumar Sankaran mode = &crtc->state->adjusted_mode;
12983804a982SJordan Crouse out_width = mode->hdisplay / cstate->num_mixers;
129925fdd593SJeykumar Sankaran
130025fdd593SJeykumar Sankaran seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id,
130125fdd593SJeykumar Sankaran mode->hdisplay, mode->vdisplay);
130225fdd593SJeykumar Sankaran
130325fdd593SJeykumar Sankaran seq_puts(s, "\n");
130425fdd593SJeykumar Sankaran
13059222cdd2SJeykumar Sankaran for (i = 0; i < cstate->num_mixers; ++i) {
13069222cdd2SJeykumar Sankaran m = &cstate->mixers[i];
130725fdd593SJeykumar Sankaran seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n",
1308cf6916f4SJeykumar Sankaran m->hw_lm->idx - LM_0, m->lm_ctl->idx - CTL_0,
130925fdd593SJeykumar Sankaran out_width, mode->vdisplay);
131025fdd593SJeykumar Sankaran }
131125fdd593SJeykumar Sankaran
131225fdd593SJeykumar Sankaran seq_puts(s, "\n");
131325fdd593SJeykumar Sankaran
131425fdd593SJeykumar Sankaran drm_atomic_crtc_for_each_plane(plane, crtc) {
131525fdd593SJeykumar Sankaran pstate = to_dpu_plane_state(plane->state);
131625fdd593SJeykumar Sankaran state = plane->state;
131725fdd593SJeykumar Sankaran
131825fdd593SJeykumar Sankaran if (!pstate || !state)
131925fdd593SJeykumar Sankaran continue;
132025fdd593SJeykumar Sankaran
132125fdd593SJeykumar Sankaran seq_printf(s, "\tplane:%u stage:%d\n", plane->base.id,
132225fdd593SJeykumar Sankaran pstate->stage);
132325fdd593SJeykumar Sankaran
132425fdd593SJeykumar Sankaran if (plane->state->fb) {
132525fdd593SJeykumar Sankaran fb = plane->state->fb;
132625fdd593SJeykumar Sankaran
132725fdd593SJeykumar Sankaran seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u ",
132825fdd593SJeykumar Sankaran fb->base.id, (char *) &fb->format->format,
132925fdd593SJeykumar Sankaran fb->width, fb->height);
133025fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(fb->format->cpp); ++i)
133125fdd593SJeykumar Sankaran seq_printf(s, "cpp[%d]:%u ",
133225fdd593SJeykumar Sankaran i, fb->format->cpp[i]);
133325fdd593SJeykumar Sankaran seq_puts(s, "\n\t");
133425fdd593SJeykumar Sankaran
133525fdd593SJeykumar Sankaran seq_printf(s, "modifier:%8llu ", fb->modifier);
133625fdd593SJeykumar Sankaran seq_puts(s, "\n");
133725fdd593SJeykumar Sankaran
133825fdd593SJeykumar Sankaran seq_puts(s, "\t");
133925fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(fb->pitches); i++)
134025fdd593SJeykumar Sankaran seq_printf(s, "pitches[%d]:%8u ", i,
134125fdd593SJeykumar Sankaran fb->pitches[i]);
134225fdd593SJeykumar Sankaran seq_puts(s, "\n");
134325fdd593SJeykumar Sankaran
134425fdd593SJeykumar Sankaran seq_puts(s, "\t");
134525fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(fb->offsets); i++)
134625fdd593SJeykumar Sankaran seq_printf(s, "offsets[%d]:%8u ", i,
134725fdd593SJeykumar Sankaran fb->offsets[i]);
134825fdd593SJeykumar Sankaran seq_puts(s, "\n");
134925fdd593SJeykumar Sankaran }
135025fdd593SJeykumar Sankaran
135125fdd593SJeykumar Sankaran seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n",
135225fdd593SJeykumar Sankaran state->src_x, state->src_y, state->src_w, state->src_h);
135325fdd593SJeykumar Sankaran
135425fdd593SJeykumar Sankaran seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n",
135525fdd593SJeykumar Sankaran state->crtc_x, state->crtc_y, state->crtc_w,
135625fdd593SJeykumar Sankaran state->crtc_h);
135780e8ae3bSDmitry Baryshkov seq_printf(s, "\tsspp[0]:%s\n",
1358dc0b5a61SDmitry Baryshkov pstate->pipe.sspp->cap->name);
135980e8ae3bSDmitry Baryshkov seq_printf(s, "\tmultirect[0]: mode: %d index: %d\n",
13603cfcd130SDmitry Baryshkov pstate->pipe.multirect_mode, pstate->pipe.multirect_index);
136180e8ae3bSDmitry Baryshkov if (pstate->r_pipe.sspp) {
136280e8ae3bSDmitry Baryshkov seq_printf(s, "\tsspp[1]:%s\n",
136380e8ae3bSDmitry Baryshkov pstate->r_pipe.sspp->cap->name);
136480e8ae3bSDmitry Baryshkov seq_printf(s, "\tmultirect[1]: mode: %d index: %d\n",
136580e8ae3bSDmitry Baryshkov pstate->r_pipe.multirect_mode, pstate->r_pipe.multirect_index);
136680e8ae3bSDmitry Baryshkov }
136725fdd593SJeykumar Sankaran
136825fdd593SJeykumar Sankaran seq_puts(s, "\n");
136925fdd593SJeykumar Sankaran }
137025fdd593SJeykumar Sankaran if (dpu_crtc->vblank_cb_count) {
137125fdd593SJeykumar Sankaran ktime_t diff = ktime_sub(ktime_get(), dpu_crtc->vblank_cb_time);
137225fdd593SJeykumar Sankaran s64 diff_ms = ktime_to_ms(diff);
137325fdd593SJeykumar Sankaran s64 fps = diff_ms ? div_s64(
137425fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_count * 1000, diff_ms) : 0;
137525fdd593SJeykumar Sankaran
137625fdd593SJeykumar Sankaran seq_printf(s,
137725fdd593SJeykumar Sankaran "vblank fps:%lld count:%u total:%llums total_framecount:%llu\n",
137825fdd593SJeykumar Sankaran fps, dpu_crtc->vblank_cb_count,
137925fdd593SJeykumar Sankaran ktime_to_ms(diff), dpu_crtc->play_count);
138025fdd593SJeykumar Sankaran
138125fdd593SJeykumar Sankaran /* reset time & count for next measurement */
138225fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_count = 0;
138325fdd593SJeykumar Sankaran dpu_crtc->vblank_cb_time = ktime_set(0, 0);
138425fdd593SJeykumar Sankaran }
138525fdd593SJeykumar Sankaran
13869222cdd2SJeykumar Sankaran drm_modeset_unlock_all(crtc->dev);
138725fdd593SJeykumar Sankaran
138825fdd593SJeykumar Sankaran return 0;
138925fdd593SJeykumar Sankaran }
139025fdd593SJeykumar Sankaran
1391341a361cSQinglang Miao DEFINE_SHOW_ATTRIBUTE(_dpu_debugfs_status);
139225fdd593SJeykumar Sankaran
dpu_crtc_debugfs_state_show(struct seq_file * s,void * v)139325fdd593SJeykumar Sankaran static int dpu_crtc_debugfs_state_show(struct seq_file *s, void *v)
139425fdd593SJeykumar Sankaran {
1395eea9cf72SSu Hui struct drm_crtc *crtc = s->private;
139625fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
139725fdd593SJeykumar Sankaran
139825fdd593SJeykumar Sankaran seq_printf(s, "client type: %d\n", dpu_crtc_get_client_type(crtc));
139925fdd593SJeykumar Sankaran seq_printf(s, "intf_mode: %d\n", dpu_crtc_get_intf_mode(crtc));
140025fdd593SJeykumar Sankaran seq_printf(s, "core_clk_rate: %llu\n",
140125fdd593SJeykumar Sankaran dpu_crtc->cur_perf.core_clk_rate);
1402cb88482eSJayant Shekhar seq_printf(s, "bw_ctl: %llu\n", dpu_crtc->cur_perf.bw_ctl);
1403cb88482eSJayant Shekhar seq_printf(s, "max_per_pipe_ib: %llu\n",
1404cb88482eSJayant Shekhar dpu_crtc->cur_perf.max_per_pipe_ib);
140525fdd593SJeykumar Sankaran
140625fdd593SJeykumar Sankaran return 0;
140725fdd593SJeykumar Sankaran }
1408341a361cSQinglang Miao DEFINE_SHOW_ATTRIBUTE(dpu_crtc_debugfs_state);
140925fdd593SJeykumar Sankaran
_dpu_crtc_init_debugfs(struct drm_crtc * crtc)141025fdd593SJeykumar Sankaran static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc)
141125fdd593SJeykumar Sankaran {
14123d688410SJordan Crouse struct dpu_crtc *dpu_crtc = to_dpu_crtc(crtc);
141325fdd593SJeykumar Sankaran
141425fdd593SJeykumar Sankaran debugfs_create_file("status", 0400,
1415f377ea2cSDmitry Baryshkov crtc->debugfs_entry,
1416341a361cSQinglang Miao dpu_crtc, &_dpu_debugfs_status_fops);
141725fdd593SJeykumar Sankaran debugfs_create_file("state", 0600,
1418f377ea2cSDmitry Baryshkov crtc->debugfs_entry,
141925fdd593SJeykumar Sankaran &dpu_crtc->base,
142025fdd593SJeykumar Sankaran &dpu_crtc_debugfs_state_fops);
142125fdd593SJeykumar Sankaran
142225fdd593SJeykumar Sankaran return 0;
142325fdd593SJeykumar Sankaran }
142425fdd593SJeykumar Sankaran #else
_dpu_crtc_init_debugfs(struct drm_crtc * crtc)142525fdd593SJeykumar Sankaran static int _dpu_crtc_init_debugfs(struct drm_crtc *crtc)
142625fdd593SJeykumar Sankaran {
142725fdd593SJeykumar Sankaran return 0;
142825fdd593SJeykumar Sankaran }
142925fdd593SJeykumar Sankaran #endif /* CONFIG_DEBUG_FS */
143025fdd593SJeykumar Sankaran
dpu_crtc_late_register(struct drm_crtc * crtc)143125fdd593SJeykumar Sankaran static int dpu_crtc_late_register(struct drm_crtc *crtc)
143225fdd593SJeykumar Sankaran {
143325fdd593SJeykumar Sankaran return _dpu_crtc_init_debugfs(crtc);
143425fdd593SJeykumar Sankaran }
143525fdd593SJeykumar Sankaran
143625fdd593SJeykumar Sankaran static const struct drm_crtc_funcs dpu_crtc_funcs = {
143725fdd593SJeykumar Sankaran .set_config = drm_atomic_helper_set_config,
143825fdd593SJeykumar Sankaran .destroy = dpu_crtc_destroy,
143925fdd593SJeykumar Sankaran .page_flip = drm_atomic_helper_page_flip,
144025fdd593SJeykumar Sankaran .reset = dpu_crtc_reset,
144125fdd593SJeykumar Sankaran .atomic_duplicate_state = dpu_crtc_duplicate_state,
144225fdd593SJeykumar Sankaran .atomic_destroy_state = dpu_crtc_destroy_state,
144353b53337SDmitry Baryshkov .atomic_print_state = dpu_crtc_atomic_print_state,
144425fdd593SJeykumar Sankaran .late_register = dpu_crtc_late_register,
144578d9b458SJessica Zhang .verify_crc_source = dpu_crtc_verify_crc_source,
144678d9b458SJessica Zhang .set_crc_source = dpu_crtc_set_crc_source,
144776e8cfd8SThomas Zimmermann .enable_vblank = msm_crtc_enable_vblank,
144876e8cfd8SThomas Zimmermann .disable_vblank = msm_crtc_disable_vblank,
144973743e72SKalyan Thota .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
145073743e72SKalyan Thota .get_vblank_counter = dpu_crtc_get_vblank_counter,
145125fdd593SJeykumar Sankaran };
145225fdd593SJeykumar Sankaran
145325fdd593SJeykumar Sankaran static const struct drm_crtc_helper_funcs dpu_crtc_helper_funcs = {
1454f7aafc8dSSean Paul .atomic_disable = dpu_crtc_disable,
145525fdd593SJeykumar Sankaran .atomic_enable = dpu_crtc_enable,
145625fdd593SJeykumar Sankaran .atomic_check = dpu_crtc_atomic_check,
145725fdd593SJeykumar Sankaran .atomic_begin = dpu_crtc_atomic_begin,
145825fdd593SJeykumar Sankaran .atomic_flush = dpu_crtc_atomic_flush,
145973743e72SKalyan Thota .get_scanout_position = dpu_crtc_get_scanout_position,
146025fdd593SJeykumar Sankaran };
146125fdd593SJeykumar Sankaran
146225fdd593SJeykumar Sankaran /* initialize crtc */
dpu_crtc_init(struct drm_device * dev,struct drm_plane * plane,struct drm_plane * cursor)146307ca1fc0SSravanthi Kollukuduru struct drm_crtc *dpu_crtc_init(struct drm_device *dev, struct drm_plane *plane,
146407ca1fc0SSravanthi Kollukuduru struct drm_plane *cursor)
146525fdd593SJeykumar Sankaran {
14663bcfc7b9SDmitry Baryshkov struct msm_drm_private *priv = dev->dev_private;
14673bcfc7b9SDmitry Baryshkov struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
146825fdd593SJeykumar Sankaran struct drm_crtc *crtc = NULL;
146925fdd593SJeykumar Sankaran struct dpu_crtc *dpu_crtc = NULL;
147011226978SVinod Polimera int i, ret;
147125fdd593SJeykumar Sankaran
147225fdd593SJeykumar Sankaran dpu_crtc = kzalloc(sizeof(*dpu_crtc), GFP_KERNEL);
147325fdd593SJeykumar Sankaran if (!dpu_crtc)
147425fdd593SJeykumar Sankaran return ERR_PTR(-ENOMEM);
147525fdd593SJeykumar Sankaran
147625fdd593SJeykumar Sankaran crtc = &dpu_crtc->base;
147725fdd593SJeykumar Sankaran crtc->dev = dev;
147825fdd593SJeykumar Sankaran
147925fdd593SJeykumar Sankaran spin_lock_init(&dpu_crtc->spin_lock);
148025fdd593SJeykumar Sankaran atomic_set(&dpu_crtc->frame_pending, 0);
148125fdd593SJeykumar Sankaran
148225fdd593SJeykumar Sankaran init_completion(&dpu_crtc->frame_done_comp);
148325fdd593SJeykumar Sankaran
148425fdd593SJeykumar Sankaran INIT_LIST_HEAD(&dpu_crtc->frame_event_list);
148525fdd593SJeykumar Sankaran
148625fdd593SJeykumar Sankaran for (i = 0; i < ARRAY_SIZE(dpu_crtc->frame_events); i++) {
148725fdd593SJeykumar Sankaran INIT_LIST_HEAD(&dpu_crtc->frame_events[i].list);
148825fdd593SJeykumar Sankaran list_add(&dpu_crtc->frame_events[i].list,
148925fdd593SJeykumar Sankaran &dpu_crtc->frame_event_list);
149025fdd593SJeykumar Sankaran kthread_init_work(&dpu_crtc->frame_events[i].work,
149125fdd593SJeykumar Sankaran dpu_crtc_frame_event_work);
149225fdd593SJeykumar Sankaran }
149325fdd593SJeykumar Sankaran
149407ca1fc0SSravanthi Kollukuduru drm_crtc_init_with_planes(dev, crtc, plane, cursor, &dpu_crtc_funcs,
149525fdd593SJeykumar Sankaran NULL);
149625fdd593SJeykumar Sankaran
149725fdd593SJeykumar Sankaran drm_crtc_helper_add(crtc, &dpu_crtc_helper_funcs);
149825fdd593SJeykumar Sankaran
14993bcfc7b9SDmitry Baryshkov if (dpu_kms->catalog->dspp_count)
15004259ff7aSKalyan Thota drm_crtc_enable_color_mgmt(crtc, 0, true, 0);
15014259ff7aSKalyan Thota
150225fdd593SJeykumar Sankaran /* save user friendly CRTC name for later */
150325fdd593SJeykumar Sankaran snprintf(dpu_crtc->name, DPU_CRTC_NAME_SIZE, "crtc%u", crtc->base.id);
150425fdd593SJeykumar Sankaran
150525fdd593SJeykumar Sankaran /* initialize event handling */
1506c17aeda0SJordan Crouse spin_lock_init(&dpu_crtc->event_lock);
150725fdd593SJeykumar Sankaran
150811226978SVinod Polimera ret = drm_self_refresh_helper_init(crtc);
150911226978SVinod Polimera if (ret) {
151011226978SVinod Polimera DPU_ERROR("Failed to initialize %s with self-refresh helpers %d\n",
151111226978SVinod Polimera crtc->name, ret);
151211226978SVinod Polimera return ERR_PTR(ret);
151311226978SVinod Polimera }
151411226978SVinod Polimera
15155b702d78SStephen Boyd DRM_DEBUG_KMS("%s: successfully initialized crtc\n", dpu_crtc->name);
151625fdd593SJeykumar Sankaran return crtc;
151725fdd593SJeykumar Sankaran }
1518