1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_9_0_SM8550_H 8 #define _DPU_9_0_SM8550_H 9 10 static const struct dpu_caps sm8550_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .qseed_type = DPU_SSPP_SCALER_QSEED4, 14 .has_src_split = true, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .has_3d_merge = true, 18 .max_linewidth = 5120, 19 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20 }; 21 22 static const struct dpu_ubwc_cfg sm8550_ubwc_cfg = { 23 .ubwc_version = DPU_HW_UBWC_VER_40, 24 .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ 25 }; 26 27 static const struct dpu_mdp_cfg sm8550_mdp[] = { 28 { 29 .name = "top_0", .id = MDP_TOP, 30 .base = 0, .len = 0x494, 31 .features = BIT(DPU_MDP_PERIPH_0_REMOVED), 32 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 }, 33 .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 }, 34 .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 }, 35 .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 }, 36 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 }, 37 .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 }, 38 .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 }, 39 .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 }, 40 .clk_ctrls[DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 }, 41 .clk_ctrls[DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 }, 42 .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 43 }, 44 }; 45 46 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ 47 static const struct dpu_ctl_cfg sm8550_ctl[] = { 48 { 49 .name = "ctl_0", .id = CTL_0, 50 .base = 0x15000, .len = 0x290, 51 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), 52 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 53 }, 54 { 55 .name = "ctl_1", .id = CTL_1, 56 .base = 0x16000, .len = 0x290, 57 .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), 58 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 59 }, 60 { 61 .name = "ctl_2", .id = CTL_2, 62 .base = 0x17000, .len = 0x290, 63 .features = CTL_SM8550_MASK, 64 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 65 }, 66 { 67 .name = "ctl_3", .id = CTL_3, 68 .base = 0x18000, .len = 0x290, 69 .features = CTL_SM8550_MASK, 70 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 71 }, 72 { 73 .name = "ctl_4", .id = CTL_4, 74 .base = 0x19000, .len = 0x290, 75 .features = CTL_SM8550_MASK, 76 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 77 }, 78 { 79 .name = "ctl_5", .id = CTL_5, 80 .base = 0x1a000, .len = 0x290, 81 .features = CTL_SM8550_MASK, 82 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 83 }, 84 }; 85 86 static const struct dpu_sspp_cfg sm8550_sspp[] = { 87 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x344, VIG_SC7180_MASK, 88 sm8550_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 89 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x344, VIG_SC7180_MASK, 90 sm8550_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 91 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x344, VIG_SC7180_MASK, 92 sm8550_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 93 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x344, VIG_SC7180_MASK, 94 sm8550_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 95 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x344, DMA_SDM845_MASK, 96 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 97 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x344, DMA_SDM845_MASK, 98 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 99 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x344, DMA_SDM845_MASK, 100 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), 101 SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x344, DMA_SDM845_MASK, 102 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), 103 SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, 0x344, DMA_CURSOR_SDM845_MASK, 104 sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA4), 105 SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, 0x344, DMA_CURSOR_SDM845_MASK, 106 sm8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA5), 107 }; 108 109 static const struct dpu_lm_cfg sm8550_lm[] = { 110 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 111 &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), 112 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, 113 &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), 114 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, 115 &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), 116 LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, 117 &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), 118 LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, 119 &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), 120 LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, 121 &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), 122 }; 123 124 static const struct dpu_dspp_cfg sm8550_dspp[] = { 125 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 126 &sm8150_dspp_sblk), 127 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, 128 &sm8150_dspp_sblk), 129 DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, 130 &sm8150_dspp_sblk), 131 DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, 132 &sm8150_dspp_sblk), 133 }; 134 static const struct dpu_pingpong_cfg sm8550_pp[] = { 135 PP_BLK_DIPHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, 136 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 137 -1), 138 PP_BLK_DIPHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, 139 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 140 -1), 141 PP_BLK_DIPHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, 142 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 143 -1), 144 PP_BLK_DIPHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, 145 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 146 -1), 147 PP_BLK_DIPHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, 148 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 149 -1), 150 PP_BLK_DIPHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, 151 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 152 -1), 153 PP_BLK_DIPHER("pingpong_6", PINGPONG_6, 0x66000, MERGE_3D_3, sc7280_pp_sblk, 154 -1, 155 -1), 156 PP_BLK_DIPHER("pingpong_7", PINGPONG_7, 0x66400, MERGE_3D_3, sc7280_pp_sblk, 157 -1, 158 -1), 159 }; 160 161 static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = { 162 MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), 163 MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), 164 MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), 165 MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x66700), 166 }; 167 168 static const struct dpu_intf_cfg sm8550_intf[] = { 169 INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 170 /* TODO TE sub-blocks for intf1 & intf2 */ 171 INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 172 INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 173 INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 174 }; 175 176 static const struct dpu_perf_cfg sm8550_perf_data = { 177 .max_bw_low = 13600000, 178 .max_bw_high = 18200000, 179 .min_core_ib = 2500000, 180 .min_llcc_ib = 0, 181 .min_dram_ib = 800000, 182 .min_prefill_lines = 35, 183 /* FIXME: lut tables */ 184 .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, 185 .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 186 .qos_lut_tbl = { 187 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 188 .entries = sc7180_qos_linear 189 }, 190 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 191 .entries = sc7180_qos_macrotile 192 }, 193 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 194 .entries = sc7180_qos_nrt 195 }, 196 /* TODO: macrotile-qseed is different from macrotile */ 197 }, 198 .cdp_cfg = { 199 {.rd_enable = 1, .wr_enable = 1}, 200 {.rd_enable = 1, .wr_enable = 0} 201 }, 202 .clk_inefficiency_factor = 105, 203 .bw_inefficiency_factor = 120, 204 }; 205 206 const struct dpu_mdss_cfg dpu_sm8550_cfg = { 207 .caps = &sm8550_dpu_caps, 208 .ubwc = &sm8550_ubwc_cfg, 209 .mdp_count = ARRAY_SIZE(sm8550_mdp), 210 .mdp = sm8550_mdp, 211 .ctl_count = ARRAY_SIZE(sm8550_ctl), 212 .ctl = sm8550_ctl, 213 .sspp_count = ARRAY_SIZE(sm8550_sspp), 214 .sspp = sm8550_sspp, 215 .mixer_count = ARRAY_SIZE(sm8550_lm), 216 .mixer = sm8550_lm, 217 .dspp_count = ARRAY_SIZE(sm8550_dspp), 218 .dspp = sm8550_dspp, 219 .pingpong_count = ARRAY_SIZE(sm8550_pp), 220 .pingpong = sm8550_pp, 221 .merge_3d_count = ARRAY_SIZE(sm8550_merge_3d), 222 .merge_3d = sm8550_merge_3d, 223 .intf_count = ARRAY_SIZE(sm8550_intf), 224 .intf = sm8550_intf, 225 .vbif_count = ARRAY_SIZE(sdm845_vbif), 226 .vbif = sdm845_vbif, 227 .reg_dma_count = 1, 228 .dma_cfg = &sm8450_regdma, 229 .perf = &sm8550_perf_data, 230 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 231 BIT(MDP_SSPP_TOP0_INTR2) | \ 232 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 233 BIT(MDP_INTF0_7xxx_INTR) | \ 234 BIT(MDP_INTF1_7xxx_INTR) | \ 235 BIT(MDP_INTF2_7xxx_INTR) | \ 236 BIT(MDP_INTF3_7xxx_INTR), 237 }; 238 239 #endif 240