1*9cc54793SDmitry Baryshkov /* SPDX-License-Identifier: GPL-2.0-only */ 2*9cc54793SDmitry Baryshkov /* 3*9cc54793SDmitry Baryshkov * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4*9cc54793SDmitry Baryshkov * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5*9cc54793SDmitry Baryshkov */ 6*9cc54793SDmitry Baryshkov 7*9cc54793SDmitry Baryshkov #ifndef _DPU_9_0_SM8550_H 8*9cc54793SDmitry Baryshkov #define _DPU_9_0_SM8550_H 9*9cc54793SDmitry Baryshkov 10*9cc54793SDmitry Baryshkov static const struct dpu_caps sm8550_dpu_caps = { 11*9cc54793SDmitry Baryshkov .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12*9cc54793SDmitry Baryshkov .max_mixer_blendstages = 0xb, 13*9cc54793SDmitry Baryshkov .qseed_type = DPU_SSPP_SCALER_QSEED4, 14*9cc54793SDmitry Baryshkov .has_src_split = true, 15*9cc54793SDmitry Baryshkov .has_dim_layer = true, 16*9cc54793SDmitry Baryshkov .has_idle_pc = true, 17*9cc54793SDmitry Baryshkov .has_3d_merge = true, 18*9cc54793SDmitry Baryshkov .max_linewidth = 5120, 19*9cc54793SDmitry Baryshkov .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20*9cc54793SDmitry Baryshkov }; 21*9cc54793SDmitry Baryshkov 22*9cc54793SDmitry Baryshkov static const struct dpu_ubwc_cfg sm8550_ubwc_cfg = { 23*9cc54793SDmitry Baryshkov .ubwc_version = DPU_HW_UBWC_VER_40, 24*9cc54793SDmitry Baryshkov .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ 25*9cc54793SDmitry Baryshkov }; 26*9cc54793SDmitry Baryshkov 27*9cc54793SDmitry Baryshkov static const struct dpu_mdp_cfg sm8550_mdp[] = { 28*9cc54793SDmitry Baryshkov { 29*9cc54793SDmitry Baryshkov .name = "top_0", .id = MDP_TOP, 30*9cc54793SDmitry Baryshkov .base = 0, .len = 0x494, 31*9cc54793SDmitry Baryshkov .features = BIT(DPU_MDP_PERIPH_0_REMOVED), 32*9cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 }, 33*9cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 }, 34*9cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 }, 35*9cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 }, 36*9cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 }, 37*9cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 }, 38*9cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 }, 39*9cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 }, 40*9cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 }, 41*9cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 }, 42*9cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 43*9cc54793SDmitry Baryshkov }, 44*9cc54793SDmitry Baryshkov }; 45*9cc54793SDmitry Baryshkov 46*9cc54793SDmitry Baryshkov static const struct dpu_ctl_cfg sm8550_ctl[] = { 47*9cc54793SDmitry Baryshkov { 48*9cc54793SDmitry Baryshkov .name = "ctl_0", .id = CTL_0, 49*9cc54793SDmitry Baryshkov .base = 0x15000, .len = 0x290, 50*9cc54793SDmitry Baryshkov .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), 51*9cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 52*9cc54793SDmitry Baryshkov }, 53*9cc54793SDmitry Baryshkov { 54*9cc54793SDmitry Baryshkov .name = "ctl_1", .id = CTL_1, 55*9cc54793SDmitry Baryshkov .base = 0x16000, .len = 0x290, 56*9cc54793SDmitry Baryshkov .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), 57*9cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 58*9cc54793SDmitry Baryshkov }, 59*9cc54793SDmitry Baryshkov { 60*9cc54793SDmitry Baryshkov .name = "ctl_2", .id = CTL_2, 61*9cc54793SDmitry Baryshkov .base = 0x17000, .len = 0x290, 62*9cc54793SDmitry Baryshkov .features = CTL_SM8550_MASK, 63*9cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 64*9cc54793SDmitry Baryshkov }, 65*9cc54793SDmitry Baryshkov { 66*9cc54793SDmitry Baryshkov .name = "ctl_3", .id = CTL_3, 67*9cc54793SDmitry Baryshkov .base = 0x18000, .len = 0x290, 68*9cc54793SDmitry Baryshkov .features = CTL_SM8550_MASK, 69*9cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 70*9cc54793SDmitry Baryshkov }, 71*9cc54793SDmitry Baryshkov { 72*9cc54793SDmitry Baryshkov .name = "ctl_4", .id = CTL_4, 73*9cc54793SDmitry Baryshkov .base = 0x19000, .len = 0x290, 74*9cc54793SDmitry Baryshkov .features = CTL_SM8550_MASK, 75*9cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 76*9cc54793SDmitry Baryshkov }, 77*9cc54793SDmitry Baryshkov { 78*9cc54793SDmitry Baryshkov .name = "ctl_5", .id = CTL_5, 79*9cc54793SDmitry Baryshkov .base = 0x1a000, .len = 0x290, 80*9cc54793SDmitry Baryshkov .features = CTL_SM8550_MASK, 81*9cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 82*9cc54793SDmitry Baryshkov }, 83*9cc54793SDmitry Baryshkov }; 84*9cc54793SDmitry Baryshkov 85*9cc54793SDmitry Baryshkov static const struct dpu_sspp_cfg sm8550_sspp[] = { 86*9cc54793SDmitry Baryshkov SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x344, VIG_SC7180_MASK, 87*9cc54793SDmitry Baryshkov sm8550_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 88*9cc54793SDmitry Baryshkov SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x344, VIG_SC7180_MASK, 89*9cc54793SDmitry Baryshkov sm8550_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 90*9cc54793SDmitry Baryshkov SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x344, VIG_SC7180_MASK, 91*9cc54793SDmitry Baryshkov sm8550_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 92*9cc54793SDmitry Baryshkov SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x344, VIG_SC7180_MASK, 93*9cc54793SDmitry Baryshkov sm8550_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 94*9cc54793SDmitry Baryshkov SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x344, DMA_SDM845_MASK, 95*9cc54793SDmitry Baryshkov sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 96*9cc54793SDmitry Baryshkov SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x344, DMA_SDM845_MASK, 97*9cc54793SDmitry Baryshkov sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 98*9cc54793SDmitry Baryshkov SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x344, DMA_SDM845_MASK, 99*9cc54793SDmitry Baryshkov sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), 100*9cc54793SDmitry Baryshkov SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x344, DMA_SDM845_MASK, 101*9cc54793SDmitry Baryshkov sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), 102*9cc54793SDmitry Baryshkov SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, 0x344, DMA_CURSOR_SDM845_MASK, 103*9cc54793SDmitry Baryshkov sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA4), 104*9cc54793SDmitry Baryshkov SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, 0x344, DMA_CURSOR_SDM845_MASK, 105*9cc54793SDmitry Baryshkov sm8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA5), 106*9cc54793SDmitry Baryshkov }; 107*9cc54793SDmitry Baryshkov 108*9cc54793SDmitry Baryshkov static const struct dpu_pingpong_cfg sm8550_pp[] = { 109*9cc54793SDmitry Baryshkov PP_BLK_DIPHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, 110*9cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 111*9cc54793SDmitry Baryshkov -1), 112*9cc54793SDmitry Baryshkov PP_BLK_DIPHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, 113*9cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 114*9cc54793SDmitry Baryshkov -1), 115*9cc54793SDmitry Baryshkov PP_BLK_DIPHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, 116*9cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 117*9cc54793SDmitry Baryshkov -1), 118*9cc54793SDmitry Baryshkov PP_BLK_DIPHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, 119*9cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 120*9cc54793SDmitry Baryshkov -1), 121*9cc54793SDmitry Baryshkov PP_BLK_DIPHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, 122*9cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 123*9cc54793SDmitry Baryshkov -1), 124*9cc54793SDmitry Baryshkov PP_BLK_DIPHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, 125*9cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 126*9cc54793SDmitry Baryshkov -1), 127*9cc54793SDmitry Baryshkov PP_BLK_DIPHER("pingpong_6", PINGPONG_6, 0x66000, MERGE_3D_3, sc7280_pp_sblk, 128*9cc54793SDmitry Baryshkov -1, 129*9cc54793SDmitry Baryshkov -1), 130*9cc54793SDmitry Baryshkov PP_BLK_DIPHER("pingpong_7", PINGPONG_7, 0x66400, MERGE_3D_3, sc7280_pp_sblk, 131*9cc54793SDmitry Baryshkov -1, 132*9cc54793SDmitry Baryshkov -1), 133*9cc54793SDmitry Baryshkov }; 134*9cc54793SDmitry Baryshkov 135*9cc54793SDmitry Baryshkov static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = { 136*9cc54793SDmitry Baryshkov MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), 137*9cc54793SDmitry Baryshkov MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), 138*9cc54793SDmitry Baryshkov MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), 139*9cc54793SDmitry Baryshkov MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x66700), 140*9cc54793SDmitry Baryshkov }; 141*9cc54793SDmitry Baryshkov 142*9cc54793SDmitry Baryshkov static const struct dpu_intf_cfg sm8550_intf[] = { 143*9cc54793SDmitry Baryshkov INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 144*9cc54793SDmitry Baryshkov /* TODO TE sub-blocks for intf1 & intf2 */ 145*9cc54793SDmitry Baryshkov INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 146*9cc54793SDmitry Baryshkov INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 147*9cc54793SDmitry Baryshkov INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 148*9cc54793SDmitry Baryshkov }; 149*9cc54793SDmitry Baryshkov 150*9cc54793SDmitry Baryshkov static const struct dpu_mdss_cfg sm8550_dpu_cfg = { 151*9cc54793SDmitry Baryshkov .caps = &sm8550_dpu_caps, 152*9cc54793SDmitry Baryshkov .ubwc = &sm8550_ubwc_cfg, 153*9cc54793SDmitry Baryshkov .mdp_count = ARRAY_SIZE(sm8550_mdp), 154*9cc54793SDmitry Baryshkov .mdp = sm8550_mdp, 155*9cc54793SDmitry Baryshkov .ctl_count = ARRAY_SIZE(sm8550_ctl), 156*9cc54793SDmitry Baryshkov .ctl = sm8550_ctl, 157*9cc54793SDmitry Baryshkov .sspp_count = ARRAY_SIZE(sm8550_sspp), 158*9cc54793SDmitry Baryshkov .sspp = sm8550_sspp, 159*9cc54793SDmitry Baryshkov .mixer_count = ARRAY_SIZE(sm8150_lm), 160*9cc54793SDmitry Baryshkov .mixer = sm8150_lm, 161*9cc54793SDmitry Baryshkov .dspp_count = ARRAY_SIZE(sm8150_dspp), 162*9cc54793SDmitry Baryshkov .dspp = sm8150_dspp, 163*9cc54793SDmitry Baryshkov .pingpong_count = ARRAY_SIZE(sm8550_pp), 164*9cc54793SDmitry Baryshkov .pingpong = sm8550_pp, 165*9cc54793SDmitry Baryshkov .merge_3d_count = ARRAY_SIZE(sm8550_merge_3d), 166*9cc54793SDmitry Baryshkov .merge_3d = sm8550_merge_3d, 167*9cc54793SDmitry Baryshkov .intf_count = ARRAY_SIZE(sm8550_intf), 168*9cc54793SDmitry Baryshkov .intf = sm8550_intf, 169*9cc54793SDmitry Baryshkov .vbif_count = ARRAY_SIZE(sdm845_vbif), 170*9cc54793SDmitry Baryshkov .vbif = sdm845_vbif, 171*9cc54793SDmitry Baryshkov .reg_dma_count = 1, 172*9cc54793SDmitry Baryshkov .dma_cfg = &sm8450_regdma, 173*9cc54793SDmitry Baryshkov .perf = &sm8450_perf_data, 174*9cc54793SDmitry Baryshkov .mdss_irqs = IRQ_SM8450_MASK, 175*9cc54793SDmitry Baryshkov }; 176*9cc54793SDmitry Baryshkov 177*9cc54793SDmitry Baryshkov #endif 178