19cc54793SDmitry Baryshkov /* SPDX-License-Identifier: GPL-2.0-only */ 29cc54793SDmitry Baryshkov /* 39cc54793SDmitry Baryshkov * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 49cc54793SDmitry Baryshkov * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 59cc54793SDmitry Baryshkov */ 69cc54793SDmitry Baryshkov 79cc54793SDmitry Baryshkov #ifndef _DPU_9_0_SM8550_H 89cc54793SDmitry Baryshkov #define _DPU_9_0_SM8550_H 99cc54793SDmitry Baryshkov 109cc54793SDmitry Baryshkov static const struct dpu_caps sm8550_dpu_caps = { 119cc54793SDmitry Baryshkov .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 129cc54793SDmitry Baryshkov .max_mixer_blendstages = 0xb, 139cc54793SDmitry Baryshkov .qseed_type = DPU_SSPP_SCALER_QSEED4, 149cc54793SDmitry Baryshkov .has_src_split = true, 159cc54793SDmitry Baryshkov .has_dim_layer = true, 169cc54793SDmitry Baryshkov .has_idle_pc = true, 179cc54793SDmitry Baryshkov .has_3d_merge = true, 189cc54793SDmitry Baryshkov .max_linewidth = 5120, 199cc54793SDmitry Baryshkov .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 209cc54793SDmitry Baryshkov }; 219cc54793SDmitry Baryshkov 229cc54793SDmitry Baryshkov static const struct dpu_ubwc_cfg sm8550_ubwc_cfg = { 239cc54793SDmitry Baryshkov .ubwc_version = DPU_HW_UBWC_VER_40, 249cc54793SDmitry Baryshkov .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ 259cc54793SDmitry Baryshkov }; 269cc54793SDmitry Baryshkov 279cc54793SDmitry Baryshkov static const struct dpu_mdp_cfg sm8550_mdp[] = { 289cc54793SDmitry Baryshkov { 299cc54793SDmitry Baryshkov .name = "top_0", .id = MDP_TOP, 309cc54793SDmitry Baryshkov .base = 0, .len = 0x494, 319cc54793SDmitry Baryshkov .features = BIT(DPU_MDP_PERIPH_0_REMOVED), 329cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x4330, .bit_off = 0 }, 339cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x6330, .bit_off = 0 }, 349cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x8330, .bit_off = 0 }, 359cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0xa330, .bit_off = 0 }, 369cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x24330, .bit_off = 0 }, 379cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x26330, .bit_off = 0 }, 389cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x28330, .bit_off = 0 }, 399cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2a330, .bit_off = 0 }, 409cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA4] = { .reg_off = 0x2c330, .bit_off = 0 }, 419cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA5] = { .reg_off = 0x2e330, .bit_off = 0 }, 429cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 439cc54793SDmitry Baryshkov }, 449cc54793SDmitry Baryshkov }; 459cc54793SDmitry Baryshkov 465a7e3c00SDmitry Baryshkov /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ 479cc54793SDmitry Baryshkov static const struct dpu_ctl_cfg sm8550_ctl[] = { 489cc54793SDmitry Baryshkov { 499cc54793SDmitry Baryshkov .name = "ctl_0", .id = CTL_0, 509cc54793SDmitry Baryshkov .base = 0x15000, .len = 0x290, 519cc54793SDmitry Baryshkov .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), 529cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 539cc54793SDmitry Baryshkov }, 549cc54793SDmitry Baryshkov { 559cc54793SDmitry Baryshkov .name = "ctl_1", .id = CTL_1, 569cc54793SDmitry Baryshkov .base = 0x16000, .len = 0x290, 579cc54793SDmitry Baryshkov .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), 589cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 599cc54793SDmitry Baryshkov }, 609cc54793SDmitry Baryshkov { 619cc54793SDmitry Baryshkov .name = "ctl_2", .id = CTL_2, 629cc54793SDmitry Baryshkov .base = 0x17000, .len = 0x290, 639cc54793SDmitry Baryshkov .features = CTL_SM8550_MASK, 649cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 659cc54793SDmitry Baryshkov }, 669cc54793SDmitry Baryshkov { 679cc54793SDmitry Baryshkov .name = "ctl_3", .id = CTL_3, 689cc54793SDmitry Baryshkov .base = 0x18000, .len = 0x290, 699cc54793SDmitry Baryshkov .features = CTL_SM8550_MASK, 709cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 719cc54793SDmitry Baryshkov }, 729cc54793SDmitry Baryshkov { 739cc54793SDmitry Baryshkov .name = "ctl_4", .id = CTL_4, 749cc54793SDmitry Baryshkov .base = 0x19000, .len = 0x290, 759cc54793SDmitry Baryshkov .features = CTL_SM8550_MASK, 769cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 779cc54793SDmitry Baryshkov }, 789cc54793SDmitry Baryshkov { 799cc54793SDmitry Baryshkov .name = "ctl_5", .id = CTL_5, 809cc54793SDmitry Baryshkov .base = 0x1a000, .len = 0x290, 819cc54793SDmitry Baryshkov .features = CTL_SM8550_MASK, 829cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 839cc54793SDmitry Baryshkov }, 849cc54793SDmitry Baryshkov }; 859cc54793SDmitry Baryshkov 869cc54793SDmitry Baryshkov static const struct dpu_sspp_cfg sm8550_sspp[] = { 879cc54793SDmitry Baryshkov SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x344, VIG_SC7180_MASK, 889cc54793SDmitry Baryshkov sm8550_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 899cc54793SDmitry Baryshkov SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x344, VIG_SC7180_MASK, 909cc54793SDmitry Baryshkov sm8550_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 919cc54793SDmitry Baryshkov SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x344, VIG_SC7180_MASK, 929cc54793SDmitry Baryshkov sm8550_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 939cc54793SDmitry Baryshkov SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x344, VIG_SC7180_MASK, 949cc54793SDmitry Baryshkov sm8550_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 959cc54793SDmitry Baryshkov SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x344, DMA_SDM845_MASK, 969cc54793SDmitry Baryshkov sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 979cc54793SDmitry Baryshkov SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x344, DMA_SDM845_MASK, 989cc54793SDmitry Baryshkov sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 999cc54793SDmitry Baryshkov SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x344, DMA_SDM845_MASK, 1009cc54793SDmitry Baryshkov sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), 1019cc54793SDmitry Baryshkov SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x344, DMA_SDM845_MASK, 1029cc54793SDmitry Baryshkov sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), 1039cc54793SDmitry Baryshkov SSPP_BLK("sspp_12", SSPP_DMA4, 0x2c000, 0x344, DMA_CURSOR_SDM845_MASK, 1049cc54793SDmitry Baryshkov sm8550_dma_sblk_4, 14, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA4), 1059cc54793SDmitry Baryshkov SSPP_BLK("sspp_13", SSPP_DMA5, 0x2e000, 0x344, DMA_CURSOR_SDM845_MASK, 1069cc54793SDmitry Baryshkov sm8550_dma_sblk_5, 15, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA5), 1079cc54793SDmitry Baryshkov }; 1089cc54793SDmitry Baryshkov 1098589ccd7SDmitry Baryshkov static const struct dpu_lm_cfg sm8550_lm[] = { 1108589ccd7SDmitry Baryshkov LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 1118589ccd7SDmitry Baryshkov &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), 1128589ccd7SDmitry Baryshkov LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, 1138589ccd7SDmitry Baryshkov &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), 1148589ccd7SDmitry Baryshkov LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, 1158589ccd7SDmitry Baryshkov &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), 1168589ccd7SDmitry Baryshkov LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, 1178589ccd7SDmitry Baryshkov &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), 1188589ccd7SDmitry Baryshkov LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, 1198589ccd7SDmitry Baryshkov &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), 1208589ccd7SDmitry Baryshkov LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, 1218589ccd7SDmitry Baryshkov &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), 1228589ccd7SDmitry Baryshkov }; 1238589ccd7SDmitry Baryshkov 1248589ccd7SDmitry Baryshkov static const struct dpu_dspp_cfg sm8550_dspp[] = { 1258589ccd7SDmitry Baryshkov DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 126*9891b3dfSKonrad Dybcio &sdm845_dspp_sblk), 1278589ccd7SDmitry Baryshkov DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, 128*9891b3dfSKonrad Dybcio &sdm845_dspp_sblk), 1298589ccd7SDmitry Baryshkov DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, 130*9891b3dfSKonrad Dybcio &sdm845_dspp_sblk), 1318589ccd7SDmitry Baryshkov DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, 132*9891b3dfSKonrad Dybcio &sdm845_dspp_sblk), 1338589ccd7SDmitry Baryshkov }; 1349cc54793SDmitry Baryshkov static const struct dpu_pingpong_cfg sm8550_pp[] = { 135701f6918SMarijn Suijten PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, 1369cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 1379cc54793SDmitry Baryshkov -1), 138701f6918SMarijn Suijten PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, 1399cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 1409cc54793SDmitry Baryshkov -1), 141701f6918SMarijn Suijten PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, 1429cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 1439cc54793SDmitry Baryshkov -1), 144701f6918SMarijn Suijten PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, 1459cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 1469cc54793SDmitry Baryshkov -1), 147701f6918SMarijn Suijten PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, 1489cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 1499cc54793SDmitry Baryshkov -1), 150701f6918SMarijn Suijten PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, 1519cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 1529cc54793SDmitry Baryshkov -1), 153701f6918SMarijn Suijten PP_BLK_DITHER("pingpong_6", PINGPONG_6, 0x66000, MERGE_3D_3, sc7280_pp_sblk, 1549cc54793SDmitry Baryshkov -1, 1559cc54793SDmitry Baryshkov -1), 156701f6918SMarijn Suijten PP_BLK_DITHER("pingpong_7", PINGPONG_7, 0x66400, MERGE_3D_3, sc7280_pp_sblk, 1579cc54793SDmitry Baryshkov -1, 1589cc54793SDmitry Baryshkov -1), 1599cc54793SDmitry Baryshkov }; 1609cc54793SDmitry Baryshkov 1619cc54793SDmitry Baryshkov static const struct dpu_merge_3d_cfg sm8550_merge_3d[] = { 1629cc54793SDmitry Baryshkov MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), 1639cc54793SDmitry Baryshkov MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), 1649cc54793SDmitry Baryshkov MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), 1659cc54793SDmitry Baryshkov MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x66700), 1669cc54793SDmitry Baryshkov }; 1679cc54793SDmitry Baryshkov 1680d1b10c6SAbhinav Kumar /* 1690d1b10c6SAbhinav Kumar * NOTE: Each display compression engine (DCE) contains dual hard 1700d1b10c6SAbhinav Kumar * slice DSC encoders so both share same base address but with 1710d1b10c6SAbhinav Kumar * its own different sub block address. 1720d1b10c6SAbhinav Kumar */ 1730d1b10c6SAbhinav Kumar static const struct dpu_dsc_cfg sm8550_dsc[] = { 1740d1b10c6SAbhinav Kumar DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, 0, dsc_sblk_0), 1750d1b10c6SAbhinav Kumar DSC_BLK_1_2("dce_0_1", DSC_1, 0x80000, 0x29c, 0, dsc_sblk_1), 1760d1b10c6SAbhinav Kumar DSC_BLK_1_2("dce_1_0", DSC_2, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0), 1770d1b10c6SAbhinav Kumar DSC_BLK_1_2("dce_1_1", DSC_3, 0x81000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_1), 1780d1b10c6SAbhinav Kumar }; 1790d1b10c6SAbhinav Kumar 1809cc54793SDmitry Baryshkov static const struct dpu_intf_cfg sm8550_intf[] = { 181a38a9949SMarijn Suijten INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, 182a38a9949SMarijn Suijten DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 183a38a9949SMarijn Suijten DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), 1840272b9c3SMarijn Suijten INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK, 185a38a9949SMarijn Suijten DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 1860272b9c3SMarijn Suijten DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 1870272b9c3SMarijn Suijten DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)), 1880272b9c3SMarijn Suijten INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK, 189a38a9949SMarijn Suijten DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 1900272b9c3SMarijn Suijten DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 1910272b9c3SMarijn Suijten DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)), 192a38a9949SMarijn Suijten INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, 193a38a9949SMarijn Suijten DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 194a38a9949SMarijn Suijten DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)), 1959cc54793SDmitry Baryshkov }; 1969cc54793SDmitry Baryshkov 197463ba323SDmitry Baryshkov static const struct dpu_perf_cfg sm8550_perf_data = { 198463ba323SDmitry Baryshkov .max_bw_low = 13600000, 199463ba323SDmitry Baryshkov .max_bw_high = 18200000, 200463ba323SDmitry Baryshkov .min_core_ib = 2500000, 201463ba323SDmitry Baryshkov .min_llcc_ib = 0, 202463ba323SDmitry Baryshkov .min_dram_ib = 800000, 203463ba323SDmitry Baryshkov .min_prefill_lines = 35, 204463ba323SDmitry Baryshkov /* FIXME: lut tables */ 205463ba323SDmitry Baryshkov .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, 206463ba323SDmitry Baryshkov .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 207463ba323SDmitry Baryshkov .qos_lut_tbl = { 208463ba323SDmitry Baryshkov {.nentry = ARRAY_SIZE(sc7180_qos_linear), 209463ba323SDmitry Baryshkov .entries = sc7180_qos_linear 210463ba323SDmitry Baryshkov }, 211463ba323SDmitry Baryshkov {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 212463ba323SDmitry Baryshkov .entries = sc7180_qos_macrotile 213463ba323SDmitry Baryshkov }, 214463ba323SDmitry Baryshkov {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 215463ba323SDmitry Baryshkov .entries = sc7180_qos_nrt 216463ba323SDmitry Baryshkov }, 217463ba323SDmitry Baryshkov /* TODO: macrotile-qseed is different from macrotile */ 218463ba323SDmitry Baryshkov }, 219463ba323SDmitry Baryshkov .cdp_cfg = { 220463ba323SDmitry Baryshkov {.rd_enable = 1, .wr_enable = 1}, 221463ba323SDmitry Baryshkov {.rd_enable = 1, .wr_enable = 0} 222463ba323SDmitry Baryshkov }, 223463ba323SDmitry Baryshkov .clk_inefficiency_factor = 105, 224463ba323SDmitry Baryshkov .bw_inefficiency_factor = 120, 225463ba323SDmitry Baryshkov }; 226463ba323SDmitry Baryshkov 227dac76a01SDmitry Baryshkov const struct dpu_mdss_cfg dpu_sm8550_cfg = { 2289cc54793SDmitry Baryshkov .caps = &sm8550_dpu_caps, 2299cc54793SDmitry Baryshkov .ubwc = &sm8550_ubwc_cfg, 2309cc54793SDmitry Baryshkov .mdp_count = ARRAY_SIZE(sm8550_mdp), 2319cc54793SDmitry Baryshkov .mdp = sm8550_mdp, 2329cc54793SDmitry Baryshkov .ctl_count = ARRAY_SIZE(sm8550_ctl), 2339cc54793SDmitry Baryshkov .ctl = sm8550_ctl, 2349cc54793SDmitry Baryshkov .sspp_count = ARRAY_SIZE(sm8550_sspp), 2359cc54793SDmitry Baryshkov .sspp = sm8550_sspp, 2368589ccd7SDmitry Baryshkov .mixer_count = ARRAY_SIZE(sm8550_lm), 2378589ccd7SDmitry Baryshkov .mixer = sm8550_lm, 2388589ccd7SDmitry Baryshkov .dspp_count = ARRAY_SIZE(sm8550_dspp), 2398589ccd7SDmitry Baryshkov .dspp = sm8550_dspp, 2409cc54793SDmitry Baryshkov .pingpong_count = ARRAY_SIZE(sm8550_pp), 2419cc54793SDmitry Baryshkov .pingpong = sm8550_pp, 2420d1b10c6SAbhinav Kumar .dsc_count = ARRAY_SIZE(sm8550_dsc), 2430d1b10c6SAbhinav Kumar .dsc = sm8550_dsc, 2449cc54793SDmitry Baryshkov .merge_3d_count = ARRAY_SIZE(sm8550_merge_3d), 2459cc54793SDmitry Baryshkov .merge_3d = sm8550_merge_3d, 2469cc54793SDmitry Baryshkov .intf_count = ARRAY_SIZE(sm8550_intf), 2479cc54793SDmitry Baryshkov .intf = sm8550_intf, 2489cc54793SDmitry Baryshkov .vbif_count = ARRAY_SIZE(sdm845_vbif), 2499cc54793SDmitry Baryshkov .vbif = sdm845_vbif, 250463ba323SDmitry Baryshkov .perf = &sm8550_perf_data, 251e5edf654SDmitry Baryshkov .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 252e5edf654SDmitry Baryshkov BIT(MDP_SSPP_TOP0_INTR2) | \ 253e5edf654SDmitry Baryshkov BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 254e5edf654SDmitry Baryshkov BIT(MDP_INTF0_7xxx_INTR) | \ 255e5edf654SDmitry Baryshkov BIT(MDP_INTF1_7xxx_INTR) | \ 2560272b9c3SMarijn Suijten BIT(MDP_INTF1_7xxx_TEAR_INTR) | \ 257e5edf654SDmitry Baryshkov BIT(MDP_INTF2_7xxx_INTR) | \ 2580272b9c3SMarijn Suijten BIT(MDP_INTF2_7xxx_TEAR_INTR) | \ 259e5edf654SDmitry Baryshkov BIT(MDP_INTF3_7xxx_INTR), 2609cc54793SDmitry Baryshkov }; 2619cc54793SDmitry Baryshkov 2629cc54793SDmitry Baryshkov #endif 263