1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_8_1_SM8450_H 8 #define _DPU_8_1_SM8450_H 9 10 static const struct dpu_caps sm8450_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .qseed_type = DPU_SSPP_SCALER_QSEED4, 14 .has_src_split = true, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .has_3d_merge = true, 18 .max_linewidth = 5120, 19 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20 }; 21 22 static const struct dpu_mdp_cfg sm8450_mdp = { 23 .name = "top_0", 24 .base = 0x0, .len = 0x494, 25 .features = BIT(DPU_MDP_PERIPH_0_REMOVED), 26 .clk_ctrls = { 27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 35 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 36 }, 37 }; 38 39 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ 40 static const struct dpu_ctl_cfg sm8450_ctl[] = { 41 { 42 .name = "ctl_0", .id = CTL_0, 43 .base = 0x15000, .len = 0x204, 44 .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, 45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 46 }, { 47 .name = "ctl_1", .id = CTL_1, 48 .base = 0x16000, .len = 0x204, 49 .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, 50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 51 }, { 52 .name = "ctl_2", .id = CTL_2, 53 .base = 0x17000, .len = 0x204, 54 .features = CTL_SC7280_MASK, 55 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 56 }, { 57 .name = "ctl_3", .id = CTL_3, 58 .base = 0x18000, .len = 0x204, 59 .features = CTL_SC7280_MASK, 60 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 61 }, { 62 .name = "ctl_4", .id = CTL_4, 63 .base = 0x19000, .len = 0x204, 64 .features = CTL_SC7280_MASK, 65 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 66 }, { 67 .name = "ctl_5", .id = CTL_5, 68 .base = 0x1a000, .len = 0x204, 69 .features = CTL_SC7280_MASK, 70 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 71 }, 72 }; 73 74 static const struct dpu_sspp_cfg sm8450_sspp[] = { 75 { 76 .name = "sspp_0", .id = SSPP_VIG0, 77 .base = 0x4000, .len = 0x32c, 78 .features = VIG_SC7180_MASK, 79 .sblk = &sm8250_vig_sblk_0, 80 .xin_id = 0, 81 .type = SSPP_TYPE_VIG, 82 .clk_ctrl = DPU_CLK_CTRL_VIG0, 83 }, { 84 .name = "sspp_1", .id = SSPP_VIG1, 85 .base = 0x6000, .len = 0x32c, 86 .features = VIG_SC7180_MASK, 87 .sblk = &sm8250_vig_sblk_1, 88 .xin_id = 4, 89 .type = SSPP_TYPE_VIG, 90 .clk_ctrl = DPU_CLK_CTRL_VIG1, 91 }, { 92 .name = "sspp_2", .id = SSPP_VIG2, 93 .base = 0x8000, .len = 0x32c, 94 .features = VIG_SC7180_MASK, 95 .sblk = &sm8250_vig_sblk_2, 96 .xin_id = 8, 97 .type = SSPP_TYPE_VIG, 98 .clk_ctrl = DPU_CLK_CTRL_VIG2, 99 }, { 100 .name = "sspp_3", .id = SSPP_VIG3, 101 .base = 0xa000, .len = 0x32c, 102 .features = VIG_SC7180_MASK, 103 .sblk = &sm8250_vig_sblk_3, 104 .xin_id = 12, 105 .type = SSPP_TYPE_VIG, 106 .clk_ctrl = DPU_CLK_CTRL_VIG3, 107 }, { 108 .name = "sspp_8", .id = SSPP_DMA0, 109 .base = 0x24000, .len = 0x32c, 110 .features = DMA_SDM845_MASK, 111 .sblk = &sdm845_dma_sblk_0, 112 .xin_id = 1, 113 .type = SSPP_TYPE_DMA, 114 .clk_ctrl = DPU_CLK_CTRL_DMA0, 115 }, { 116 .name = "sspp_9", .id = SSPP_DMA1, 117 .base = 0x26000, .len = 0x32c, 118 .features = DMA_SDM845_MASK, 119 .sblk = &sdm845_dma_sblk_1, 120 .xin_id = 5, 121 .type = SSPP_TYPE_DMA, 122 .clk_ctrl = DPU_CLK_CTRL_DMA1, 123 }, { 124 .name = "sspp_10", .id = SSPP_DMA2, 125 .base = 0x28000, .len = 0x32c, 126 .features = DMA_CURSOR_SDM845_MASK, 127 .sblk = &sdm845_dma_sblk_2, 128 .xin_id = 9, 129 .type = SSPP_TYPE_DMA, 130 .clk_ctrl = DPU_CLK_CTRL_DMA2, 131 }, { 132 .name = "sspp_11", .id = SSPP_DMA3, 133 .base = 0x2a000, .len = 0x32c, 134 .features = DMA_CURSOR_SDM845_MASK, 135 .sblk = &sdm845_dma_sblk_3, 136 .xin_id = 13, 137 .type = SSPP_TYPE_DMA, 138 .clk_ctrl = DPU_CLK_CTRL_DMA3, 139 }, 140 }; 141 142 static const struct dpu_lm_cfg sm8450_lm[] = { 143 { 144 .name = "lm_0", .id = LM_0, 145 .base = 0x44000, .len = 0x320, 146 .features = MIXER_SDM845_MASK, 147 .sblk = &sdm845_lm_sblk, 148 .lm_pair = LM_1, 149 .pingpong = PINGPONG_0, 150 .dspp = DSPP_0, 151 }, { 152 .name = "lm_1", .id = LM_1, 153 .base = 0x45000, .len = 0x320, 154 .features = MIXER_SDM845_MASK, 155 .sblk = &sdm845_lm_sblk, 156 .lm_pair = LM_0, 157 .pingpong = PINGPONG_1, 158 .dspp = DSPP_1, 159 }, { 160 .name = "lm_2", .id = LM_2, 161 .base = 0x46000, .len = 0x320, 162 .features = MIXER_SDM845_MASK, 163 .sblk = &sdm845_lm_sblk, 164 .lm_pair = LM_3, 165 .pingpong = PINGPONG_2, 166 .dspp = DSPP_2, 167 }, { 168 .name = "lm_3", .id = LM_3, 169 .base = 0x47000, .len = 0x320, 170 .features = MIXER_SDM845_MASK, 171 .sblk = &sdm845_lm_sblk, 172 .lm_pair = LM_2, 173 .pingpong = PINGPONG_3, 174 .dspp = DSPP_3, 175 }, { 176 .name = "lm_4", .id = LM_4, 177 .base = 0x48000, .len = 0x320, 178 .features = MIXER_SDM845_MASK, 179 .sblk = &sdm845_lm_sblk, 180 .lm_pair = LM_5, 181 .pingpong = PINGPONG_4, 182 }, { 183 .name = "lm_5", .id = LM_5, 184 .base = 0x49000, .len = 0x320, 185 .features = MIXER_SDM845_MASK, 186 .sblk = &sdm845_lm_sblk, 187 .lm_pair = LM_4, 188 .pingpong = PINGPONG_5, 189 }, 190 }; 191 192 static const struct dpu_dspp_cfg sm8450_dspp[] = { 193 { 194 .name = "dspp_0", .id = DSPP_0, 195 .base = 0x54000, .len = 0x1800, 196 .features = DSPP_SC7180_MASK, 197 .sblk = &sdm845_dspp_sblk, 198 }, { 199 .name = "dspp_1", .id = DSPP_1, 200 .base = 0x56000, .len = 0x1800, 201 .features = DSPP_SC7180_MASK, 202 .sblk = &sdm845_dspp_sblk, 203 }, { 204 .name = "dspp_2", .id = DSPP_2, 205 .base = 0x58000, .len = 0x1800, 206 .features = DSPP_SC7180_MASK, 207 .sblk = &sdm845_dspp_sblk, 208 }, { 209 .name = "dspp_3", .id = DSPP_3, 210 .base = 0x5a000, .len = 0x1800, 211 .features = DSPP_SC7180_MASK, 212 .sblk = &sdm845_dspp_sblk, 213 }, 214 }; 215 216 static const struct dpu_pingpong_cfg sm8450_pp[] = { 217 { 218 .name = "pingpong_0", .id = PINGPONG_0, 219 .base = 0x69000, .len = 0, 220 .features = BIT(DPU_PINGPONG_DITHER), 221 .sblk = &sc7280_pp_sblk, 222 .merge_3d = MERGE_3D_0, 223 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 224 .intr_rdptr = -1, 225 }, { 226 .name = "pingpong_1", .id = PINGPONG_1, 227 .base = 0x6a000, .len = 0, 228 .features = BIT(DPU_PINGPONG_DITHER), 229 .sblk = &sc7280_pp_sblk, 230 .merge_3d = MERGE_3D_0, 231 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 232 .intr_rdptr = -1, 233 }, { 234 .name = "pingpong_2", .id = PINGPONG_2, 235 .base = 0x6b000, .len = 0, 236 .features = BIT(DPU_PINGPONG_DITHER), 237 .sblk = &sc7280_pp_sblk, 238 .merge_3d = MERGE_3D_1, 239 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 240 .intr_rdptr = -1, 241 }, { 242 .name = "pingpong_3", .id = PINGPONG_3, 243 .base = 0x6c000, .len = 0, 244 .features = BIT(DPU_PINGPONG_DITHER), 245 .sblk = &sc7280_pp_sblk, 246 .merge_3d = MERGE_3D_1, 247 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 248 .intr_rdptr = -1, 249 }, { 250 .name = "pingpong_4", .id = PINGPONG_4, 251 .base = 0x6d000, .len = 0, 252 .features = BIT(DPU_PINGPONG_DITHER), 253 .sblk = &sc7280_pp_sblk, 254 .merge_3d = MERGE_3D_2, 255 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 256 .intr_rdptr = -1, 257 }, { 258 .name = "pingpong_5", .id = PINGPONG_5, 259 .base = 0x6e000, .len = 0, 260 .features = BIT(DPU_PINGPONG_DITHER), 261 .sblk = &sc7280_pp_sblk, 262 .merge_3d = MERGE_3D_2, 263 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 264 .intr_rdptr = -1, 265 }, { 266 .name = "pingpong_6", .id = PINGPONG_6, 267 .base = 0x65800, .len = 0, 268 .features = BIT(DPU_PINGPONG_DITHER), 269 .sblk = &sc7280_pp_sblk, 270 .merge_3d = MERGE_3D_3, 271 .intr_done = -1, 272 .intr_rdptr = -1, 273 }, { 274 .name = "pingpong_7", .id = PINGPONG_7, 275 .base = 0x65c00, .len = 0, 276 .features = BIT(DPU_PINGPONG_DITHER), 277 .sblk = &sc7280_pp_sblk, 278 .merge_3d = MERGE_3D_3, 279 .intr_done = -1, 280 .intr_rdptr = -1, 281 }, 282 }; 283 284 static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { 285 { 286 .name = "merge_3d_0", .id = MERGE_3D_0, 287 .base = 0x4e000, .len = 0x8, 288 }, { 289 .name = "merge_3d_1", .id = MERGE_3D_1, 290 .base = 0x4f000, .len = 0x8, 291 }, { 292 .name = "merge_3d_2", .id = MERGE_3D_2, 293 .base = 0x50000, .len = 0x8, 294 }, { 295 .name = "merge_3d_3", .id = MERGE_3D_3, 296 .base = 0x65f00, .len = 0x8, 297 }, 298 }; 299 300 /* 301 * NOTE: Each display compression engine (DCE) contains dual hard 302 * slice DSC encoders so both share same base address but with 303 * its own different sub block address. 304 */ 305 static const struct dpu_dsc_cfg sm8450_dsc[] = { 306 { 307 .name = "dce_0_0", .id = DSC_0, 308 .base = 0x80000, .len = 0x4, 309 .features = BIT(DPU_DSC_HW_REV_1_2), 310 .sblk = &dsc_sblk_0, 311 }, { 312 .name = "dce_0_1", .id = DSC_1, 313 .base = 0x80000, .len = 0x4, 314 .features = BIT(DPU_DSC_HW_REV_1_2), 315 .sblk = &dsc_sblk_1, 316 }, { 317 .name = "dce_1_0", .id = DSC_2, 318 .base = 0x81000, .len = 0x4, 319 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 320 .sblk = &dsc_sblk_0, 321 }, { 322 .name = "dce_1_1", .id = DSC_3, 323 .base = 0x81000, .len = 0x4, 324 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 325 .sblk = &dsc_sblk_1, 326 }, 327 }; 328 329 static const struct dpu_intf_cfg sm8450_intf[] = { 330 { 331 .name = "intf_0", .id = INTF_0, 332 .base = 0x34000, .len = 0x280, 333 .features = INTF_SC7280_MASK, 334 .type = INTF_DP, 335 .controller_id = MSM_DP_CONTROLLER_0, 336 .prog_fetch_lines_worst_case = 24, 337 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 338 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 339 .intr_tear_rd_ptr = -1, 340 }, { 341 .name = "intf_1", .id = INTF_1, 342 .base = 0x35000, .len = 0x300, 343 .features = INTF_SC7280_MASK, 344 .type = INTF_DSI, 345 .controller_id = MSM_DSI_CONTROLLER_0, 346 .prog_fetch_lines_worst_case = 24, 347 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 348 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 349 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 350 }, { 351 .name = "intf_2", .id = INTF_2, 352 .base = 0x36000, .len = 0x300, 353 .features = INTF_SC7280_MASK, 354 .type = INTF_DSI, 355 .controller_id = MSM_DSI_CONTROLLER_1, 356 .prog_fetch_lines_worst_case = 24, 357 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 358 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 359 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 360 }, { 361 .name = "intf_3", .id = INTF_3, 362 .base = 0x37000, .len = 0x280, 363 .features = INTF_SC7280_MASK, 364 .type = INTF_DP, 365 .controller_id = MSM_DP_CONTROLLER_1, 366 .prog_fetch_lines_worst_case = 24, 367 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 368 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 369 .intr_tear_rd_ptr = -1, 370 }, 371 }; 372 373 static const struct dpu_perf_cfg sm8450_perf_data = { 374 .max_bw_low = 13600000, 375 .max_bw_high = 18200000, 376 .min_core_ib = 2500000, 377 .min_llcc_ib = 0, 378 .min_dram_ib = 800000, 379 .min_prefill_lines = 35, 380 /* FIXME: lut tables */ 381 .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, 382 .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 383 .qos_lut_tbl = { 384 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 385 .entries = sc7180_qos_linear 386 }, 387 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 388 .entries = sc7180_qos_macrotile 389 }, 390 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 391 .entries = sc7180_qos_nrt 392 }, 393 /* TODO: macrotile-qseed is different from macrotile */ 394 }, 395 .cdp_cfg = { 396 {.rd_enable = 1, .wr_enable = 1}, 397 {.rd_enable = 1, .wr_enable = 0} 398 }, 399 .clk_inefficiency_factor = 105, 400 .bw_inefficiency_factor = 120, 401 }; 402 403 static const struct dpu_mdss_version sm8450_mdss_ver = { 404 .core_major_ver = 8, 405 .core_minor_ver = 1, 406 }; 407 408 const struct dpu_mdss_cfg dpu_sm8450_cfg = { 409 .mdss_ver = &sm8450_mdss_ver, 410 .caps = &sm8450_dpu_caps, 411 .mdp = &sm8450_mdp, 412 .ctl_count = ARRAY_SIZE(sm8450_ctl), 413 .ctl = sm8450_ctl, 414 .sspp_count = ARRAY_SIZE(sm8450_sspp), 415 .sspp = sm8450_sspp, 416 .mixer_count = ARRAY_SIZE(sm8450_lm), 417 .mixer = sm8450_lm, 418 .dspp_count = ARRAY_SIZE(sm8450_dspp), 419 .dspp = sm8450_dspp, 420 .pingpong_count = ARRAY_SIZE(sm8450_pp), 421 .pingpong = sm8450_pp, 422 .dsc_count = ARRAY_SIZE(sm8450_dsc), 423 .dsc = sm8450_dsc, 424 .merge_3d_count = ARRAY_SIZE(sm8450_merge_3d), 425 .merge_3d = sm8450_merge_3d, 426 .intf_count = ARRAY_SIZE(sm8450_intf), 427 .intf = sm8450_intf, 428 .vbif_count = ARRAY_SIZE(sdm845_vbif), 429 .vbif = sdm845_vbif, 430 .perf = &sm8450_perf_data, 431 }; 432 433 #endif 434