1*9cc54793SDmitry Baryshkov /* SPDX-License-Identifier: GPL-2.0-only */ 2*9cc54793SDmitry Baryshkov /* 3*9cc54793SDmitry Baryshkov * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4*9cc54793SDmitry Baryshkov * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5*9cc54793SDmitry Baryshkov */ 6*9cc54793SDmitry Baryshkov 7*9cc54793SDmitry Baryshkov #ifndef _DPU_8_1_SM8450_H 8*9cc54793SDmitry Baryshkov #define _DPU_8_1_SM8450_H 9*9cc54793SDmitry Baryshkov 10*9cc54793SDmitry Baryshkov static const struct dpu_caps sm8450_dpu_caps = { 11*9cc54793SDmitry Baryshkov .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12*9cc54793SDmitry Baryshkov .max_mixer_blendstages = 0xb, 13*9cc54793SDmitry Baryshkov .qseed_type = DPU_SSPP_SCALER_QSEED4, 14*9cc54793SDmitry Baryshkov .has_src_split = true, 15*9cc54793SDmitry Baryshkov .has_dim_layer = true, 16*9cc54793SDmitry Baryshkov .has_idle_pc = true, 17*9cc54793SDmitry Baryshkov .has_3d_merge = true, 18*9cc54793SDmitry Baryshkov .max_linewidth = 5120, 19*9cc54793SDmitry Baryshkov .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20*9cc54793SDmitry Baryshkov }; 21*9cc54793SDmitry Baryshkov 22*9cc54793SDmitry Baryshkov static const struct dpu_ubwc_cfg sm8450_ubwc_cfg = { 23*9cc54793SDmitry Baryshkov .ubwc_version = DPU_HW_UBWC_VER_40, 24*9cc54793SDmitry Baryshkov .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ 25*9cc54793SDmitry Baryshkov .ubwc_swizzle = 0x6, 26*9cc54793SDmitry Baryshkov }; 27*9cc54793SDmitry Baryshkov 28*9cc54793SDmitry Baryshkov static const struct dpu_mdp_cfg sm8450_mdp[] = { 29*9cc54793SDmitry Baryshkov { 30*9cc54793SDmitry Baryshkov .name = "top_0", .id = MDP_TOP, 31*9cc54793SDmitry Baryshkov .base = 0x0, .len = 0x494, 32*9cc54793SDmitry Baryshkov .features = BIT(DPU_MDP_PERIPH_0_REMOVED), 33*9cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 34*9cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 35*9cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 36*9cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 37*9cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 38*9cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 39*9cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 40*9cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 41*9cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 42*9cc54793SDmitry Baryshkov }, 43*9cc54793SDmitry Baryshkov }; 44*9cc54793SDmitry Baryshkov 45*9cc54793SDmitry Baryshkov static const struct dpu_ctl_cfg sm8450_ctl[] = { 46*9cc54793SDmitry Baryshkov { 47*9cc54793SDmitry Baryshkov .name = "ctl_0", .id = CTL_0, 48*9cc54793SDmitry Baryshkov .base = 0x15000, .len = 0x204, 49*9cc54793SDmitry Baryshkov .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE), 50*9cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 51*9cc54793SDmitry Baryshkov }, 52*9cc54793SDmitry Baryshkov { 53*9cc54793SDmitry Baryshkov .name = "ctl_1", .id = CTL_1, 54*9cc54793SDmitry Baryshkov .base = 0x16000, .len = 0x204, 55*9cc54793SDmitry Baryshkov .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, 56*9cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 57*9cc54793SDmitry Baryshkov }, 58*9cc54793SDmitry Baryshkov { 59*9cc54793SDmitry Baryshkov .name = "ctl_2", .id = CTL_2, 60*9cc54793SDmitry Baryshkov .base = 0x17000, .len = 0x204, 61*9cc54793SDmitry Baryshkov .features = CTL_SC7280_MASK, 62*9cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 63*9cc54793SDmitry Baryshkov }, 64*9cc54793SDmitry Baryshkov { 65*9cc54793SDmitry Baryshkov .name = "ctl_3", .id = CTL_3, 66*9cc54793SDmitry Baryshkov .base = 0x18000, .len = 0x204, 67*9cc54793SDmitry Baryshkov .features = CTL_SC7280_MASK, 68*9cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 69*9cc54793SDmitry Baryshkov }, 70*9cc54793SDmitry Baryshkov { 71*9cc54793SDmitry Baryshkov .name = "ctl_4", .id = CTL_4, 72*9cc54793SDmitry Baryshkov .base = 0x19000, .len = 0x204, 73*9cc54793SDmitry Baryshkov .features = CTL_SC7280_MASK, 74*9cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 75*9cc54793SDmitry Baryshkov }, 76*9cc54793SDmitry Baryshkov { 77*9cc54793SDmitry Baryshkov .name = "ctl_5", .id = CTL_5, 78*9cc54793SDmitry Baryshkov .base = 0x1a000, .len = 0x204, 79*9cc54793SDmitry Baryshkov .features = CTL_SC7280_MASK, 80*9cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 81*9cc54793SDmitry Baryshkov }, 82*9cc54793SDmitry Baryshkov }; 83*9cc54793SDmitry Baryshkov 84*9cc54793SDmitry Baryshkov static const struct dpu_sspp_cfg sm8450_sspp[] = { 85*9cc54793SDmitry Baryshkov SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x32c, VIG_SC7180_MASK, 86*9cc54793SDmitry Baryshkov sm8450_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 87*9cc54793SDmitry Baryshkov SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x32c, VIG_SC7180_MASK, 88*9cc54793SDmitry Baryshkov sm8450_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 89*9cc54793SDmitry Baryshkov SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x32c, VIG_SC7180_MASK, 90*9cc54793SDmitry Baryshkov sm8450_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 91*9cc54793SDmitry Baryshkov SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x32c, VIG_SC7180_MASK, 92*9cc54793SDmitry Baryshkov sm8450_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 93*9cc54793SDmitry Baryshkov SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x32c, DMA_SDM845_MASK, 94*9cc54793SDmitry Baryshkov sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 95*9cc54793SDmitry Baryshkov SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x32c, DMA_SDM845_MASK, 96*9cc54793SDmitry Baryshkov sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 97*9cc54793SDmitry Baryshkov SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x32c, DMA_CURSOR_SDM845_MASK, 98*9cc54793SDmitry Baryshkov sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), 99*9cc54793SDmitry Baryshkov SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x32c, DMA_CURSOR_SDM845_MASK, 100*9cc54793SDmitry Baryshkov sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), 101*9cc54793SDmitry Baryshkov }; 102*9cc54793SDmitry Baryshkov 103*9cc54793SDmitry Baryshkov /* FIXME: interrupts */ 104*9cc54793SDmitry Baryshkov static const struct dpu_pingpong_cfg sm8450_pp[] = { 105*9cc54793SDmitry Baryshkov PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, 106*9cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 107*9cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 108*9cc54793SDmitry Baryshkov PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, 109*9cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 110*9cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 111*9cc54793SDmitry Baryshkov PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk, 112*9cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 113*9cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), 114*9cc54793SDmitry Baryshkov PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk, 115*9cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 116*9cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), 117*9cc54793SDmitry Baryshkov PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk, 118*9cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 119*9cc54793SDmitry Baryshkov -1), 120*9cc54793SDmitry Baryshkov PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk, 121*9cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 122*9cc54793SDmitry Baryshkov -1), 123*9cc54793SDmitry Baryshkov PP_BLK("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sdm845_pp_sblk, 124*9cc54793SDmitry Baryshkov -1, 125*9cc54793SDmitry Baryshkov -1), 126*9cc54793SDmitry Baryshkov PP_BLK("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sdm845_pp_sblk, 127*9cc54793SDmitry Baryshkov -1, 128*9cc54793SDmitry Baryshkov -1), 129*9cc54793SDmitry Baryshkov }; 130*9cc54793SDmitry Baryshkov 131*9cc54793SDmitry Baryshkov static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { 132*9cc54793SDmitry Baryshkov MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), 133*9cc54793SDmitry Baryshkov MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), 134*9cc54793SDmitry Baryshkov MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), 135*9cc54793SDmitry Baryshkov MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00), 136*9cc54793SDmitry Baryshkov }; 137*9cc54793SDmitry Baryshkov 138*9cc54793SDmitry Baryshkov static const struct dpu_intf_cfg sm8450_intf[] = { 139*9cc54793SDmitry Baryshkov INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 140*9cc54793SDmitry Baryshkov INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 141*9cc54793SDmitry Baryshkov INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 142*9cc54793SDmitry Baryshkov INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 143*9cc54793SDmitry Baryshkov }; 144*9cc54793SDmitry Baryshkov 145*9cc54793SDmitry Baryshkov static const struct dpu_perf_cfg sm8450_perf_data = { 146*9cc54793SDmitry Baryshkov .max_bw_low = 13600000, 147*9cc54793SDmitry Baryshkov .max_bw_high = 18200000, 148*9cc54793SDmitry Baryshkov .min_core_ib = 2500000, 149*9cc54793SDmitry Baryshkov .min_llcc_ib = 0, 150*9cc54793SDmitry Baryshkov .min_dram_ib = 800000, 151*9cc54793SDmitry Baryshkov .min_prefill_lines = 35, 152*9cc54793SDmitry Baryshkov /* FIXME: lut tables */ 153*9cc54793SDmitry Baryshkov .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, 154*9cc54793SDmitry Baryshkov .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 155*9cc54793SDmitry Baryshkov .qos_lut_tbl = { 156*9cc54793SDmitry Baryshkov {.nentry = ARRAY_SIZE(sc7180_qos_linear), 157*9cc54793SDmitry Baryshkov .entries = sc7180_qos_linear 158*9cc54793SDmitry Baryshkov }, 159*9cc54793SDmitry Baryshkov {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 160*9cc54793SDmitry Baryshkov .entries = sc7180_qos_macrotile 161*9cc54793SDmitry Baryshkov }, 162*9cc54793SDmitry Baryshkov {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 163*9cc54793SDmitry Baryshkov .entries = sc7180_qos_nrt 164*9cc54793SDmitry Baryshkov }, 165*9cc54793SDmitry Baryshkov /* TODO: macrotile-qseed is different from macrotile */ 166*9cc54793SDmitry Baryshkov }, 167*9cc54793SDmitry Baryshkov .cdp_cfg = { 168*9cc54793SDmitry Baryshkov {.rd_enable = 1, .wr_enable = 1}, 169*9cc54793SDmitry Baryshkov {.rd_enable = 1, .wr_enable = 0} 170*9cc54793SDmitry Baryshkov }, 171*9cc54793SDmitry Baryshkov .clk_inefficiency_factor = 105, 172*9cc54793SDmitry Baryshkov .bw_inefficiency_factor = 120, 173*9cc54793SDmitry Baryshkov }; 174*9cc54793SDmitry Baryshkov 175*9cc54793SDmitry Baryshkov static const struct dpu_mdss_cfg sm8450_dpu_cfg = { 176*9cc54793SDmitry Baryshkov .caps = &sm8450_dpu_caps, 177*9cc54793SDmitry Baryshkov .ubwc = &sm8450_ubwc_cfg, 178*9cc54793SDmitry Baryshkov .mdp_count = ARRAY_SIZE(sm8450_mdp), 179*9cc54793SDmitry Baryshkov .mdp = sm8450_mdp, 180*9cc54793SDmitry Baryshkov .ctl_count = ARRAY_SIZE(sm8450_ctl), 181*9cc54793SDmitry Baryshkov .ctl = sm8450_ctl, 182*9cc54793SDmitry Baryshkov .sspp_count = ARRAY_SIZE(sm8450_sspp), 183*9cc54793SDmitry Baryshkov .sspp = sm8450_sspp, 184*9cc54793SDmitry Baryshkov .mixer_count = ARRAY_SIZE(sm8150_lm), 185*9cc54793SDmitry Baryshkov .mixer = sm8150_lm, 186*9cc54793SDmitry Baryshkov .dspp_count = ARRAY_SIZE(sm8150_dspp), 187*9cc54793SDmitry Baryshkov .dspp = sm8150_dspp, 188*9cc54793SDmitry Baryshkov .pingpong_count = ARRAY_SIZE(sm8450_pp), 189*9cc54793SDmitry Baryshkov .pingpong = sm8450_pp, 190*9cc54793SDmitry Baryshkov .merge_3d_count = ARRAY_SIZE(sm8450_merge_3d), 191*9cc54793SDmitry Baryshkov .merge_3d = sm8450_merge_3d, 192*9cc54793SDmitry Baryshkov .intf_count = ARRAY_SIZE(sm8450_intf), 193*9cc54793SDmitry Baryshkov .intf = sm8450_intf, 194*9cc54793SDmitry Baryshkov .vbif_count = ARRAY_SIZE(sdm845_vbif), 195*9cc54793SDmitry Baryshkov .vbif = sdm845_vbif, 196*9cc54793SDmitry Baryshkov .reg_dma_count = 1, 197*9cc54793SDmitry Baryshkov .dma_cfg = &sm8450_regdma, 198*9cc54793SDmitry Baryshkov .perf = &sm8450_perf_data, 199*9cc54793SDmitry Baryshkov .mdss_irqs = IRQ_SM8450_MASK, 200*9cc54793SDmitry Baryshkov }; 201*9cc54793SDmitry Baryshkov 202*9cc54793SDmitry Baryshkov #endif 203