19cc54793SDmitry Baryshkov /* SPDX-License-Identifier: GPL-2.0-only */ 29cc54793SDmitry Baryshkov /* 39cc54793SDmitry Baryshkov * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 49cc54793SDmitry Baryshkov * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 59cc54793SDmitry Baryshkov */ 69cc54793SDmitry Baryshkov 79cc54793SDmitry Baryshkov #ifndef _DPU_8_1_SM8450_H 89cc54793SDmitry Baryshkov #define _DPU_8_1_SM8450_H 99cc54793SDmitry Baryshkov 109cc54793SDmitry Baryshkov static const struct dpu_caps sm8450_dpu_caps = { 119cc54793SDmitry Baryshkov .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 129cc54793SDmitry Baryshkov .max_mixer_blendstages = 0xb, 139cc54793SDmitry Baryshkov .qseed_type = DPU_SSPP_SCALER_QSEED4, 149cc54793SDmitry Baryshkov .has_src_split = true, 159cc54793SDmitry Baryshkov .has_dim_layer = true, 169cc54793SDmitry Baryshkov .has_idle_pc = true, 179cc54793SDmitry Baryshkov .has_3d_merge = true, 189cc54793SDmitry Baryshkov .max_linewidth = 5120, 199cc54793SDmitry Baryshkov .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 209cc54793SDmitry Baryshkov }; 219cc54793SDmitry Baryshkov 229cc54793SDmitry Baryshkov static const struct dpu_ubwc_cfg sm8450_ubwc_cfg = { 239cc54793SDmitry Baryshkov .ubwc_version = DPU_HW_UBWC_VER_40, 249cc54793SDmitry Baryshkov .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ 259cc54793SDmitry Baryshkov .ubwc_swizzle = 0x6, 269cc54793SDmitry Baryshkov }; 279cc54793SDmitry Baryshkov 289cc54793SDmitry Baryshkov static const struct dpu_mdp_cfg sm8450_mdp[] = { 299cc54793SDmitry Baryshkov { 309cc54793SDmitry Baryshkov .name = "top_0", .id = MDP_TOP, 319cc54793SDmitry Baryshkov .base = 0x0, .len = 0x494, 329cc54793SDmitry Baryshkov .features = BIT(DPU_MDP_PERIPH_0_REMOVED), 339cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 349cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 359cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 369cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 379cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 389cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 399cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 409cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 419cc54793SDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 429cc54793SDmitry Baryshkov }, 439cc54793SDmitry Baryshkov }; 449cc54793SDmitry Baryshkov 45*5a7e3c00SDmitry Baryshkov /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ 469cc54793SDmitry Baryshkov static const struct dpu_ctl_cfg sm8450_ctl[] = { 479cc54793SDmitry Baryshkov { 489cc54793SDmitry Baryshkov .name = "ctl_0", .id = CTL_0, 499cc54793SDmitry Baryshkov .base = 0x15000, .len = 0x204, 509cc54793SDmitry Baryshkov .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE), 519cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 529cc54793SDmitry Baryshkov }, 539cc54793SDmitry Baryshkov { 549cc54793SDmitry Baryshkov .name = "ctl_1", .id = CTL_1, 559cc54793SDmitry Baryshkov .base = 0x16000, .len = 0x204, 569cc54793SDmitry Baryshkov .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, 579cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 589cc54793SDmitry Baryshkov }, 599cc54793SDmitry Baryshkov { 609cc54793SDmitry Baryshkov .name = "ctl_2", .id = CTL_2, 619cc54793SDmitry Baryshkov .base = 0x17000, .len = 0x204, 629cc54793SDmitry Baryshkov .features = CTL_SC7280_MASK, 639cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 649cc54793SDmitry Baryshkov }, 659cc54793SDmitry Baryshkov { 669cc54793SDmitry Baryshkov .name = "ctl_3", .id = CTL_3, 679cc54793SDmitry Baryshkov .base = 0x18000, .len = 0x204, 689cc54793SDmitry Baryshkov .features = CTL_SC7280_MASK, 699cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 709cc54793SDmitry Baryshkov }, 719cc54793SDmitry Baryshkov { 729cc54793SDmitry Baryshkov .name = "ctl_4", .id = CTL_4, 739cc54793SDmitry Baryshkov .base = 0x19000, .len = 0x204, 749cc54793SDmitry Baryshkov .features = CTL_SC7280_MASK, 759cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 769cc54793SDmitry Baryshkov }, 779cc54793SDmitry Baryshkov { 789cc54793SDmitry Baryshkov .name = "ctl_5", .id = CTL_5, 799cc54793SDmitry Baryshkov .base = 0x1a000, .len = 0x204, 809cc54793SDmitry Baryshkov .features = CTL_SC7280_MASK, 819cc54793SDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 829cc54793SDmitry Baryshkov }, 839cc54793SDmitry Baryshkov }; 849cc54793SDmitry Baryshkov 859cc54793SDmitry Baryshkov static const struct dpu_sspp_cfg sm8450_sspp[] = { 869cc54793SDmitry Baryshkov SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x32c, VIG_SC7180_MASK, 879cc54793SDmitry Baryshkov sm8450_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 889cc54793SDmitry Baryshkov SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x32c, VIG_SC7180_MASK, 899cc54793SDmitry Baryshkov sm8450_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 909cc54793SDmitry Baryshkov SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x32c, VIG_SC7180_MASK, 919cc54793SDmitry Baryshkov sm8450_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 929cc54793SDmitry Baryshkov SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x32c, VIG_SC7180_MASK, 939cc54793SDmitry Baryshkov sm8450_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 949cc54793SDmitry Baryshkov SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x32c, DMA_SDM845_MASK, 959cc54793SDmitry Baryshkov sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 969cc54793SDmitry Baryshkov SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x32c, DMA_SDM845_MASK, 979cc54793SDmitry Baryshkov sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 989cc54793SDmitry Baryshkov SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x32c, DMA_CURSOR_SDM845_MASK, 999cc54793SDmitry Baryshkov sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), 1009cc54793SDmitry Baryshkov SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x32c, DMA_CURSOR_SDM845_MASK, 1019cc54793SDmitry Baryshkov sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), 1029cc54793SDmitry Baryshkov }; 1039cc54793SDmitry Baryshkov 1048589ccd7SDmitry Baryshkov static const struct dpu_lm_cfg sm8450_lm[] = { 1058589ccd7SDmitry Baryshkov LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 1068589ccd7SDmitry Baryshkov &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), 1078589ccd7SDmitry Baryshkov LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, 1088589ccd7SDmitry Baryshkov &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), 1098589ccd7SDmitry Baryshkov LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, 1108589ccd7SDmitry Baryshkov &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), 1118589ccd7SDmitry Baryshkov LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, 1128589ccd7SDmitry Baryshkov &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), 1138589ccd7SDmitry Baryshkov LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, 1148589ccd7SDmitry Baryshkov &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), 1158589ccd7SDmitry Baryshkov LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, 1168589ccd7SDmitry Baryshkov &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), 1178589ccd7SDmitry Baryshkov }; 1188589ccd7SDmitry Baryshkov 1198589ccd7SDmitry Baryshkov static const struct dpu_dspp_cfg sm8450_dspp[] = { 1208589ccd7SDmitry Baryshkov DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 1218589ccd7SDmitry Baryshkov &sm8150_dspp_sblk), 1228589ccd7SDmitry Baryshkov DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, 1238589ccd7SDmitry Baryshkov &sm8150_dspp_sblk), 1248589ccd7SDmitry Baryshkov DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, 1258589ccd7SDmitry Baryshkov &sm8150_dspp_sblk), 1268589ccd7SDmitry Baryshkov DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, 1278589ccd7SDmitry Baryshkov &sm8150_dspp_sblk), 1288589ccd7SDmitry Baryshkov }; 1299cc54793SDmitry Baryshkov /* FIXME: interrupts */ 1309cc54793SDmitry Baryshkov static const struct dpu_pingpong_cfg sm8450_pp[] = { 1319cc54793SDmitry Baryshkov PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te, 1329cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 1339cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 1349cc54793SDmitry Baryshkov PP_BLK_TE("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sdm845_pp_sblk_te, 1359cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 1369cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 1379cc54793SDmitry Baryshkov PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sdm845_pp_sblk, 1389cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 1399cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), 1409cc54793SDmitry Baryshkov PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sdm845_pp_sblk, 1419cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 1429cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), 1439cc54793SDmitry Baryshkov PP_BLK("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sdm845_pp_sblk, 1449cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 1459cc54793SDmitry Baryshkov -1), 1469cc54793SDmitry Baryshkov PP_BLK("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sdm845_pp_sblk, 1479cc54793SDmitry Baryshkov DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 1489cc54793SDmitry Baryshkov -1), 1499cc54793SDmitry Baryshkov PP_BLK("pingpong_6", PINGPONG_6, 0x65800, MERGE_3D_3, sdm845_pp_sblk, 1509cc54793SDmitry Baryshkov -1, 1519cc54793SDmitry Baryshkov -1), 1529cc54793SDmitry Baryshkov PP_BLK("pingpong_7", PINGPONG_7, 0x65c00, MERGE_3D_3, sdm845_pp_sblk, 1539cc54793SDmitry Baryshkov -1, 1549cc54793SDmitry Baryshkov -1), 1559cc54793SDmitry Baryshkov }; 1569cc54793SDmitry Baryshkov 1579cc54793SDmitry Baryshkov static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { 1589cc54793SDmitry Baryshkov MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), 1599cc54793SDmitry Baryshkov MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), 1609cc54793SDmitry Baryshkov MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), 1619cc54793SDmitry Baryshkov MERGE_3D_BLK("merge_3d_3", MERGE_3D_3, 0x65f00), 1629cc54793SDmitry Baryshkov }; 1639cc54793SDmitry Baryshkov 1649cc54793SDmitry Baryshkov static const struct dpu_intf_cfg sm8450_intf[] = { 1659cc54793SDmitry Baryshkov INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 1669cc54793SDmitry Baryshkov INTF_BLK("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 1679cc54793SDmitry Baryshkov INTF_BLK("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 1689cc54793SDmitry Baryshkov INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 1699cc54793SDmitry Baryshkov }; 1709cc54793SDmitry Baryshkov 1719cc54793SDmitry Baryshkov static const struct dpu_perf_cfg sm8450_perf_data = { 1729cc54793SDmitry Baryshkov .max_bw_low = 13600000, 1739cc54793SDmitry Baryshkov .max_bw_high = 18200000, 1749cc54793SDmitry Baryshkov .min_core_ib = 2500000, 1759cc54793SDmitry Baryshkov .min_llcc_ib = 0, 1769cc54793SDmitry Baryshkov .min_dram_ib = 800000, 1779cc54793SDmitry Baryshkov .min_prefill_lines = 35, 1789cc54793SDmitry Baryshkov /* FIXME: lut tables */ 1799cc54793SDmitry Baryshkov .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, 1809cc54793SDmitry Baryshkov .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 1819cc54793SDmitry Baryshkov .qos_lut_tbl = { 1829cc54793SDmitry Baryshkov {.nentry = ARRAY_SIZE(sc7180_qos_linear), 1839cc54793SDmitry Baryshkov .entries = sc7180_qos_linear 1849cc54793SDmitry Baryshkov }, 1859cc54793SDmitry Baryshkov {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 1869cc54793SDmitry Baryshkov .entries = sc7180_qos_macrotile 1879cc54793SDmitry Baryshkov }, 1889cc54793SDmitry Baryshkov {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 1899cc54793SDmitry Baryshkov .entries = sc7180_qos_nrt 1909cc54793SDmitry Baryshkov }, 1919cc54793SDmitry Baryshkov /* TODO: macrotile-qseed is different from macrotile */ 1929cc54793SDmitry Baryshkov }, 1939cc54793SDmitry Baryshkov .cdp_cfg = { 1949cc54793SDmitry Baryshkov {.rd_enable = 1, .wr_enable = 1}, 1959cc54793SDmitry Baryshkov {.rd_enable = 1, .wr_enable = 0} 1969cc54793SDmitry Baryshkov }, 1979cc54793SDmitry Baryshkov .clk_inefficiency_factor = 105, 1989cc54793SDmitry Baryshkov .bw_inefficiency_factor = 120, 1999cc54793SDmitry Baryshkov }; 2009cc54793SDmitry Baryshkov 2019cc54793SDmitry Baryshkov static const struct dpu_mdss_cfg sm8450_dpu_cfg = { 2029cc54793SDmitry Baryshkov .caps = &sm8450_dpu_caps, 2039cc54793SDmitry Baryshkov .ubwc = &sm8450_ubwc_cfg, 2049cc54793SDmitry Baryshkov .mdp_count = ARRAY_SIZE(sm8450_mdp), 2059cc54793SDmitry Baryshkov .mdp = sm8450_mdp, 2069cc54793SDmitry Baryshkov .ctl_count = ARRAY_SIZE(sm8450_ctl), 2079cc54793SDmitry Baryshkov .ctl = sm8450_ctl, 2089cc54793SDmitry Baryshkov .sspp_count = ARRAY_SIZE(sm8450_sspp), 2099cc54793SDmitry Baryshkov .sspp = sm8450_sspp, 2108589ccd7SDmitry Baryshkov .mixer_count = ARRAY_SIZE(sm8450_lm), 2118589ccd7SDmitry Baryshkov .mixer = sm8450_lm, 2128589ccd7SDmitry Baryshkov .dspp_count = ARRAY_SIZE(sm8450_dspp), 2138589ccd7SDmitry Baryshkov .dspp = sm8450_dspp, 2149cc54793SDmitry Baryshkov .pingpong_count = ARRAY_SIZE(sm8450_pp), 2159cc54793SDmitry Baryshkov .pingpong = sm8450_pp, 2169cc54793SDmitry Baryshkov .merge_3d_count = ARRAY_SIZE(sm8450_merge_3d), 2179cc54793SDmitry Baryshkov .merge_3d = sm8450_merge_3d, 2189cc54793SDmitry Baryshkov .intf_count = ARRAY_SIZE(sm8450_intf), 2199cc54793SDmitry Baryshkov .intf = sm8450_intf, 2209cc54793SDmitry Baryshkov .vbif_count = ARRAY_SIZE(sdm845_vbif), 2219cc54793SDmitry Baryshkov .vbif = sdm845_vbif, 2229cc54793SDmitry Baryshkov .reg_dma_count = 1, 2239cc54793SDmitry Baryshkov .dma_cfg = &sm8450_regdma, 2249cc54793SDmitry Baryshkov .perf = &sm8450_perf_data, 2259cc54793SDmitry Baryshkov .mdss_irqs = IRQ_SM8450_MASK, 2269cc54793SDmitry Baryshkov }; 2279cc54793SDmitry Baryshkov 2289cc54793SDmitry Baryshkov #endif 229