1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_7_2_SC7280_H 8 #define _DPU_7_2_SC7280_H 9 10 static const struct dpu_caps sc7280_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0x7, 13 .qseed_type = DPU_SSPP_SCALER_QSEED4, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .max_linewidth = 2400, 17 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18 }; 19 20 static const struct dpu_ubwc_cfg sc7280_ubwc_cfg = { 21 .ubwc_version = DPU_HW_UBWC_VER_30, 22 .highest_bank_bit = 0x1, 23 .ubwc_swizzle = 0x6, 24 }; 25 26 static const struct dpu_mdp_cfg sc7280_mdp[] = { 27 { 28 .name = "top_0", .id = MDP_TOP, 29 .base = 0x0, .len = 0x2014, 30 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 31 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 32 .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 33 .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 34 .clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, 35 }, 36 }; 37 38 static const struct dpu_ctl_cfg sc7280_ctl[] = { 39 { 40 .name = "ctl_0", .id = CTL_0, 41 .base = 0x15000, .len = 0x1e8, 42 .features = CTL_SC7280_MASK, 43 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 44 }, 45 { 46 .name = "ctl_1", .id = CTL_1, 47 .base = 0x16000, .len = 0x1e8, 48 .features = CTL_SC7280_MASK, 49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 50 }, 51 { 52 .name = "ctl_2", .id = CTL_2, 53 .base = 0x17000, .len = 0x1e8, 54 .features = CTL_SC7280_MASK, 55 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 56 }, 57 { 58 .name = "ctl_3", .id = CTL_3, 59 .base = 0x18000, .len = 0x1e8, 60 .features = CTL_SC7280_MASK, 61 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 62 }, 63 }; 64 65 static const struct dpu_sspp_cfg sc7280_sspp[] = { 66 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7280_MASK_SDMA, 67 sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 68 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA, 69 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 70 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA, 71 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 72 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA, 73 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), 74 }; 75 76 static const struct dpu_lm_cfg sc7280_lm[] = { 77 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 78 &sc7180_lm_sblk, PINGPONG_0, 0, DSPP_0), 79 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, 80 &sc7180_lm_sblk, PINGPONG_2, LM_3, 0), 81 LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, 82 &sc7180_lm_sblk, PINGPONG_3, LM_2, 0), 83 }; 84 85 static const struct dpu_dspp_cfg sc7280_dspp[] = { 86 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 87 &sm8150_dspp_sblk), 88 }; 89 90 static const struct dpu_pingpong_cfg sc7280_pp[] = { 91 PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk, 92 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 93 -1), 94 PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, 95 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 96 -1), 97 PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, 98 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 99 -1), 100 PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, 101 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 102 -1), 103 }; 104 105 /* NOTE: sc7280 only has one DSC hard slice encoder */ 106 static const struct dpu_dsc_cfg sc7280_dsc[] = { 107 DSC_BLK_1_2("dce_0_0", DSC_0, 0x80000, 0x29c, BIT(DPU_DSC_NATIVE_42x_EN), dsc_sblk_0), 108 }; 109 110 static const struct dpu_wb_cfg sc7280_wb[] = { 111 WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6, 112 VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4), 113 }; 114 115 static const struct dpu_intf_cfg sc7280_intf[] = { 116 INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, 117 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 118 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), 119 INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, 120 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 121 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 122 DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)), 123 INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, 124 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), 125 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)), 126 }; 127 128 static const struct dpu_perf_cfg sc7280_perf_data = { 129 .max_bw_low = 4700000, 130 .max_bw_high = 8800000, 131 .min_core_ib = 2500000, 132 .min_llcc_ib = 0, 133 .min_dram_ib = 1600000, 134 .min_prefill_lines = 24, 135 .danger_lut_tbl = {0xffff, 0xffff, 0x0}, 136 .safe_lut_tbl = {0xff00, 0xff00, 0xffff}, 137 .qos_lut_tbl = { 138 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 139 .entries = sc7180_qos_macrotile 140 }, 141 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 142 .entries = sc7180_qos_macrotile 143 }, 144 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 145 .entries = sc7180_qos_nrt 146 }, 147 }, 148 .cdp_cfg = { 149 {.rd_enable = 1, .wr_enable = 1}, 150 {.rd_enable = 1, .wr_enable = 0} 151 }, 152 .clk_inefficiency_factor = 105, 153 .bw_inefficiency_factor = 120, 154 }; 155 156 const struct dpu_mdss_cfg dpu_sc7280_cfg = { 157 .caps = &sc7280_dpu_caps, 158 .ubwc = &sc7280_ubwc_cfg, 159 .mdp_count = ARRAY_SIZE(sc7280_mdp), 160 .mdp = sc7280_mdp, 161 .ctl_count = ARRAY_SIZE(sc7280_ctl), 162 .ctl = sc7280_ctl, 163 .sspp_count = ARRAY_SIZE(sc7280_sspp), 164 .sspp = sc7280_sspp, 165 .dspp_count = ARRAY_SIZE(sc7280_dspp), 166 .dspp = sc7280_dspp, 167 .mixer_count = ARRAY_SIZE(sc7280_lm), 168 .mixer = sc7280_lm, 169 .pingpong_count = ARRAY_SIZE(sc7280_pp), 170 .pingpong = sc7280_pp, 171 .dsc_count = ARRAY_SIZE(sc7280_dsc), 172 .dsc = sc7280_dsc, 173 .wb_count = ARRAY_SIZE(sc7280_wb), 174 .wb = sc7280_wb, 175 .intf_count = ARRAY_SIZE(sc7280_intf), 176 .intf = sc7280_intf, 177 .vbif_count = ARRAY_SIZE(sdm845_vbif), 178 .vbif = sdm845_vbif, 179 .perf = &sc7280_perf_data, 180 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 181 BIT(MDP_SSPP_TOP0_INTR2) | \ 182 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 183 BIT(MDP_INTF0_7xxx_INTR) | \ 184 BIT(MDP_INTF1_7xxx_INTR) | \ 185 BIT(MDP_INTF1_7xxx_TEAR_INTR) | \ 186 BIT(MDP_INTF5_7xxx_INTR), 187 }; 188 189 #endif 190