1*f0f2c32aSDmitry Baryshkov /* SPDX-License-Identifier: GPL-2.0-only */ 2*f0f2c32aSDmitry Baryshkov /* 3*f0f2c32aSDmitry Baryshkov * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4*f0f2c32aSDmitry Baryshkov * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5*f0f2c32aSDmitry Baryshkov */ 6*f0f2c32aSDmitry Baryshkov 7*f0f2c32aSDmitry Baryshkov #ifndef _DPU_7_2_SC7280_H 8*f0f2c32aSDmitry Baryshkov #define _DPU_7_2_SC7280_H 9*f0f2c32aSDmitry Baryshkov 10*f0f2c32aSDmitry Baryshkov static const struct dpu_caps sc7280_dpu_caps = { 11*f0f2c32aSDmitry Baryshkov .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12*f0f2c32aSDmitry Baryshkov .max_mixer_blendstages = 0x7, 13*f0f2c32aSDmitry Baryshkov .qseed_type = DPU_SSPP_SCALER_QSEED4, 14*f0f2c32aSDmitry Baryshkov .has_dim_layer = true, 15*f0f2c32aSDmitry Baryshkov .has_idle_pc = true, 16*f0f2c32aSDmitry Baryshkov .max_linewidth = 2400, 17*f0f2c32aSDmitry Baryshkov .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18*f0f2c32aSDmitry Baryshkov }; 19*f0f2c32aSDmitry Baryshkov 20*f0f2c32aSDmitry Baryshkov static const struct dpu_ubwc_cfg sc7280_ubwc_cfg = { 21*f0f2c32aSDmitry Baryshkov .ubwc_version = DPU_HW_UBWC_VER_30, 22*f0f2c32aSDmitry Baryshkov .highest_bank_bit = 0x1, 23*f0f2c32aSDmitry Baryshkov .ubwc_swizzle = 0x6, 24*f0f2c32aSDmitry Baryshkov }; 25*f0f2c32aSDmitry Baryshkov 26*f0f2c32aSDmitry Baryshkov static const struct dpu_mdp_cfg sc7280_mdp[] = { 27*f0f2c32aSDmitry Baryshkov { 28*f0f2c32aSDmitry Baryshkov .name = "top_0", .id = MDP_TOP, 29*f0f2c32aSDmitry Baryshkov .base = 0x0, .len = 0x2014, 30*f0f2c32aSDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 31*f0f2c32aSDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 32*f0f2c32aSDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 33*f0f2c32aSDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 34*f0f2c32aSDmitry Baryshkov }, 35*f0f2c32aSDmitry Baryshkov }; 36*f0f2c32aSDmitry Baryshkov 37*f0f2c32aSDmitry Baryshkov static const struct dpu_ctl_cfg sc7280_ctl[] = { 38*f0f2c32aSDmitry Baryshkov { 39*f0f2c32aSDmitry Baryshkov .name = "ctl_0", .id = CTL_0, 40*f0f2c32aSDmitry Baryshkov .base = 0x15000, .len = 0x1e8, 41*f0f2c32aSDmitry Baryshkov .features = CTL_SC7280_MASK, 42*f0f2c32aSDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 43*f0f2c32aSDmitry Baryshkov }, 44*f0f2c32aSDmitry Baryshkov { 45*f0f2c32aSDmitry Baryshkov .name = "ctl_1", .id = CTL_1, 46*f0f2c32aSDmitry Baryshkov .base = 0x16000, .len = 0x1e8, 47*f0f2c32aSDmitry Baryshkov .features = CTL_SC7280_MASK, 48*f0f2c32aSDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 49*f0f2c32aSDmitry Baryshkov }, 50*f0f2c32aSDmitry Baryshkov { 51*f0f2c32aSDmitry Baryshkov .name = "ctl_2", .id = CTL_2, 52*f0f2c32aSDmitry Baryshkov .base = 0x17000, .len = 0x1e8, 53*f0f2c32aSDmitry Baryshkov .features = CTL_SC7280_MASK, 54*f0f2c32aSDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 55*f0f2c32aSDmitry Baryshkov }, 56*f0f2c32aSDmitry Baryshkov { 57*f0f2c32aSDmitry Baryshkov .name = "ctl_3", .id = CTL_3, 58*f0f2c32aSDmitry Baryshkov .base = 0x18000, .len = 0x1e8, 59*f0f2c32aSDmitry Baryshkov .features = CTL_SC7280_MASK, 60*f0f2c32aSDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 61*f0f2c32aSDmitry Baryshkov }, 62*f0f2c32aSDmitry Baryshkov }; 63*f0f2c32aSDmitry Baryshkov 64*f0f2c32aSDmitry Baryshkov static const struct dpu_sspp_cfg sc7280_sspp[] = { 65*f0f2c32aSDmitry Baryshkov SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7280_MASK_SDMA, 66*f0f2c32aSDmitry Baryshkov sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 67*f0f2c32aSDmitry Baryshkov SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA, 68*f0f2c32aSDmitry Baryshkov sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 69*f0f2c32aSDmitry Baryshkov SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA, 70*f0f2c32aSDmitry Baryshkov sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 71*f0f2c32aSDmitry Baryshkov SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA, 72*f0f2c32aSDmitry Baryshkov sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), 73*f0f2c32aSDmitry Baryshkov }; 74*f0f2c32aSDmitry Baryshkov 75*f0f2c32aSDmitry Baryshkov static const struct dpu_lm_cfg sc7280_lm[] = { 76*f0f2c32aSDmitry Baryshkov LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 77*f0f2c32aSDmitry Baryshkov &sc7180_lm_sblk, PINGPONG_0, 0, DSPP_0), 78*f0f2c32aSDmitry Baryshkov LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, 79*f0f2c32aSDmitry Baryshkov &sc7180_lm_sblk, PINGPONG_2, LM_3, 0), 80*f0f2c32aSDmitry Baryshkov LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, 81*f0f2c32aSDmitry Baryshkov &sc7180_lm_sblk, PINGPONG_3, LM_2, 0), 82*f0f2c32aSDmitry Baryshkov }; 83*f0f2c32aSDmitry Baryshkov 84*f0f2c32aSDmitry Baryshkov static const struct dpu_pingpong_cfg sc7280_pp[] = { 85*f0f2c32aSDmitry Baryshkov PP_BLK("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk, -1, -1), 86*f0f2c32aSDmitry Baryshkov PP_BLK("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1), 87*f0f2c32aSDmitry Baryshkov PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1), 88*f0f2c32aSDmitry Baryshkov PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1), 89*f0f2c32aSDmitry Baryshkov }; 90*f0f2c32aSDmitry Baryshkov 91*f0f2c32aSDmitry Baryshkov static const struct dpu_intf_cfg sc7280_intf[] = { 92*f0f2c32aSDmitry Baryshkov INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 93*f0f2c32aSDmitry Baryshkov INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 94*f0f2c32aSDmitry Baryshkov INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), 95*f0f2c32aSDmitry Baryshkov }; 96*f0f2c32aSDmitry Baryshkov 97*f0f2c32aSDmitry Baryshkov static const struct dpu_perf_cfg sc7280_perf_data = { 98*f0f2c32aSDmitry Baryshkov .max_bw_low = 4700000, 99*f0f2c32aSDmitry Baryshkov .max_bw_high = 8800000, 100*f0f2c32aSDmitry Baryshkov .min_core_ib = 2500000, 101*f0f2c32aSDmitry Baryshkov .min_llcc_ib = 0, 102*f0f2c32aSDmitry Baryshkov .min_dram_ib = 1600000, 103*f0f2c32aSDmitry Baryshkov .min_prefill_lines = 24, 104*f0f2c32aSDmitry Baryshkov .danger_lut_tbl = {0xffff, 0xffff, 0x0}, 105*f0f2c32aSDmitry Baryshkov .safe_lut_tbl = {0xff00, 0xff00, 0xffff}, 106*f0f2c32aSDmitry Baryshkov .qos_lut_tbl = { 107*f0f2c32aSDmitry Baryshkov {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 108*f0f2c32aSDmitry Baryshkov .entries = sc7180_qos_macrotile 109*f0f2c32aSDmitry Baryshkov }, 110*f0f2c32aSDmitry Baryshkov {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 111*f0f2c32aSDmitry Baryshkov .entries = sc7180_qos_macrotile 112*f0f2c32aSDmitry Baryshkov }, 113*f0f2c32aSDmitry Baryshkov {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 114*f0f2c32aSDmitry Baryshkov .entries = sc7180_qos_nrt 115*f0f2c32aSDmitry Baryshkov }, 116*f0f2c32aSDmitry Baryshkov }, 117*f0f2c32aSDmitry Baryshkov .cdp_cfg = { 118*f0f2c32aSDmitry Baryshkov {.rd_enable = 1, .wr_enable = 1}, 119*f0f2c32aSDmitry Baryshkov {.rd_enable = 1, .wr_enable = 0} 120*f0f2c32aSDmitry Baryshkov }, 121*f0f2c32aSDmitry Baryshkov .clk_inefficiency_factor = 105, 122*f0f2c32aSDmitry Baryshkov .bw_inefficiency_factor = 120, 123*f0f2c32aSDmitry Baryshkov }; 124*f0f2c32aSDmitry Baryshkov 125*f0f2c32aSDmitry Baryshkov static const struct dpu_mdss_cfg sc7280_dpu_cfg = { 126*f0f2c32aSDmitry Baryshkov .caps = &sc7280_dpu_caps, 127*f0f2c32aSDmitry Baryshkov .ubwc = &sc7280_ubwc_cfg, 128*f0f2c32aSDmitry Baryshkov .mdp_count = ARRAY_SIZE(sc7280_mdp), 129*f0f2c32aSDmitry Baryshkov .mdp = sc7280_mdp, 130*f0f2c32aSDmitry Baryshkov .ctl_count = ARRAY_SIZE(sc7280_ctl), 131*f0f2c32aSDmitry Baryshkov .ctl = sc7280_ctl, 132*f0f2c32aSDmitry Baryshkov .sspp_count = ARRAY_SIZE(sc7280_sspp), 133*f0f2c32aSDmitry Baryshkov .sspp = sc7280_sspp, 134*f0f2c32aSDmitry Baryshkov .dspp_count = ARRAY_SIZE(sc7180_dspp), 135*f0f2c32aSDmitry Baryshkov .dspp = sc7180_dspp, 136*f0f2c32aSDmitry Baryshkov .mixer_count = ARRAY_SIZE(sc7280_lm), 137*f0f2c32aSDmitry Baryshkov .mixer = sc7280_lm, 138*f0f2c32aSDmitry Baryshkov .pingpong_count = ARRAY_SIZE(sc7280_pp), 139*f0f2c32aSDmitry Baryshkov .pingpong = sc7280_pp, 140*f0f2c32aSDmitry Baryshkov .intf_count = ARRAY_SIZE(sc7280_intf), 141*f0f2c32aSDmitry Baryshkov .intf = sc7280_intf, 142*f0f2c32aSDmitry Baryshkov .vbif_count = ARRAY_SIZE(sdm845_vbif), 143*f0f2c32aSDmitry Baryshkov .vbif = sdm845_vbif, 144*f0f2c32aSDmitry Baryshkov .perf = &sc7280_perf_data, 145*f0f2c32aSDmitry Baryshkov .mdss_irqs = IRQ_SC7280_MASK, 146*f0f2c32aSDmitry Baryshkov }; 147*f0f2c32aSDmitry Baryshkov 148*f0f2c32aSDmitry Baryshkov #endif 149