1f0f2c32aSDmitry Baryshkov /* SPDX-License-Identifier: GPL-2.0-only */ 2f0f2c32aSDmitry Baryshkov /* 3f0f2c32aSDmitry Baryshkov * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4f0f2c32aSDmitry Baryshkov * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5f0f2c32aSDmitry Baryshkov */ 6f0f2c32aSDmitry Baryshkov 7f0f2c32aSDmitry Baryshkov #ifndef _DPU_7_2_SC7280_H 8f0f2c32aSDmitry Baryshkov #define _DPU_7_2_SC7280_H 9f0f2c32aSDmitry Baryshkov 10f0f2c32aSDmitry Baryshkov static const struct dpu_caps sc7280_dpu_caps = { 11f0f2c32aSDmitry Baryshkov .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12f0f2c32aSDmitry Baryshkov .max_mixer_blendstages = 0x7, 13f0f2c32aSDmitry Baryshkov .qseed_type = DPU_SSPP_SCALER_QSEED4, 14f0f2c32aSDmitry Baryshkov .has_dim_layer = true, 15f0f2c32aSDmitry Baryshkov .has_idle_pc = true, 16f0f2c32aSDmitry Baryshkov .max_linewidth = 2400, 17f0f2c32aSDmitry Baryshkov .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18f0f2c32aSDmitry Baryshkov }; 19f0f2c32aSDmitry Baryshkov 20f0f2c32aSDmitry Baryshkov static const struct dpu_ubwc_cfg sc7280_ubwc_cfg = { 21f0f2c32aSDmitry Baryshkov .ubwc_version = DPU_HW_UBWC_VER_30, 22f0f2c32aSDmitry Baryshkov .highest_bank_bit = 0x1, 23f0f2c32aSDmitry Baryshkov .ubwc_swizzle = 0x6, 24f0f2c32aSDmitry Baryshkov }; 25f0f2c32aSDmitry Baryshkov 26f0f2c32aSDmitry Baryshkov static const struct dpu_mdp_cfg sc7280_mdp[] = { 27f0f2c32aSDmitry Baryshkov { 28f0f2c32aSDmitry Baryshkov .name = "top_0", .id = MDP_TOP, 29f0f2c32aSDmitry Baryshkov .base = 0x0, .len = 0x2014, 30f0f2c32aSDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 31f0f2c32aSDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 32f0f2c32aSDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 33f0f2c32aSDmitry Baryshkov .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 34*3ce16638SAbhinav Kumar .clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, 35f0f2c32aSDmitry Baryshkov }, 36f0f2c32aSDmitry Baryshkov }; 37f0f2c32aSDmitry Baryshkov 38f0f2c32aSDmitry Baryshkov static const struct dpu_ctl_cfg sc7280_ctl[] = { 39f0f2c32aSDmitry Baryshkov { 40f0f2c32aSDmitry Baryshkov .name = "ctl_0", .id = CTL_0, 41f0f2c32aSDmitry Baryshkov .base = 0x15000, .len = 0x1e8, 42f0f2c32aSDmitry Baryshkov .features = CTL_SC7280_MASK, 43f0f2c32aSDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 44f0f2c32aSDmitry Baryshkov }, 45f0f2c32aSDmitry Baryshkov { 46f0f2c32aSDmitry Baryshkov .name = "ctl_1", .id = CTL_1, 47f0f2c32aSDmitry Baryshkov .base = 0x16000, .len = 0x1e8, 48f0f2c32aSDmitry Baryshkov .features = CTL_SC7280_MASK, 49f0f2c32aSDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 50f0f2c32aSDmitry Baryshkov }, 51f0f2c32aSDmitry Baryshkov { 52f0f2c32aSDmitry Baryshkov .name = "ctl_2", .id = CTL_2, 53f0f2c32aSDmitry Baryshkov .base = 0x17000, .len = 0x1e8, 54f0f2c32aSDmitry Baryshkov .features = CTL_SC7280_MASK, 55f0f2c32aSDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 56f0f2c32aSDmitry Baryshkov }, 57f0f2c32aSDmitry Baryshkov { 58f0f2c32aSDmitry Baryshkov .name = "ctl_3", .id = CTL_3, 59f0f2c32aSDmitry Baryshkov .base = 0x18000, .len = 0x1e8, 60f0f2c32aSDmitry Baryshkov .features = CTL_SC7280_MASK, 61f0f2c32aSDmitry Baryshkov .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 62f0f2c32aSDmitry Baryshkov }, 63f0f2c32aSDmitry Baryshkov }; 64f0f2c32aSDmitry Baryshkov 65f0f2c32aSDmitry Baryshkov static const struct dpu_sspp_cfg sc7280_sspp[] = { 66f0f2c32aSDmitry Baryshkov SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7280_MASK_SDMA, 67f0f2c32aSDmitry Baryshkov sc7280_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 68f0f2c32aSDmitry Baryshkov SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK_SDMA, 69f0f2c32aSDmitry Baryshkov sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 70f0f2c32aSDmitry Baryshkov SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA, 71f0f2c32aSDmitry Baryshkov sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 72f0f2c32aSDmitry Baryshkov SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK_SDMA, 73f0f2c32aSDmitry Baryshkov sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), 74f0f2c32aSDmitry Baryshkov }; 75f0f2c32aSDmitry Baryshkov 76f0f2c32aSDmitry Baryshkov static const struct dpu_lm_cfg sc7280_lm[] = { 77f0f2c32aSDmitry Baryshkov LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 78f0f2c32aSDmitry Baryshkov &sc7180_lm_sblk, PINGPONG_0, 0, DSPP_0), 79f0f2c32aSDmitry Baryshkov LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, 80f0f2c32aSDmitry Baryshkov &sc7180_lm_sblk, PINGPONG_2, LM_3, 0), 81f0f2c32aSDmitry Baryshkov LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, 82f0f2c32aSDmitry Baryshkov &sc7180_lm_sblk, PINGPONG_3, LM_2, 0), 83f0f2c32aSDmitry Baryshkov }; 84f0f2c32aSDmitry Baryshkov 857ea3e251SDmitry Baryshkov static const struct dpu_dspp_cfg sc7280_dspp[] = { 867ea3e251SDmitry Baryshkov DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 877ea3e251SDmitry Baryshkov &sc7180_dspp_sblk), 887ea3e251SDmitry Baryshkov }; 897ea3e251SDmitry Baryshkov 90f0f2c32aSDmitry Baryshkov static const struct dpu_pingpong_cfg sc7280_pp[] = { 917557f58bSMarijn Suijten PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, 0, sc7280_pp_sblk, -1, -1), 927557f58bSMarijn Suijten PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, 0, sc7280_pp_sblk, -1, -1), 937557f58bSMarijn Suijten PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1), 947557f58bSMarijn Suijten PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1), 95f0f2c32aSDmitry Baryshkov }; 96f0f2c32aSDmitry Baryshkov 97*3ce16638SAbhinav Kumar static const struct dpu_wb_cfg sc7280_wb[] = { 98*3ce16638SAbhinav Kumar WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6, 99*3ce16638SAbhinav Kumar VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4), 100*3ce16638SAbhinav Kumar }; 101*3ce16638SAbhinav Kumar 102f0f2c32aSDmitry Baryshkov static const struct dpu_intf_cfg sc7280_intf[] = { 103f0f2c32aSDmitry Baryshkov INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 104f0f2c32aSDmitry Baryshkov INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 105f0f2c32aSDmitry Baryshkov INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 22, 23), 106f0f2c32aSDmitry Baryshkov }; 107f0f2c32aSDmitry Baryshkov 108f0f2c32aSDmitry Baryshkov static const struct dpu_perf_cfg sc7280_perf_data = { 109f0f2c32aSDmitry Baryshkov .max_bw_low = 4700000, 110f0f2c32aSDmitry Baryshkov .max_bw_high = 8800000, 111f0f2c32aSDmitry Baryshkov .min_core_ib = 2500000, 112f0f2c32aSDmitry Baryshkov .min_llcc_ib = 0, 113f0f2c32aSDmitry Baryshkov .min_dram_ib = 1600000, 114f0f2c32aSDmitry Baryshkov .min_prefill_lines = 24, 115f0f2c32aSDmitry Baryshkov .danger_lut_tbl = {0xffff, 0xffff, 0x0}, 116f0f2c32aSDmitry Baryshkov .safe_lut_tbl = {0xff00, 0xff00, 0xffff}, 117f0f2c32aSDmitry Baryshkov .qos_lut_tbl = { 118f0f2c32aSDmitry Baryshkov {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 119f0f2c32aSDmitry Baryshkov .entries = sc7180_qos_macrotile 120f0f2c32aSDmitry Baryshkov }, 121f0f2c32aSDmitry Baryshkov {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 122f0f2c32aSDmitry Baryshkov .entries = sc7180_qos_macrotile 123f0f2c32aSDmitry Baryshkov }, 124f0f2c32aSDmitry Baryshkov {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 125f0f2c32aSDmitry Baryshkov .entries = sc7180_qos_nrt 126f0f2c32aSDmitry Baryshkov }, 127f0f2c32aSDmitry Baryshkov }, 128f0f2c32aSDmitry Baryshkov .cdp_cfg = { 129f0f2c32aSDmitry Baryshkov {.rd_enable = 1, .wr_enable = 1}, 130f0f2c32aSDmitry Baryshkov {.rd_enable = 1, .wr_enable = 0} 131f0f2c32aSDmitry Baryshkov }, 132f0f2c32aSDmitry Baryshkov .clk_inefficiency_factor = 105, 133f0f2c32aSDmitry Baryshkov .bw_inefficiency_factor = 120, 134f0f2c32aSDmitry Baryshkov }; 135f0f2c32aSDmitry Baryshkov 136dac76a01SDmitry Baryshkov const struct dpu_mdss_cfg dpu_sc7280_cfg = { 137f0f2c32aSDmitry Baryshkov .caps = &sc7280_dpu_caps, 138f0f2c32aSDmitry Baryshkov .ubwc = &sc7280_ubwc_cfg, 139f0f2c32aSDmitry Baryshkov .mdp_count = ARRAY_SIZE(sc7280_mdp), 140f0f2c32aSDmitry Baryshkov .mdp = sc7280_mdp, 141f0f2c32aSDmitry Baryshkov .ctl_count = ARRAY_SIZE(sc7280_ctl), 142f0f2c32aSDmitry Baryshkov .ctl = sc7280_ctl, 143f0f2c32aSDmitry Baryshkov .sspp_count = ARRAY_SIZE(sc7280_sspp), 144f0f2c32aSDmitry Baryshkov .sspp = sc7280_sspp, 1457ea3e251SDmitry Baryshkov .dspp_count = ARRAY_SIZE(sc7280_dspp), 1467ea3e251SDmitry Baryshkov .dspp = sc7280_dspp, 147f0f2c32aSDmitry Baryshkov .mixer_count = ARRAY_SIZE(sc7280_lm), 148f0f2c32aSDmitry Baryshkov .mixer = sc7280_lm, 149f0f2c32aSDmitry Baryshkov .pingpong_count = ARRAY_SIZE(sc7280_pp), 150f0f2c32aSDmitry Baryshkov .pingpong = sc7280_pp, 151*3ce16638SAbhinav Kumar .wb_count = ARRAY_SIZE(sc7280_wb), 152*3ce16638SAbhinav Kumar .wb = sc7280_wb, 153f0f2c32aSDmitry Baryshkov .intf_count = ARRAY_SIZE(sc7280_intf), 154f0f2c32aSDmitry Baryshkov .intf = sc7280_intf, 155f0f2c32aSDmitry Baryshkov .vbif_count = ARRAY_SIZE(sdm845_vbif), 156f0f2c32aSDmitry Baryshkov .vbif = sdm845_vbif, 157f0f2c32aSDmitry Baryshkov .perf = &sc7280_perf_data, 158e5edf654SDmitry Baryshkov .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 159e5edf654SDmitry Baryshkov BIT(MDP_SSPP_TOP0_INTR2) | \ 160e5edf654SDmitry Baryshkov BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 161e5edf654SDmitry Baryshkov BIT(MDP_INTF0_7xxx_INTR) | \ 162e5edf654SDmitry Baryshkov BIT(MDP_INTF1_7xxx_INTR) | \ 163e5edf654SDmitry Baryshkov BIT(MDP_INTF5_7xxx_INTR), 164f0f2c32aSDmitry Baryshkov }; 165f0f2c32aSDmitry Baryshkov 166f0f2c32aSDmitry Baryshkov #endif 167