1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_7_0_SM8350_H 8 #define _DPU_7_0_SM8350_H 9 10 static const struct dpu_caps sm8350_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .qseed_type = DPU_SSPP_SCALER_QSEED4, 14 .has_src_split = true, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .has_3d_merge = true, 18 .max_linewidth = 4096, 19 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20 }; 21 22 static const struct dpu_ubwc_cfg sm8350_ubwc_cfg = { 23 .ubwc_version = DPU_HW_UBWC_VER_40, 24 .highest_bank_bit = 0x3, /* TODO: 2 for LP_DDR4 */ 25 }; 26 27 static const struct dpu_mdp_cfg sm8350_mdp[] = { 28 { 29 .name = "top_0", .id = MDP_TOP, 30 .base = 0x0, .len = 0x494, 31 .features = 0, 32 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 33 .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 34 .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 35 .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 36 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 37 .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 38 .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 39 .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 40 .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 41 }, 42 }; 43 44 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ 45 static const struct dpu_ctl_cfg sm8350_ctl[] = { 46 { 47 .name = "ctl_0", .id = CTL_0, 48 .base = 0x15000, .len = 0x1e8, 49 .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, 50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 51 }, 52 { 53 .name = "ctl_1", .id = CTL_1, 54 .base = 0x16000, .len = 0x1e8, 55 .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, 56 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 57 }, 58 { 59 .name = "ctl_2", .id = CTL_2, 60 .base = 0x17000, .len = 0x1e8, 61 .features = CTL_SC7280_MASK, 62 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 63 }, 64 { 65 .name = "ctl_3", .id = CTL_3, 66 .base = 0x18000, .len = 0x1e8, 67 .features = CTL_SC7280_MASK, 68 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 69 }, 70 { 71 .name = "ctl_4", .id = CTL_4, 72 .base = 0x19000, .len = 0x1e8, 73 .features = CTL_SC7280_MASK, 74 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 75 }, 76 { 77 .name = "ctl_5", .id = CTL_5, 78 .base = 0x1a000, .len = 0x1e8, 79 .features = CTL_SC7280_MASK, 80 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 81 }, 82 }; 83 84 static const struct dpu_sspp_cfg sm8350_sspp[] = { 85 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, 86 sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 87 SSPP_BLK("sspp_1", SSPP_VIG1, 0x6000, 0x1f8, VIG_SC7180_MASK, 88 sm8250_vig_sblk_1, 4, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG1), 89 SSPP_BLK("sspp_2", SSPP_VIG2, 0x8000, 0x1f8, VIG_SC7180_MASK, 90 sm8250_vig_sblk_2, 8, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG2), 91 SSPP_BLK("sspp_3", SSPP_VIG3, 0xa000, 0x1f8, VIG_SC7180_MASK, 92 sm8250_vig_sblk_3, 12, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG3), 93 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, 94 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 95 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_SDM845_MASK, 96 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 97 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK, 98 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), 99 SSPP_BLK("sspp_11", SSPP_DMA3, 0x2a000, 0x1f8, DMA_CURSOR_SDM845_MASK, 100 sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3), 101 }; 102 103 static const struct dpu_lm_cfg sm8350_lm[] = { 104 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 105 &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0), 106 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, 107 &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1), 108 LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, 109 &sdm845_lm_sblk, PINGPONG_2, LM_3, 0), 110 LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, 111 &sdm845_lm_sblk, PINGPONG_3, LM_2, 0), 112 LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, 113 &sdm845_lm_sblk, PINGPONG_4, LM_5, 0), 114 LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, 115 &sdm845_lm_sblk, PINGPONG_5, LM_4, 0), 116 }; 117 118 static const struct dpu_dspp_cfg sm8350_dspp[] = { 119 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 120 &sm8150_dspp_sblk), 121 DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK, 122 &sm8150_dspp_sblk), 123 DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK, 124 &sm8150_dspp_sblk), 125 DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK, 126 &sm8150_dspp_sblk), 127 }; 128 129 static const struct dpu_pingpong_cfg sm8350_pp[] = { 130 PP_BLK_DITHER("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sc7280_pp_sblk, 131 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 132 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12)), 133 PP_BLK_DITHER("pingpong_1", PINGPONG_1, 0x6a000, MERGE_3D_0, sc7280_pp_sblk, 134 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 135 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13)), 136 PP_BLK_DITHER("pingpong_2", PINGPONG_2, 0x6b000, MERGE_3D_1, sc7280_pp_sblk, 137 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 138 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14)), 139 PP_BLK_DITHER("pingpong_3", PINGPONG_3, 0x6c000, MERGE_3D_1, sc7280_pp_sblk, 140 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 141 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15)), 142 PP_BLK_DITHER("pingpong_4", PINGPONG_4, 0x6d000, MERGE_3D_2, sc7280_pp_sblk, 143 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 144 -1), 145 PP_BLK_DITHER("pingpong_5", PINGPONG_5, 0x6e000, MERGE_3D_2, sc7280_pp_sblk, 146 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 147 -1), 148 }; 149 150 static const struct dpu_merge_3d_cfg sm8350_merge_3d[] = { 151 MERGE_3D_BLK("merge_3d_0", MERGE_3D_0, 0x4e000), 152 MERGE_3D_BLK("merge_3d_1", MERGE_3D_1, 0x4f000), 153 MERGE_3D_BLK("merge_3d_2", MERGE_3D_2, 0x50000), 154 }; 155 156 static const struct dpu_intf_cfg sm8350_intf[] = { 157 INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 158 INTF_BLK("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 159 INTF_BLK("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 28, 29), 160 INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK, MDP_SSPP_TOP0_INTR, 30, 31), 161 }; 162 163 static const struct dpu_perf_cfg sm8350_perf_data = { 164 .max_bw_low = 11800000, 165 .max_bw_high = 15500000, 166 .min_core_ib = 2500000, 167 .min_llcc_ib = 0, 168 .min_dram_ib = 800000, 169 .min_prefill_lines = 40, 170 /* FIXME: lut tables */ 171 .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, 172 .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 173 .qos_lut_tbl = { 174 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 175 .entries = sc7180_qos_linear 176 }, 177 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 178 .entries = sc7180_qos_macrotile 179 }, 180 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 181 .entries = sc7180_qos_nrt 182 }, 183 /* TODO: macrotile-qseed is different from macrotile */ 184 }, 185 .cdp_cfg = { 186 {.rd_enable = 1, .wr_enable = 1}, 187 {.rd_enable = 1, .wr_enable = 0} 188 }, 189 .clk_inefficiency_factor = 105, 190 .bw_inefficiency_factor = 120, 191 }; 192 193 const struct dpu_mdss_cfg dpu_sm8350_cfg = { 194 .caps = &sm8350_dpu_caps, 195 .ubwc = &sm8350_ubwc_cfg, 196 .mdp_count = ARRAY_SIZE(sm8350_mdp), 197 .mdp = sm8350_mdp, 198 .ctl_count = ARRAY_SIZE(sm8350_ctl), 199 .ctl = sm8350_ctl, 200 .sspp_count = ARRAY_SIZE(sm8350_sspp), 201 .sspp = sm8350_sspp, 202 .mixer_count = ARRAY_SIZE(sm8350_lm), 203 .mixer = sm8350_lm, 204 .dspp_count = ARRAY_SIZE(sm8350_dspp), 205 .dspp = sm8350_dspp, 206 .pingpong_count = ARRAY_SIZE(sm8350_pp), 207 .pingpong = sm8350_pp, 208 .merge_3d_count = ARRAY_SIZE(sm8350_merge_3d), 209 .merge_3d = sm8350_merge_3d, 210 .intf_count = ARRAY_SIZE(sm8350_intf), 211 .intf = sm8350_intf, 212 .vbif_count = ARRAY_SIZE(sdm845_vbif), 213 .vbif = sdm845_vbif, 214 .reg_dma_count = 1, 215 .dma_cfg = &sm8350_regdma, 216 .perf = &sm8350_perf_data, 217 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 218 BIT(MDP_SSPP_TOP0_INTR2) | \ 219 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 220 BIT(MDP_INTF0_7xxx_INTR) | \ 221 BIT(MDP_INTF1_7xxx_INTR) | \ 222 BIT(MDP_INTF2_7xxx_INTR) | \ 223 BIT(MDP_INTF3_7xxx_INTR), 224 }; 225 226 #endif 227