1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
4  * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
5  * Copyright (c) 2023, Linaro Limited
6  */
7 
8 #ifndef _DPU_6_9_SM6375_H
9 #define _DPU_6_9_SM6375_H
10 
11 static const struct dpu_caps sm6375_dpu_caps = {
12 	.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
13 	.max_mixer_blendstages = 0x4,
14 	.qseed_type = DPU_SSPP_SCALER_QSEED4,
15 	.has_dim_layer = true,
16 	.has_idle_pc = true,
17 	.max_linewidth = 2160,
18 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
19 };
20 
21 static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = {
22 	.ubwc_version = DPU_HW_UBWC_VER_20,
23 	.ubwc_swizzle = 6,
24 	.highest_bank_bit = 1,
25 };
26 
27 static const struct dpu_mdp_cfg sm6375_mdp = {
28 	.name = "top_0",
29 	.base = 0x0, .len = 0x494,
30 	.clk_ctrls = {
31 		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
32 		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
33 	},
34 };
35 
36 static const struct dpu_ctl_cfg sm6375_ctl[] = {
37 	{
38 		.name = "ctl_0", .id = CTL_0,
39 		.base = 0x1000, .len = 0x1dc,
40 		.features = BIT(DPU_CTL_ACTIVE_CFG),
41 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
42 	},
43 };
44 
45 static const struct dpu_sspp_cfg sm6375_sspp[] = {
46 	{
47 		.name = "sspp_0", .id = SSPP_VIG0,
48 		.base = 0x4000, .len = 0x1f8,
49 		.features = VIG_SC7180_MASK,
50 		.sblk = &sm6115_vig_sblk_0,
51 		.xin_id = 0,
52 		.type = SSPP_TYPE_VIG,
53 		.clk_ctrl = DPU_CLK_CTRL_VIG0,
54 	}, {
55 		.name = "sspp_8", .id = SSPP_DMA0,
56 		.base = 0x24000, .len = 0x1f8,
57 		.features = DMA_SDM845_MASK,
58 		.sblk = &sdm845_dma_sblk_0,
59 		.xin_id = 1,
60 		.type = SSPP_TYPE_DMA,
61 		.clk_ctrl = DPU_CLK_CTRL_DMA0,
62 	},
63 };
64 
65 static const struct dpu_lm_cfg sm6375_lm[] = {
66 	LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
67 		&qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
68 };
69 
70 static const struct dpu_dspp_cfg sm6375_dspp[] = {
71 	DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
72 		&sdm845_dspp_sblk),
73 };
74 
75 static const struct dpu_pingpong_cfg sm6375_pp[] = {
76 	PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
77 		DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
78 		-1),
79 };
80 
81 static const struct dpu_dsc_cfg sm6375_dsc[] = {
82 	DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
83 };
84 
85 static const struct dpu_intf_cfg sm6375_intf[] = {
86 	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
87 		DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
88 		DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
89 		DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
90 };
91 
92 static const struct dpu_perf_cfg sm6375_perf_data = {
93 	.max_bw_low = 5200000,
94 	.max_bw_high = 6200000,
95 	.min_core_ib = 2500000,
96 	.min_llcc_ib = 0, /* No LLCC on this SoC */
97 	.min_dram_ib = 1600000,
98 	.min_prefill_lines = 24,
99 	/* TODO: confirm danger_lut_tbl */
100 	.danger_lut_tbl = {0xffff, 0xffff, 0x0},
101 	.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
102 	.qos_lut_tbl = {
103 		{.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
104 		.entries = sm6350_qos_linear_macrotile
105 		},
106 		{.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
107 		.entries = sm6350_qos_linear_macrotile
108 		},
109 		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
110 		.entries = sc7180_qos_nrt
111 		},
112 	},
113 	.cdp_cfg = {
114 		{.rd_enable = 1, .wr_enable = 1},
115 		{.rd_enable = 1, .wr_enable = 0}
116 	},
117 	.clk_inefficiency_factor = 105,
118 	.bw_inefficiency_factor = 120,
119 };
120 
121 const struct dpu_mdss_cfg dpu_sm6375_cfg = {
122 	.caps = &sm6375_dpu_caps,
123 	.ubwc = &sm6375_ubwc_cfg,
124 	.mdp = &sm6375_mdp,
125 	.ctl_count = ARRAY_SIZE(sm6375_ctl),
126 	.ctl = sm6375_ctl,
127 	.sspp_count = ARRAY_SIZE(sm6375_sspp),
128 	.sspp = sm6375_sspp,
129 	.mixer_count = ARRAY_SIZE(sm6375_lm),
130 	.mixer = sm6375_lm,
131 	.dspp_count = ARRAY_SIZE(sm6375_dspp),
132 	.dspp = sm6375_dspp,
133 	.dsc_count = ARRAY_SIZE(sm6375_dsc),
134 	.dsc = sm6375_dsc,
135 	.pingpong_count = ARRAY_SIZE(sm6375_pp),
136 	.pingpong = sm6375_pp,
137 	.intf_count = ARRAY_SIZE(sm6375_intf),
138 	.intf = sm6375_intf,
139 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
140 	.vbif = sdm845_vbif,
141 	.perf = &sm6375_perf_data,
142 	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
143 		     BIT(MDP_SSPP_TOP0_INTR2) | \
144 		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
145 		     BIT(MDP_INTF1_INTR) | \
146 		     BIT(MDP_INTF1_TEAR_INTR),
147 };
148 
149 #endif
150