1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 * Copyright (c) 2023, Linaro Limited 6 */ 7 8 #ifndef _DPU_6_9_SM6375_H 9 #define _DPU_6_9_SM6375_H 10 11 static const struct dpu_caps sm6375_dpu_caps = { 12 .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, 13 .max_mixer_blendstages = 0x4, 14 .qseed_type = DPU_SSPP_SCALER_QSEED4, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .max_linewidth = 2160, 18 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 19 }; 20 21 static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = { 22 .ubwc_version = DPU_HW_UBWC_VER_20, 23 .ubwc_swizzle = 6, 24 .highest_bank_bit = 1, 25 }; 26 27 static const struct dpu_mdp_cfg sm6375_mdp[] = { 28 { 29 .name = "top_0", .id = MDP_TOP, 30 .base = 0x0, .len = 0x494, 31 .features = 0, 32 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 33 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 34 }, 35 }; 36 37 static const struct dpu_ctl_cfg sm6375_ctl[] = { 38 { 39 .name = "ctl_0", .id = CTL_0, 40 .base = 0x1000, .len = 0x1dc, 41 .features = BIT(DPU_CTL_ACTIVE_CFG), 42 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 43 }, 44 }; 45 46 static const struct dpu_sspp_cfg sm6375_sspp[] = { 47 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, 48 sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 49 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, 50 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 51 }; 52 53 static const struct dpu_lm_cfg sm6375_lm[] = { 54 LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK, 55 &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0), 56 }; 57 58 static const struct dpu_dspp_cfg sm6375_dspp[] = { 59 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 60 &sm8150_dspp_sblk), 61 }; 62 63 static const struct dpu_pingpong_cfg sm6375_pp[] = { 64 PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk, 65 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 66 -1), 67 }; 68 69 static const struct dpu_dsc_cfg sm6375_dsc[] = { 70 DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), 71 }; 72 73 static const struct dpu_intf_cfg sm6375_intf[] = { 74 INTF_BLK("intf_0", INTF_0, 0x00000, 0x280, INTF_NONE, 0, 0, 0, 0, 0), 75 INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, 76 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 77 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 78 DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), 79 }; 80 81 static const struct dpu_perf_cfg sm6375_perf_data = { 82 .max_bw_low = 5200000, 83 .max_bw_high = 6200000, 84 .min_core_ib = 2500000, 85 .min_llcc_ib = 0, /* No LLCC on this SoC */ 86 .min_dram_ib = 1600000, 87 .min_prefill_lines = 24, 88 /* TODO: confirm danger_lut_tbl */ 89 .danger_lut_tbl = {0xffff, 0xffff, 0x0}, 90 .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 91 .qos_lut_tbl = { 92 {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), 93 .entries = sm6350_qos_linear_macrotile 94 }, 95 {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), 96 .entries = sm6350_qos_linear_macrotile 97 }, 98 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 99 .entries = sc7180_qos_nrt 100 }, 101 }, 102 .cdp_cfg = { 103 {.rd_enable = 1, .wr_enable = 1}, 104 {.rd_enable = 1, .wr_enable = 0} 105 }, 106 .clk_inefficiency_factor = 105, 107 .bw_inefficiency_factor = 120, 108 }; 109 110 const struct dpu_mdss_cfg dpu_sm6375_cfg = { 111 .caps = &sm6375_dpu_caps, 112 .ubwc = &sm6375_ubwc_cfg, 113 .mdp_count = ARRAY_SIZE(sm6375_mdp), 114 .mdp = sm6375_mdp, 115 .ctl_count = ARRAY_SIZE(sm6375_ctl), 116 .ctl = sm6375_ctl, 117 .sspp_count = ARRAY_SIZE(sm6375_sspp), 118 .sspp = sm6375_sspp, 119 .mixer_count = ARRAY_SIZE(sm6375_lm), 120 .mixer = sm6375_lm, 121 .dspp_count = ARRAY_SIZE(sm6375_dspp), 122 .dspp = sm6375_dspp, 123 .dsc_count = ARRAY_SIZE(sm6375_dsc), 124 .dsc = sm6375_dsc, 125 .pingpong_count = ARRAY_SIZE(sm6375_pp), 126 .pingpong = sm6375_pp, 127 .intf_count = ARRAY_SIZE(sm6375_intf), 128 .intf = sm6375_intf, 129 .vbif_count = ARRAY_SIZE(sdm845_vbif), 130 .vbif = sdm845_vbif, 131 .perf = &sm6375_perf_data, 132 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 133 BIT(MDP_SSPP_TOP0_INTR2) | \ 134 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 135 BIT(MDP_INTF1_INTR) | \ 136 BIT(MDP_INTF1_TEAR_INTR), 137 }; 138 139 #endif 140