1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 * Copyright (c) 2023, Linaro Limited 6 */ 7 8 #ifndef _DPU_6_9_SM6375_H 9 #define _DPU_6_9_SM6375_H 10 11 static const struct dpu_caps sm6375_dpu_caps = { 12 .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, 13 .max_mixer_blendstages = 0x4, 14 .qseed_type = DPU_SSPP_SCALER_QSEED4, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .max_linewidth = 2160, 18 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 19 }; 20 21 static const struct dpu_ubwc_cfg sm6375_ubwc_cfg = { 22 .ubwc_version = DPU_HW_UBWC_VER_20, 23 .ubwc_swizzle = 6, 24 .highest_bank_bit = 1, 25 }; 26 27 static const struct dpu_mdp_cfg sm6375_mdp = { 28 .name = "top_0", 29 .base = 0x0, .len = 0x494, 30 .clk_ctrls = { 31 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 33 }, 34 }; 35 36 static const struct dpu_ctl_cfg sm6375_ctl[] = { 37 { 38 .name = "ctl_0", .id = CTL_0, 39 .base = 0x1000, .len = 0x1dc, 40 .features = BIT(DPU_CTL_ACTIVE_CFG), 41 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 42 }, 43 }; 44 45 static const struct dpu_sspp_cfg sm6375_sspp[] = { 46 { 47 .name = "sspp_0", .id = SSPP_VIG0, 48 .base = 0x4000, .len = 0x1f8, 49 .features = VIG_SC7180_MASK, 50 .sblk = &sm6115_vig_sblk_0, 51 .xin_id = 0, 52 .type = SSPP_TYPE_VIG, 53 .clk_ctrl = DPU_CLK_CTRL_VIG0, 54 }, { 55 .name = "sspp_8", .id = SSPP_DMA0, 56 .base = 0x24000, .len = 0x1f8, 57 .features = DMA_SDM845_MASK, 58 .sblk = &sdm845_dma_sblk_0, 59 .xin_id = 1, 60 .type = SSPP_TYPE_DMA, 61 .clk_ctrl = DPU_CLK_CTRL_DMA0, 62 }, 63 }; 64 65 static const struct dpu_lm_cfg sm6375_lm[] = { 66 { 67 .name = "lm_0", .id = LM_0, 68 .base = 0x44000, .len = 0x320, 69 .features = MIXER_QCM2290_MASK, 70 .sblk = &qcm2290_lm_sblk, 71 .lm_pair = 0, 72 .pingpong = PINGPONG_0, 73 .dspp = DSPP_0, 74 }, 75 }; 76 77 static const struct dpu_dspp_cfg sm6375_dspp[] = { 78 { 79 .name = "dspp_0", .id = DSPP_0, 80 .base = 0x54000, .len = 0x1800, 81 .features = DSPP_SC7180_MASK, 82 .sblk = &sdm845_dspp_sblk, 83 }, 84 }; 85 86 static const struct dpu_pingpong_cfg sm6375_pp[] = { 87 PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk, 88 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 89 -1), 90 }; 91 92 static const struct dpu_dsc_cfg sm6375_dsc[] = { 93 { 94 .name = "dsc_0", .id = DSC_0, 95 .base = 0x80000, .len = 0x140, 96 .features = BIT(DPU_DSC_OUTPUT_CTRL), 97 }, 98 }; 99 100 static const struct dpu_intf_cfg sm6375_intf[] = { 101 INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK, 102 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 103 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 104 DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), 105 }; 106 107 static const struct dpu_perf_cfg sm6375_perf_data = { 108 .max_bw_low = 5200000, 109 .max_bw_high = 6200000, 110 .min_core_ib = 2500000, 111 .min_llcc_ib = 0, /* No LLCC on this SoC */ 112 .min_dram_ib = 1600000, 113 .min_prefill_lines = 24, 114 /* TODO: confirm danger_lut_tbl */ 115 .danger_lut_tbl = {0xffff, 0xffff, 0x0}, 116 .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 117 .qos_lut_tbl = { 118 {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), 119 .entries = sm6350_qos_linear_macrotile 120 }, 121 {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), 122 .entries = sm6350_qos_linear_macrotile 123 }, 124 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 125 .entries = sc7180_qos_nrt 126 }, 127 }, 128 .cdp_cfg = { 129 {.rd_enable = 1, .wr_enable = 1}, 130 {.rd_enable = 1, .wr_enable = 0} 131 }, 132 .clk_inefficiency_factor = 105, 133 .bw_inefficiency_factor = 120, 134 }; 135 136 const struct dpu_mdss_cfg dpu_sm6375_cfg = { 137 .caps = &sm6375_dpu_caps, 138 .ubwc = &sm6375_ubwc_cfg, 139 .mdp = &sm6375_mdp, 140 .ctl_count = ARRAY_SIZE(sm6375_ctl), 141 .ctl = sm6375_ctl, 142 .sspp_count = ARRAY_SIZE(sm6375_sspp), 143 .sspp = sm6375_sspp, 144 .mixer_count = ARRAY_SIZE(sm6375_lm), 145 .mixer = sm6375_lm, 146 .dspp_count = ARRAY_SIZE(sm6375_dspp), 147 .dspp = sm6375_dspp, 148 .dsc_count = ARRAY_SIZE(sm6375_dsc), 149 .dsc = sm6375_dsc, 150 .pingpong_count = ARRAY_SIZE(sm6375_pp), 151 .pingpong = sm6375_pp, 152 .intf_count = ARRAY_SIZE(sm6375_intf), 153 .intf = sm6375_intf, 154 .vbif_count = ARRAY_SIZE(sdm845_vbif), 155 .vbif = sdm845_vbif, 156 .perf = &sm6375_perf_data, 157 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 158 BIT(MDP_SSPP_TOP0_INTR2) | \ 159 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 160 BIT(MDP_INTF1_INTR) | \ 161 BIT(MDP_INTF1_TEAR_INTR), 162 }; 163 164 #endif 165