1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
4  * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
5  */
6 
7 #ifndef _DPU_6_5_QCM2290_H
8 #define _DPU_6_5_QCM2290_H
9 
10 static const struct dpu_caps qcm2290_dpu_caps = {
11 	.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
12 	.max_mixer_blendstages = 0x4,
13 	.has_dim_layer = true,
14 	.has_idle_pc = true,
15 	.max_linewidth = 2160,
16 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
17 };
18 
19 static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = {
20 	.highest_bank_bit = 0x2,
21 };
22 
23 static const struct dpu_mdp_cfg qcm2290_mdp = {
24 	.name = "top_0",
25 	.base = 0x0, .len = 0x494,
26 	.clk_ctrls = {
27 		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 	},
30 };
31 
32 static const struct dpu_ctl_cfg qcm2290_ctl[] = {
33 	{
34 		.name = "ctl_0", .id = CTL_0,
35 		.base = 0x1000, .len = 0x1dc,
36 		.features = BIT(DPU_CTL_ACTIVE_CFG),
37 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
38 	},
39 };
40 
41 static const struct dpu_sspp_cfg qcm2290_sspp[] = {
42 	{
43 		.name = "sspp_0", .id = SSPP_VIG0,
44 		.base = 0x4000, .len = 0x1f8,
45 		.features = VIG_QCM2290_MASK,
46 		.sblk = &qcm2290_vig_sblk_0,
47 		.xin_id = 0,
48 		.type = SSPP_TYPE_VIG,
49 		.clk_ctrl = DPU_CLK_CTRL_VIG0,
50 	}, {
51 		.name = "sspp_8", .id = SSPP_DMA0,
52 		.base = 0x24000, .len = 0x1f8,
53 		.features = DMA_SDM845_MASK,
54 		.sblk = &qcm2290_dma_sblk_0,
55 		.xin_id = 1,
56 		.type = SSPP_TYPE_DMA,
57 		.clk_ctrl = DPU_CLK_CTRL_DMA0,
58 	},
59 };
60 
61 static const struct dpu_lm_cfg qcm2290_lm[] = {
62 	LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
63 		&qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
64 };
65 
66 static const struct dpu_dspp_cfg qcm2290_dspp[] = {
67 	{
68 		.name = "dspp_0", .id = DSPP_0,
69 		.base = 0x54000, .len = 0x1800,
70 		.features = DSPP_SC7180_MASK,
71 		.sblk = &sdm845_dspp_sblk,
72 	},
73 };
74 
75 static const struct dpu_pingpong_cfg qcm2290_pp[] = {
76 	PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
77 		DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
78 		-1),
79 };
80 
81 static const struct dpu_intf_cfg qcm2290_intf[] = {
82 	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
83 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
84 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
85 			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
86 };
87 
88 static const struct dpu_perf_cfg qcm2290_perf_data = {
89 	.max_bw_low = 2700000,
90 	.max_bw_high = 2700000,
91 	.min_core_ib = 1300000,
92 	.min_llcc_ib = 0,
93 	.min_dram_ib = 1600000,
94 	.min_prefill_lines = 24,
95 	.danger_lut_tbl = {0xff, 0x0, 0x0},
96 	.safe_lut_tbl = {0xfff0, 0x0, 0x0},
97 	.qos_lut_tbl = {
98 		{.nentry = ARRAY_SIZE(qcm2290_qos_linear),
99 		.entries = qcm2290_qos_linear
100 		},
101 	},
102 	.cdp_cfg = {
103 		{.rd_enable = 1, .wr_enable = 1},
104 		{.rd_enable = 1, .wr_enable = 0}
105 	},
106 	.clk_inefficiency_factor = 105,
107 	.bw_inefficiency_factor = 120,
108 };
109 
110 const struct dpu_mdss_cfg dpu_qcm2290_cfg = {
111 	.caps = &qcm2290_dpu_caps,
112 	.ubwc = &qcm2290_ubwc_cfg,
113 	.mdp = &qcm2290_mdp,
114 	.ctl_count = ARRAY_SIZE(qcm2290_ctl),
115 	.ctl = qcm2290_ctl,
116 	.sspp_count = ARRAY_SIZE(qcm2290_sspp),
117 	.sspp = qcm2290_sspp,
118 	.mixer_count = ARRAY_SIZE(qcm2290_lm),
119 	.mixer = qcm2290_lm,
120 	.dspp_count = ARRAY_SIZE(qcm2290_dspp),
121 	.dspp = qcm2290_dspp,
122 	.pingpong_count = ARRAY_SIZE(qcm2290_pp),
123 	.pingpong = qcm2290_pp,
124 	.intf_count = ARRAY_SIZE(qcm2290_intf),
125 	.intf = qcm2290_intf,
126 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
127 	.vbif = sdm845_vbif,
128 	.perf = &qcm2290_perf_data,
129 	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
130 		     BIT(MDP_SSPP_TOP0_INTR2) | \
131 		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
132 		     BIT(MDP_INTF1_INTR) | \
133 		     BIT(MDP_INTF1_TEAR_INTR),
134 };
135 
136 #endif
137