1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_6_5_QCM2290_H 8 #define _DPU_6_5_QCM2290_H 9 10 static const struct dpu_caps qcm2290_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, 12 .max_mixer_blendstages = 0x4, 13 .has_dim_layer = true, 14 .has_idle_pc = true, 15 .max_linewidth = 2160, 16 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 17 }; 18 19 static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = { 20 .highest_bank_bit = 0x2, 21 }; 22 23 static const struct dpu_mdp_cfg qcm2290_mdp = { 24 .name = "top_0", 25 .base = 0x0, .len = 0x494, 26 .clk_ctrls = { 27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 29 }, 30 }; 31 32 static const struct dpu_ctl_cfg qcm2290_ctl[] = { 33 { 34 .name = "ctl_0", .id = CTL_0, 35 .base = 0x1000, .len = 0x1dc, 36 .features = BIT(DPU_CTL_ACTIVE_CFG), 37 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 38 }, 39 }; 40 41 static const struct dpu_sspp_cfg qcm2290_sspp[] = { 42 { 43 .name = "sspp_0", .id = SSPP_VIG0, 44 .base = 0x4000, .len = 0x1f8, 45 .features = VIG_QCM2290_MASK, 46 .sblk = &qcm2290_vig_sblk_0, 47 .xin_id = 0, 48 .type = SSPP_TYPE_VIG, 49 .clk_ctrl = DPU_CLK_CTRL_VIG0, 50 }, { 51 .name = "sspp_8", .id = SSPP_DMA0, 52 .base = 0x24000, .len = 0x1f8, 53 .features = DMA_SDM845_MASK, 54 .sblk = &qcm2290_dma_sblk_0, 55 .xin_id = 1, 56 .type = SSPP_TYPE_DMA, 57 .clk_ctrl = DPU_CLK_CTRL_DMA0, 58 }, 59 }; 60 61 static const struct dpu_lm_cfg qcm2290_lm[] = { 62 { 63 .name = "lm_0", .id = LM_0, 64 .base = 0x44000, .len = 0x320, 65 .features = MIXER_QCM2290_MASK, 66 .sblk = &qcm2290_lm_sblk, 67 .pingpong = PINGPONG_0, 68 .dspp = DSPP_0, 69 }, 70 }; 71 72 static const struct dpu_dspp_cfg qcm2290_dspp[] = { 73 { 74 .name = "dspp_0", .id = DSPP_0, 75 .base = 0x54000, .len = 0x1800, 76 .features = DSPP_SC7180_MASK, 77 .sblk = &sdm845_dspp_sblk, 78 }, 79 }; 80 81 static const struct dpu_pingpong_cfg qcm2290_pp[] = { 82 PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk, 83 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 84 -1), 85 }; 86 87 static const struct dpu_intf_cfg qcm2290_intf[] = { 88 INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK, 89 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 90 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 91 DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), 92 }; 93 94 static const struct dpu_perf_cfg qcm2290_perf_data = { 95 .max_bw_low = 2700000, 96 .max_bw_high = 2700000, 97 .min_core_ib = 1300000, 98 .min_llcc_ib = 0, 99 .min_dram_ib = 1600000, 100 .min_prefill_lines = 24, 101 .danger_lut_tbl = {0xff, 0x0, 0x0}, 102 .safe_lut_tbl = {0xfff0, 0x0, 0x0}, 103 .qos_lut_tbl = { 104 {.nentry = ARRAY_SIZE(qcm2290_qos_linear), 105 .entries = qcm2290_qos_linear 106 }, 107 }, 108 .cdp_cfg = { 109 {.rd_enable = 1, .wr_enable = 1}, 110 {.rd_enable = 1, .wr_enable = 0} 111 }, 112 .clk_inefficiency_factor = 105, 113 .bw_inefficiency_factor = 120, 114 }; 115 116 const struct dpu_mdss_cfg dpu_qcm2290_cfg = { 117 .caps = &qcm2290_dpu_caps, 118 .ubwc = &qcm2290_ubwc_cfg, 119 .mdp = &qcm2290_mdp, 120 .ctl_count = ARRAY_SIZE(qcm2290_ctl), 121 .ctl = qcm2290_ctl, 122 .sspp_count = ARRAY_SIZE(qcm2290_sspp), 123 .sspp = qcm2290_sspp, 124 .mixer_count = ARRAY_SIZE(qcm2290_lm), 125 .mixer = qcm2290_lm, 126 .dspp_count = ARRAY_SIZE(qcm2290_dspp), 127 .dspp = qcm2290_dspp, 128 .pingpong_count = ARRAY_SIZE(qcm2290_pp), 129 .pingpong = qcm2290_pp, 130 .intf_count = ARRAY_SIZE(qcm2290_intf), 131 .intf = qcm2290_intf, 132 .vbif_count = ARRAY_SIZE(sdm845_vbif), 133 .vbif = sdm845_vbif, 134 .perf = &qcm2290_perf_data, 135 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 136 BIT(MDP_SSPP_TOP0_INTR2) | \ 137 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 138 BIT(MDP_INTF1_INTR) | \ 139 BIT(MDP_INTF1_TEAR_INTR), 140 }; 141 142 #endif 143