1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
4  * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
5  */
6 
7 #ifndef _DPU_6_5_QCM2290_H
8 #define _DPU_6_5_QCM2290_H
9 
10 static const struct dpu_caps qcm2290_dpu_caps = {
11 	.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
12 	.max_mixer_blendstages = 0x4,
13 	.has_dim_layer = true,
14 	.has_idle_pc = true,
15 	.max_linewidth = 2160,
16 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
17 };
18 
19 static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = {
20 	.highest_bank_bit = 0x2,
21 };
22 
23 static const struct dpu_mdp_cfg qcm2290_mdp = {
24 	.name = "top_0", .id = MDP_TOP,
25 	.base = 0x0, .len = 0x494,
26 	.features = 0,
27 	.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 	.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 };
30 
31 static const struct dpu_ctl_cfg qcm2290_ctl[] = {
32 	{
33 	.name = "ctl_0", .id = CTL_0,
34 	.base = 0x1000, .len = 0x1dc,
35 	.features = BIT(DPU_CTL_ACTIVE_CFG),
36 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
37 	},
38 };
39 
40 static const struct dpu_sspp_cfg qcm2290_sspp[] = {
41 	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_QCM2290_MASK,
42 		 qcm2290_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
43 	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
44 		 qcm2290_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
45 };
46 
47 static const struct dpu_lm_cfg qcm2290_lm[] = {
48 	LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
49 		&qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
50 };
51 
52 static const struct dpu_dspp_cfg qcm2290_dspp[] = {
53 	DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
54 		 &sdm845_dspp_sblk),
55 };
56 
57 static const struct dpu_pingpong_cfg qcm2290_pp[] = {
58 	PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
59 		DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
60 		-1),
61 };
62 
63 static const struct dpu_intf_cfg qcm2290_intf[] = {
64 	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
65 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
66 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
67 			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
68 };
69 
70 static const struct dpu_perf_cfg qcm2290_perf_data = {
71 	.max_bw_low = 2700000,
72 	.max_bw_high = 2700000,
73 	.min_core_ib = 1300000,
74 	.min_llcc_ib = 0,
75 	.min_dram_ib = 1600000,
76 	.min_prefill_lines = 24,
77 	.danger_lut_tbl = {0xff, 0x0, 0x0},
78 	.safe_lut_tbl = {0xfff0, 0x0, 0x0},
79 	.qos_lut_tbl = {
80 		{.nentry = ARRAY_SIZE(qcm2290_qos_linear),
81 		.entries = qcm2290_qos_linear
82 		},
83 	},
84 	.cdp_cfg = {
85 		{.rd_enable = 1, .wr_enable = 1},
86 		{.rd_enable = 1, .wr_enable = 0}
87 	},
88 	.clk_inefficiency_factor = 105,
89 	.bw_inefficiency_factor = 120,
90 };
91 
92 const struct dpu_mdss_cfg dpu_qcm2290_cfg = {
93 	.caps = &qcm2290_dpu_caps,
94 	.ubwc = &qcm2290_ubwc_cfg,
95 	.mdp = &qcm2290_mdp,
96 	.ctl_count = ARRAY_SIZE(qcm2290_ctl),
97 	.ctl = qcm2290_ctl,
98 	.sspp_count = ARRAY_SIZE(qcm2290_sspp),
99 	.sspp = qcm2290_sspp,
100 	.mixer_count = ARRAY_SIZE(qcm2290_lm),
101 	.mixer = qcm2290_lm,
102 	.dspp_count = ARRAY_SIZE(qcm2290_dspp),
103 	.dspp = qcm2290_dspp,
104 	.pingpong_count = ARRAY_SIZE(qcm2290_pp),
105 	.pingpong = qcm2290_pp,
106 	.intf_count = ARRAY_SIZE(qcm2290_intf),
107 	.intf = qcm2290_intf,
108 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
109 	.vbif = sdm845_vbif,
110 	.perf = &qcm2290_perf_data,
111 	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
112 		     BIT(MDP_SSPP_TOP0_INTR2) | \
113 		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
114 		     BIT(MDP_INTF1_INTR) | \
115 		     BIT(MDP_INTF1_TEAR_INTR),
116 };
117 
118 #endif
119