1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
4  * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
5  */
6 
7 #ifndef _DPU_6_5_QCM2290_H
8 #define _DPU_6_5_QCM2290_H
9 
10 static const struct dpu_caps qcm2290_dpu_caps = {
11 	.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
12 	.max_mixer_blendstages = 0x4,
13 	.has_dim_layer = true,
14 	.has_idle_pc = true,
15 	.max_linewidth = 2160,
16 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
17 };
18 
19 static const struct dpu_ubwc_cfg qcm2290_ubwc_cfg = {
20 	.highest_bank_bit = 0x2,
21 };
22 
23 static const struct dpu_mdp_cfg qcm2290_mdp = {
24 	.name = "top_0",
25 	.base = 0x0, .len = 0x494,
26 	.clk_ctrls = {
27 		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
29 	},
30 };
31 
32 static const struct dpu_ctl_cfg qcm2290_ctl[] = {
33 	{
34 		.name = "ctl_0", .id = CTL_0,
35 		.base = 0x1000, .len = 0x1dc,
36 		.features = BIT(DPU_CTL_ACTIVE_CFG),
37 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
38 	},
39 };
40 
41 static const struct dpu_sspp_cfg qcm2290_sspp[] = {
42 	{
43 		.name = "sspp_0", .id = SSPP_VIG0,
44 		.base = 0x4000, .len = 0x1f8,
45 		.features = VIG_QCM2290_MASK,
46 		.sblk = &qcm2290_vig_sblk_0,
47 		.xin_id = 0,
48 		.type = SSPP_TYPE_VIG,
49 		.clk_ctrl = DPU_CLK_CTRL_VIG0,
50 	}, {
51 		.name = "sspp_8", .id = SSPP_DMA0,
52 		.base = 0x24000, .len = 0x1f8,
53 		.features = DMA_SDM845_MASK,
54 		.sblk = &qcm2290_dma_sblk_0,
55 		.xin_id = 1,
56 		.type = SSPP_TYPE_DMA,
57 		.clk_ctrl = DPU_CLK_CTRL_DMA0,
58 	},
59 };
60 
61 static const struct dpu_lm_cfg qcm2290_lm[] = {
62 	{
63 		.name = "lm_0", .id = LM_0,
64 		.base = 0x44000, .len = 0x320,
65 		.features = MIXER_QCM2290_MASK,
66 		.sblk = &qcm2290_lm_sblk,
67 		.pingpong = PINGPONG_0,
68 		.dspp = DSPP_0,
69 	},
70 };
71 
72 static const struct dpu_dspp_cfg qcm2290_dspp[] = {
73 	{
74 		.name = "dspp_0", .id = DSPP_0,
75 		.base = 0x54000, .len = 0x1800,
76 		.features = DSPP_SC7180_MASK,
77 		.sblk = &sdm845_dspp_sblk,
78 	},
79 };
80 
81 static const struct dpu_pingpong_cfg qcm2290_pp[] = {
82 	{
83 		.name = "pingpong_0", .id = PINGPONG_0,
84 		.base = 0x70000, .len = 0xd4,
85 		.features = PINGPONG_SM8150_MASK,
86 		.sblk = &sdm845_pp_sblk,
87 		.merge_3d = 0,
88 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
89 		.intr_rdptr = -1,
90 	},
91 };
92 
93 static const struct dpu_intf_cfg qcm2290_intf[] = {
94 	{
95 		.name = "intf_1", .id = INTF_1,
96 		.base = 0x6a800, .len = 0x2c0,
97 		.features = INTF_SC7180_MASK,
98 		.type = INTF_DSI,
99 		.controller_id = MSM_DSI_CONTROLLER_0,
100 		.prog_fetch_lines_worst_case = 24,
101 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
102 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
103 		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
104 	},
105 };
106 
107 static const struct dpu_perf_cfg qcm2290_perf_data = {
108 	.max_bw_low = 2700000,
109 	.max_bw_high = 2700000,
110 	.min_core_ib = 1300000,
111 	.min_llcc_ib = 0,
112 	.min_dram_ib = 1600000,
113 	.min_prefill_lines = 24,
114 	.danger_lut_tbl = {0xff, 0x0, 0x0},
115 	.safe_lut_tbl = {0xfff0, 0x0, 0x0},
116 	.qos_lut_tbl = {
117 		{.nentry = ARRAY_SIZE(qcm2290_qos_linear),
118 		.entries = qcm2290_qos_linear
119 		},
120 	},
121 	.cdp_cfg = {
122 		{.rd_enable = 1, .wr_enable = 1},
123 		{.rd_enable = 1, .wr_enable = 0}
124 	},
125 	.clk_inefficiency_factor = 105,
126 	.bw_inefficiency_factor = 120,
127 };
128 
129 static const struct dpu_mdss_version qcm2290_mdss_ver = {
130 	.core_major_ver = 6,
131 	.core_minor_ver = 5,
132 };
133 
134 const struct dpu_mdss_cfg dpu_qcm2290_cfg = {
135 	.mdss_ver = &qcm2290_mdss_ver,
136 	.caps = &qcm2290_dpu_caps,
137 	.ubwc = &qcm2290_ubwc_cfg,
138 	.mdp = &qcm2290_mdp,
139 	.ctl_count = ARRAY_SIZE(qcm2290_ctl),
140 	.ctl = qcm2290_ctl,
141 	.sspp_count = ARRAY_SIZE(qcm2290_sspp),
142 	.sspp = qcm2290_sspp,
143 	.mixer_count = ARRAY_SIZE(qcm2290_lm),
144 	.mixer = qcm2290_lm,
145 	.dspp_count = ARRAY_SIZE(qcm2290_dspp),
146 	.dspp = qcm2290_dspp,
147 	.pingpong_count = ARRAY_SIZE(qcm2290_pp),
148 	.pingpong = qcm2290_pp,
149 	.intf_count = ARRAY_SIZE(qcm2290_intf),
150 	.intf = qcm2290_intf,
151 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
152 	.vbif = sdm845_vbif,
153 	.perf = &qcm2290_perf_data,
154 };
155 
156 #endif
157