1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 * Copyright (c) 2023, Linaro Limited 6 */ 7 8 #ifndef _DPU_6_4_SM6350_H 9 #define _DPU_6_4_SM6350_H 10 11 static const struct dpu_caps sm6350_dpu_caps = { 12 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 13 .max_mixer_blendstages = 0x7, 14 .qseed_type = DPU_SSPP_SCALER_QSEED4, 15 .has_src_split = true, 16 .has_dim_layer = true, 17 .has_idle_pc = true, 18 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 19 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20 }; 21 22 static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = { 23 .ubwc_version = DPU_HW_UBWC_VER_20, 24 .ubwc_swizzle = 6, 25 .highest_bank_bit = 1, 26 }; 27 28 static const struct dpu_mdp_cfg sm6350_mdp[] = { 29 { 30 .name = "top_0", .id = MDP_TOP, 31 .base = 0x0, .len = 0x494, 32 .features = 0, 33 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 34 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 35 .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 36 .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 37 .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 38 }, 39 }; 40 41 static const struct dpu_ctl_cfg sm6350_ctl[] = { 42 { 43 .name = "ctl_0", .id = CTL_0, 44 .base = 0x1000, .len = 0x1dc, 45 .features = BIT(DPU_CTL_ACTIVE_CFG), 46 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 47 }, 48 { 49 .name = "ctl_1", .id = CTL_1, 50 .base = 0x1200, .len = 0x1dc, 51 .features = BIT(DPU_CTL_ACTIVE_CFG), 52 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 53 }, 54 { 55 .name = "ctl_2", .id = CTL_2, 56 .base = 0x1400, .len = 0x1dc, 57 .features = BIT(DPU_CTL_ACTIVE_CFG), 58 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 59 }, 60 { 61 .name = "ctl_3", .id = CTL_3, 62 .base = 0x1600, .len = 0x1dc, 63 .features = BIT(DPU_CTL_ACTIVE_CFG), 64 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 65 }, 66 }; 67 68 static const struct dpu_sspp_cfg sm6350_sspp[] = { 69 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, 70 sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 71 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, 72 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 73 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK, 74 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 75 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK, 76 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), 77 }; 78 79 static const struct dpu_lm_cfg sm6350_lm[] = { 80 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 81 &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0), 82 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, 83 &sc7180_lm_sblk, PINGPONG_1, LM_0, 0), 84 }; 85 86 static const struct dpu_dspp_cfg sm6350_dspp[] = { 87 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 88 &sm8150_dspp_sblk), 89 }; 90 91 static struct dpu_pingpong_cfg sm6350_pp[] = { 92 PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk, 93 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 94 -1), 95 PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk, 96 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 97 -1), 98 }; 99 100 static const struct dpu_dsc_cfg sm6350_dsc[] = { 101 DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), 102 }; 103 104 static const struct dpu_intf_cfg sm6350_intf[] = { 105 INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 35, INTF_SC7180_MASK, 106 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 107 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), 108 INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK, 109 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 110 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 111 DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), 112 }; 113 114 static const struct dpu_perf_cfg sm6350_perf_data = { 115 .max_bw_low = 4200000, 116 .max_bw_high = 5100000, 117 .min_core_ib = 2500000, 118 .min_llcc_ib = 0, 119 .min_dram_ib = 1600000, 120 .min_prefill_lines = 35, 121 /* TODO: confirm danger_lut_tbl */ 122 .danger_lut_tbl = {0xffff, 0xffff, 0x0}, 123 .safe_lut_tbl = {0xff00, 0xff00, 0xffff}, 124 .qos_lut_tbl = { 125 {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), 126 .entries = sm6350_qos_linear_macrotile 127 }, 128 {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), 129 .entries = sm6350_qos_linear_macrotile 130 }, 131 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 132 .entries = sc7180_qos_nrt 133 }, 134 }, 135 .cdp_cfg = { 136 {.rd_enable = 1, .wr_enable = 1}, 137 {.rd_enable = 1, .wr_enable = 0} 138 }, 139 .clk_inefficiency_factor = 105, 140 .bw_inefficiency_factor = 120, 141 }; 142 143 const struct dpu_mdss_cfg dpu_sm6350_cfg = { 144 .caps = &sm6350_dpu_caps, 145 .ubwc = &sm6350_ubwc_cfg, 146 .mdp_count = ARRAY_SIZE(sm6350_mdp), 147 .mdp = sm6350_mdp, 148 .ctl_count = ARRAY_SIZE(sm6350_ctl), 149 .ctl = sm6350_ctl, 150 .sspp_count = ARRAY_SIZE(sm6350_sspp), 151 .sspp = sm6350_sspp, 152 .mixer_count = ARRAY_SIZE(sm6350_lm), 153 .mixer = sm6350_lm, 154 .dspp_count = ARRAY_SIZE(sm6350_dspp), 155 .dspp = sm6350_dspp, 156 .dsc_count = ARRAY_SIZE(sm6350_dsc), 157 .dsc = sm6350_dsc, 158 .pingpong_count = ARRAY_SIZE(sm6350_pp), 159 .pingpong = sm6350_pp, 160 .intf_count = ARRAY_SIZE(sm6350_intf), 161 .intf = sm6350_intf, 162 .vbif_count = ARRAY_SIZE(sdm845_vbif), 163 .vbif = sdm845_vbif, 164 .perf = &sm6350_perf_data, 165 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 166 BIT(MDP_SSPP_TOP0_INTR2) | \ 167 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 168 BIT(MDP_INTF0_INTR) | \ 169 BIT(MDP_INTF1_INTR) | \ 170 BIT(MDP_INTF1_TEAR_INTR), 171 }; 172 173 #endif 174