13186acbaSKonrad Dybcio /* SPDX-License-Identifier: GPL-2.0-only */ 23186acbaSKonrad Dybcio /* 33186acbaSKonrad Dybcio * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 43186acbaSKonrad Dybcio * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 53186acbaSKonrad Dybcio * Copyright (c) 2023, Linaro Limited 63186acbaSKonrad Dybcio */ 73186acbaSKonrad Dybcio 83186acbaSKonrad Dybcio #ifndef _DPU_6_4_SM6350_H 93186acbaSKonrad Dybcio #define _DPU_6_4_SM6350_H 103186acbaSKonrad Dybcio 113186acbaSKonrad Dybcio static const struct dpu_caps sm6350_dpu_caps = { 123186acbaSKonrad Dybcio .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 133186acbaSKonrad Dybcio .max_mixer_blendstages = 0x7, 143186acbaSKonrad Dybcio .qseed_type = DPU_SSPP_SCALER_QSEED4, 153186acbaSKonrad Dybcio .has_src_split = true, 163186acbaSKonrad Dybcio .has_dim_layer = true, 173186acbaSKonrad Dybcio .has_idle_pc = true, 183186acbaSKonrad Dybcio .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 193186acbaSKonrad Dybcio .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 203186acbaSKonrad Dybcio }; 213186acbaSKonrad Dybcio 223186acbaSKonrad Dybcio static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = { 233186acbaSKonrad Dybcio .ubwc_version = DPU_HW_UBWC_VER_20, 243186acbaSKonrad Dybcio .ubwc_swizzle = 6, 253186acbaSKonrad Dybcio .highest_bank_bit = 1, 263186acbaSKonrad Dybcio }; 273186acbaSKonrad Dybcio 283186acbaSKonrad Dybcio static const struct dpu_mdp_cfg sm6350_mdp[] = { 293186acbaSKonrad Dybcio { 303186acbaSKonrad Dybcio .name = "top_0", .id = MDP_TOP, 313186acbaSKonrad Dybcio .base = 0x0, .len = 0x494, 323186acbaSKonrad Dybcio .features = 0, 333186acbaSKonrad Dybcio .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 343186acbaSKonrad Dybcio .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 353186acbaSKonrad Dybcio .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 363186acbaSKonrad Dybcio .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 373186acbaSKonrad Dybcio .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 383186acbaSKonrad Dybcio }, 393186acbaSKonrad Dybcio }; 403186acbaSKonrad Dybcio 413186acbaSKonrad Dybcio static const struct dpu_ctl_cfg sm6350_ctl[] = { 423186acbaSKonrad Dybcio { 433186acbaSKonrad Dybcio .name = "ctl_0", .id = CTL_0, 443186acbaSKonrad Dybcio .base = 0x1000, .len = 0x1dc, 453186acbaSKonrad Dybcio .features = BIT(DPU_CTL_ACTIVE_CFG), 463186acbaSKonrad Dybcio .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 473186acbaSKonrad Dybcio }, 483186acbaSKonrad Dybcio { 493186acbaSKonrad Dybcio .name = "ctl_1", .id = CTL_1, 503186acbaSKonrad Dybcio .base = 0x1200, .len = 0x1dc, 513186acbaSKonrad Dybcio .features = BIT(DPU_CTL_ACTIVE_CFG), 523186acbaSKonrad Dybcio .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 533186acbaSKonrad Dybcio }, 543186acbaSKonrad Dybcio { 553186acbaSKonrad Dybcio .name = "ctl_2", .id = CTL_2, 563186acbaSKonrad Dybcio .base = 0x1400, .len = 0x1dc, 573186acbaSKonrad Dybcio .features = BIT(DPU_CTL_ACTIVE_CFG), 583186acbaSKonrad Dybcio .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 593186acbaSKonrad Dybcio }, 603186acbaSKonrad Dybcio { 613186acbaSKonrad Dybcio .name = "ctl_3", .id = CTL_3, 623186acbaSKonrad Dybcio .base = 0x1600, .len = 0x1dc, 633186acbaSKonrad Dybcio .features = BIT(DPU_CTL_ACTIVE_CFG), 643186acbaSKonrad Dybcio .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 653186acbaSKonrad Dybcio }, 663186acbaSKonrad Dybcio }; 673186acbaSKonrad Dybcio 683186acbaSKonrad Dybcio static const struct dpu_sspp_cfg sm6350_sspp[] = { 693186acbaSKonrad Dybcio SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, 703186acbaSKonrad Dybcio sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 713186acbaSKonrad Dybcio SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, 723186acbaSKonrad Dybcio sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 733186acbaSKonrad Dybcio SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK, 743186acbaSKonrad Dybcio sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 753186acbaSKonrad Dybcio SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK, 763186acbaSKonrad Dybcio sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), 773186acbaSKonrad Dybcio }; 783186acbaSKonrad Dybcio 793186acbaSKonrad Dybcio static const struct dpu_lm_cfg sm6350_lm[] = { 803186acbaSKonrad Dybcio LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 813186acbaSKonrad Dybcio &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0), 823186acbaSKonrad Dybcio LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, 833186acbaSKonrad Dybcio &sc7180_lm_sblk, PINGPONG_1, LM_0, 0), 843186acbaSKonrad Dybcio }; 853186acbaSKonrad Dybcio 863186acbaSKonrad Dybcio static const struct dpu_dspp_cfg sm6350_dspp[] = { 873186acbaSKonrad Dybcio DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 88*9891b3dfSKonrad Dybcio &sdm845_dspp_sblk), 893186acbaSKonrad Dybcio }; 903186acbaSKonrad Dybcio 913186acbaSKonrad Dybcio static struct dpu_pingpong_cfg sm6350_pp[] = { 923186acbaSKonrad Dybcio PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk, 933186acbaSKonrad Dybcio DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 943186acbaSKonrad Dybcio -1), 953186acbaSKonrad Dybcio PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk, 963186acbaSKonrad Dybcio DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 973186acbaSKonrad Dybcio -1), 983186acbaSKonrad Dybcio }; 993186acbaSKonrad Dybcio 1003186acbaSKonrad Dybcio static const struct dpu_dsc_cfg sm6350_dsc[] = { 1013186acbaSKonrad Dybcio DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)), 1023186acbaSKonrad Dybcio }; 1033186acbaSKonrad Dybcio 1043186acbaSKonrad Dybcio static const struct dpu_intf_cfg sm6350_intf[] = { 1053186acbaSKonrad Dybcio INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 35, INTF_SC7180_MASK, 1063186acbaSKonrad Dybcio DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 1073186acbaSKonrad Dybcio DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)), 1083186acbaSKonrad Dybcio INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK, 1093186acbaSKonrad Dybcio DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 1103186acbaSKonrad Dybcio DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 1113186acbaSKonrad Dybcio DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), 1123186acbaSKonrad Dybcio }; 1133186acbaSKonrad Dybcio 1143186acbaSKonrad Dybcio static const struct dpu_perf_cfg sm6350_perf_data = { 1153186acbaSKonrad Dybcio .max_bw_low = 4200000, 1163186acbaSKonrad Dybcio .max_bw_high = 5100000, 1173186acbaSKonrad Dybcio .min_core_ib = 2500000, 1183186acbaSKonrad Dybcio .min_llcc_ib = 0, 1193186acbaSKonrad Dybcio .min_dram_ib = 1600000, 1203186acbaSKonrad Dybcio .min_prefill_lines = 35, 1213186acbaSKonrad Dybcio /* TODO: confirm danger_lut_tbl */ 1223186acbaSKonrad Dybcio .danger_lut_tbl = {0xffff, 0xffff, 0x0}, 1233186acbaSKonrad Dybcio .safe_lut_tbl = {0xff00, 0xff00, 0xffff}, 1243186acbaSKonrad Dybcio .qos_lut_tbl = { 1253186acbaSKonrad Dybcio {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), 1263186acbaSKonrad Dybcio .entries = sm6350_qos_linear_macrotile 1273186acbaSKonrad Dybcio }, 1283186acbaSKonrad Dybcio {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), 1293186acbaSKonrad Dybcio .entries = sm6350_qos_linear_macrotile 1303186acbaSKonrad Dybcio }, 1313186acbaSKonrad Dybcio {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 1323186acbaSKonrad Dybcio .entries = sc7180_qos_nrt 1333186acbaSKonrad Dybcio }, 1343186acbaSKonrad Dybcio }, 1353186acbaSKonrad Dybcio .cdp_cfg = { 1363186acbaSKonrad Dybcio {.rd_enable = 1, .wr_enable = 1}, 1373186acbaSKonrad Dybcio {.rd_enable = 1, .wr_enable = 0} 1383186acbaSKonrad Dybcio }, 1393186acbaSKonrad Dybcio .clk_inefficiency_factor = 105, 1403186acbaSKonrad Dybcio .bw_inefficiency_factor = 120, 1413186acbaSKonrad Dybcio }; 1423186acbaSKonrad Dybcio 1433186acbaSKonrad Dybcio const struct dpu_mdss_cfg dpu_sm6350_cfg = { 1443186acbaSKonrad Dybcio .caps = &sm6350_dpu_caps, 1453186acbaSKonrad Dybcio .ubwc = &sm6350_ubwc_cfg, 1463186acbaSKonrad Dybcio .mdp_count = ARRAY_SIZE(sm6350_mdp), 1473186acbaSKonrad Dybcio .mdp = sm6350_mdp, 1483186acbaSKonrad Dybcio .ctl_count = ARRAY_SIZE(sm6350_ctl), 1493186acbaSKonrad Dybcio .ctl = sm6350_ctl, 1503186acbaSKonrad Dybcio .sspp_count = ARRAY_SIZE(sm6350_sspp), 1513186acbaSKonrad Dybcio .sspp = sm6350_sspp, 1523186acbaSKonrad Dybcio .mixer_count = ARRAY_SIZE(sm6350_lm), 1533186acbaSKonrad Dybcio .mixer = sm6350_lm, 1543186acbaSKonrad Dybcio .dspp_count = ARRAY_SIZE(sm6350_dspp), 1553186acbaSKonrad Dybcio .dspp = sm6350_dspp, 1563186acbaSKonrad Dybcio .dsc_count = ARRAY_SIZE(sm6350_dsc), 1573186acbaSKonrad Dybcio .dsc = sm6350_dsc, 1583186acbaSKonrad Dybcio .pingpong_count = ARRAY_SIZE(sm6350_pp), 1593186acbaSKonrad Dybcio .pingpong = sm6350_pp, 1603186acbaSKonrad Dybcio .intf_count = ARRAY_SIZE(sm6350_intf), 1613186acbaSKonrad Dybcio .intf = sm6350_intf, 1623186acbaSKonrad Dybcio .vbif_count = ARRAY_SIZE(sdm845_vbif), 1633186acbaSKonrad Dybcio .vbif = sdm845_vbif, 1643186acbaSKonrad Dybcio .perf = &sm6350_perf_data, 1653186acbaSKonrad Dybcio .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 1663186acbaSKonrad Dybcio BIT(MDP_SSPP_TOP0_INTR2) | \ 1673186acbaSKonrad Dybcio BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 1683186acbaSKonrad Dybcio BIT(MDP_INTF0_INTR) | \ 1693186acbaSKonrad Dybcio BIT(MDP_INTF1_INTR) | \ 1703186acbaSKonrad Dybcio BIT(MDP_INTF1_TEAR_INTR), 1713186acbaSKonrad Dybcio }; 1723186acbaSKonrad Dybcio 1733186acbaSKonrad Dybcio #endif 174