1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
4  * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
5  */
6 
7 #ifndef _DPU_6_3_SM6115_H
8 #define _DPU_6_3_SM6115_H
9 
10 static const struct dpu_caps sm6115_dpu_caps = {
11 	.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
12 	.max_mixer_blendstages = 0x4,
13 	.qseed_type = DPU_SSPP_SCALER_QSEED4,
14 	.has_dim_layer = true,
15 	.has_idle_pc = true,
16 	.max_linewidth = 2160,
17 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
18 };
19 
20 static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = {
21 	.ubwc_version = DPU_HW_UBWC_VER_10,
22 	.highest_bank_bit = 0x1,
23 	.ubwc_swizzle = 0x7,
24 };
25 
26 static const struct dpu_mdp_cfg sm6115_mdp[] = {
27 	{
28 	.name = "top_0", .id = MDP_TOP,
29 	.base = 0x0, .len = 0x494,
30 	.features = 0,
31 	.clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
32 	.clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
33 	},
34 };
35 
36 static const struct dpu_ctl_cfg sm6115_ctl[] = {
37 	{
38 	.name = "ctl_0", .id = CTL_0,
39 	.base = 0x1000, .len = 0x1dc,
40 	.features = BIT(DPU_CTL_ACTIVE_CFG),
41 	.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
42 	},
43 };
44 
45 static const struct dpu_sspp_cfg sm6115_sspp[] = {
46 	SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
47 		sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
48 	SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
49 		sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
50 };
51 
52 static const struct dpu_lm_cfg sm6115_lm[] = {
53 	LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
54 		&qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
55 };
56 
57 static const struct dpu_dspp_cfg sm6115_dspp[] = {
58 	DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
59 		 &sm8150_dspp_sblk),
60 };
61 
62 static const struct dpu_pingpong_cfg sm6115_pp[] = {
63 	PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
64 		DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
65 		-1),
66 };
67 
68 static const struct dpu_intf_cfg sm6115_intf[] = {
69 	INTF_BLK("intf_0", INTF_0, 0x00000, 0x280, INTF_NONE, 0, 0, 0, 0, 0),
70 	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
71 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
72 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
73 			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
74 };
75 
76 static const struct dpu_perf_cfg sm6115_perf_data = {
77 	.max_bw_low = 3100000,
78 	.max_bw_high = 4000000,
79 	.min_core_ib = 2400000,
80 	.min_llcc_ib = 800000,
81 	.min_dram_ib = 800000,
82 	.min_prefill_lines = 24,
83 	.danger_lut_tbl = {0xff, 0xffff, 0x0},
84 	.safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
85 	.qos_lut_tbl = {
86 		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
87 		.entries = sc7180_qos_linear
88 		},
89 		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
90 		.entries = sc7180_qos_macrotile
91 		},
92 		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
93 		.entries = sc7180_qos_nrt
94 		},
95 		/* TODO: macrotile-qseed is different from macrotile */
96 	},
97 	.cdp_cfg = {
98 		{.rd_enable = 1, .wr_enable = 1},
99 		{.rd_enable = 1, .wr_enable = 0}
100 	},
101 	.clk_inefficiency_factor = 105,
102 	.bw_inefficiency_factor = 120,
103 };
104 
105 const struct dpu_mdss_cfg dpu_sm6115_cfg = {
106 	.caps = &sm6115_dpu_caps,
107 	.ubwc = &sm6115_ubwc_cfg,
108 	.mdp_count = ARRAY_SIZE(sm6115_mdp),
109 	.mdp = sm6115_mdp,
110 	.ctl_count = ARRAY_SIZE(sm6115_ctl),
111 	.ctl = sm6115_ctl,
112 	.sspp_count = ARRAY_SIZE(sm6115_sspp),
113 	.sspp = sm6115_sspp,
114 	.mixer_count = ARRAY_SIZE(sm6115_lm),
115 	.mixer = sm6115_lm,
116 	.dspp_count = ARRAY_SIZE(sm6115_dspp),
117 	.dspp = sm6115_dspp,
118 	.pingpong_count = ARRAY_SIZE(sm6115_pp),
119 	.pingpong = sm6115_pp,
120 	.intf_count = ARRAY_SIZE(sm6115_intf),
121 	.intf = sm6115_intf,
122 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
123 	.vbif = sdm845_vbif,
124 	.perf = &sm6115_perf_data,
125 	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
126 		     BIT(MDP_SSPP_TOP0_INTR2) | \
127 		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
128 		     BIT(MDP_INTF1_INTR) | \
129 		     BIT(MDP_INTF1_TEAR_INTR),
130 };
131 
132 #endif
133