1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
4  * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
5  */
6 
7 #ifndef _DPU_6_3_SM6115_H
8 #define _DPU_6_3_SM6115_H
9 
10 static const struct dpu_caps sm6115_dpu_caps = {
11 	.max_mixer_width = DEFAULT_DPU_LINE_WIDTH,
12 	.max_mixer_blendstages = 0x4,
13 	.qseed_type = DPU_SSPP_SCALER_QSEED4,
14 	.has_dim_layer = true,
15 	.has_idle_pc = true,
16 	.max_linewidth = 2160,
17 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
18 };
19 
20 static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = {
21 	.ubwc_version = DPU_HW_UBWC_VER_10,
22 	.highest_bank_bit = 0x1,
23 	.ubwc_swizzle = 0x7,
24 };
25 
26 static const struct dpu_mdp_cfg sm6115_mdp = {
27 	.name = "top_0",
28 	.base = 0x0, .len = 0x494,
29 	.clk_ctrls = {
30 		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
31 		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
32 	},
33 };
34 
35 static const struct dpu_ctl_cfg sm6115_ctl[] = {
36 	{
37 		.name = "ctl_0", .id = CTL_0,
38 		.base = 0x1000, .len = 0x1dc,
39 		.features = BIT(DPU_CTL_ACTIVE_CFG),
40 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
41 	},
42 };
43 
44 static const struct dpu_sspp_cfg sm6115_sspp[] = {
45 	{
46 		.name = "sspp_0", .id = SSPP_VIG0,
47 		.base = 0x4000, .len = 0x1f8,
48 		.features = VIG_SC7180_MASK,
49 		.sblk = &sm6115_vig_sblk_0,
50 		.xin_id = 0,
51 		.type = SSPP_TYPE_VIG,
52 		.clk_ctrl = DPU_CLK_CTRL_VIG0,
53 	}, {
54 		.name = "sspp_8", .id = SSPP_DMA0,
55 		.base = 0x24000, .len = 0x1f8,
56 		.features = DMA_SDM845_MASK,
57 		.sblk = &sdm845_dma_sblk_0,
58 		.xin_id = 1,
59 		.type = SSPP_TYPE_DMA,
60 		.clk_ctrl = DPU_CLK_CTRL_DMA0,
61 	},
62 };
63 
64 static const struct dpu_lm_cfg sm6115_lm[] = {
65 	LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK,
66 		&qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0),
67 };
68 
69 static const struct dpu_dspp_cfg sm6115_dspp[] = {
70 	{
71 		.name = "dspp_0", .id = DSPP_0,
72 		.base = 0x54000, .len = 0x1800,
73 		.features = DSPP_SC7180_MASK,
74 		.sblk = &sdm845_dspp_sblk,
75 	},
76 };
77 
78 static const struct dpu_pingpong_cfg sm6115_pp[] = {
79 	PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
80 		DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
81 		-1),
82 };
83 
84 static const struct dpu_intf_cfg sm6115_intf[] = {
85 	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
86 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
87 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
88 			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
89 };
90 
91 static const struct dpu_perf_cfg sm6115_perf_data = {
92 	.max_bw_low = 3100000,
93 	.max_bw_high = 4000000,
94 	.min_core_ib = 2400000,
95 	.min_llcc_ib = 800000,
96 	.min_dram_ib = 800000,
97 	.min_prefill_lines = 24,
98 	.danger_lut_tbl = {0xff, 0xffff, 0x0},
99 	.safe_lut_tbl = {0xfff0, 0xff00, 0xffff},
100 	.qos_lut_tbl = {
101 		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
102 		.entries = sc7180_qos_linear
103 		},
104 		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
105 		.entries = sc7180_qos_macrotile
106 		},
107 		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
108 		.entries = sc7180_qos_nrt
109 		},
110 		/* TODO: macrotile-qseed is different from macrotile */
111 	},
112 	.cdp_cfg = {
113 		{.rd_enable = 1, .wr_enable = 1},
114 		{.rd_enable = 1, .wr_enable = 0}
115 	},
116 	.clk_inefficiency_factor = 105,
117 	.bw_inefficiency_factor = 120,
118 };
119 
120 const struct dpu_mdss_cfg dpu_sm6115_cfg = {
121 	.caps = &sm6115_dpu_caps,
122 	.ubwc = &sm6115_ubwc_cfg,
123 	.mdp = &sm6115_mdp,
124 	.ctl_count = ARRAY_SIZE(sm6115_ctl),
125 	.ctl = sm6115_ctl,
126 	.sspp_count = ARRAY_SIZE(sm6115_sspp),
127 	.sspp = sm6115_sspp,
128 	.mixer_count = ARRAY_SIZE(sm6115_lm),
129 	.mixer = sm6115_lm,
130 	.dspp_count = ARRAY_SIZE(sm6115_dspp),
131 	.dspp = sm6115_dspp,
132 	.pingpong_count = ARRAY_SIZE(sm6115_pp),
133 	.pingpong = sm6115_pp,
134 	.intf_count = ARRAY_SIZE(sm6115_intf),
135 	.intf = sm6115_intf,
136 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
137 	.vbif = sdm845_vbif,
138 	.perf = &sm6115_perf_data,
139 	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
140 		     BIT(MDP_SSPP_TOP0_INTR2) | \
141 		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
142 		     BIT(MDP_INTF1_INTR) | \
143 		     BIT(MDP_INTF1_TEAR_INTR),
144 };
145 
146 #endif
147