1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_6_3_SM6115_H 8 #define _DPU_6_3_SM6115_H 9 10 static const struct dpu_caps sm6115_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, 12 .max_mixer_blendstages = 0x4, 13 .qseed_type = DPU_SSPP_SCALER_QSEED4, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .max_linewidth = 2160, 17 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18 }; 19 20 static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = { 21 .ubwc_version = DPU_HW_UBWC_VER_10, 22 .highest_bank_bit = 0x1, 23 .ubwc_swizzle = 0x7, 24 }; 25 26 static const struct dpu_mdp_cfg sm6115_mdp = { 27 .name = "top_0", 28 .base = 0x0, .len = 0x494, 29 .clk_ctrls = { 30 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 32 }, 33 }; 34 35 static const struct dpu_ctl_cfg sm6115_ctl[] = { 36 { 37 .name = "ctl_0", .id = CTL_0, 38 .base = 0x1000, .len = 0x1dc, 39 .features = BIT(DPU_CTL_ACTIVE_CFG), 40 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 41 }, 42 }; 43 44 static const struct dpu_sspp_cfg sm6115_sspp[] = { 45 { 46 .name = "sspp_0", .id = SSPP_VIG0, 47 .base = 0x4000, .len = 0x1f8, 48 .features = VIG_SC7180_MASK, 49 .sblk = &sm6115_vig_sblk_0, 50 .xin_id = 0, 51 .type = SSPP_TYPE_VIG, 52 .clk_ctrl = DPU_CLK_CTRL_VIG0, 53 }, { 54 .name = "sspp_8", .id = SSPP_DMA0, 55 .base = 0x24000, .len = 0x1f8, 56 .features = DMA_SDM845_MASK, 57 .sblk = &sdm845_dma_sblk_0, 58 .xin_id = 1, 59 .type = SSPP_TYPE_DMA, 60 .clk_ctrl = DPU_CLK_CTRL_DMA0, 61 }, 62 }; 63 64 static const struct dpu_lm_cfg sm6115_lm[] = { 65 { 66 .name = "lm_0", .id = LM_0, 67 .base = 0x44000, .len = 0x320, 68 .features = MIXER_QCM2290_MASK, 69 .sblk = &qcm2290_lm_sblk, 70 .pingpong = PINGPONG_0, 71 .dspp = DSPP_0, 72 }, 73 }; 74 75 static const struct dpu_dspp_cfg sm6115_dspp[] = { 76 { 77 .name = "dspp_0", .id = DSPP_0, 78 .base = 0x54000, .len = 0x1800, 79 .features = DSPP_SC7180_MASK, 80 .sblk = &sdm845_dspp_sblk, 81 }, 82 }; 83 84 static const struct dpu_pingpong_cfg sm6115_pp[] = { 85 PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk, 86 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 87 -1), 88 }; 89 90 static const struct dpu_intf_cfg sm6115_intf[] = { 91 INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK, 92 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 93 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 94 DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), 95 }; 96 97 static const struct dpu_perf_cfg sm6115_perf_data = { 98 .max_bw_low = 3100000, 99 .max_bw_high = 4000000, 100 .min_core_ib = 2400000, 101 .min_llcc_ib = 800000, 102 .min_dram_ib = 800000, 103 .min_prefill_lines = 24, 104 .danger_lut_tbl = {0xff, 0xffff, 0x0}, 105 .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, 106 .qos_lut_tbl = { 107 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 108 .entries = sc7180_qos_linear 109 }, 110 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 111 .entries = sc7180_qos_macrotile 112 }, 113 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 114 .entries = sc7180_qos_nrt 115 }, 116 /* TODO: macrotile-qseed is different from macrotile */ 117 }, 118 .cdp_cfg = { 119 {.rd_enable = 1, .wr_enable = 1}, 120 {.rd_enable = 1, .wr_enable = 0} 121 }, 122 .clk_inefficiency_factor = 105, 123 .bw_inefficiency_factor = 120, 124 }; 125 126 const struct dpu_mdss_cfg dpu_sm6115_cfg = { 127 .caps = &sm6115_dpu_caps, 128 .ubwc = &sm6115_ubwc_cfg, 129 .mdp = &sm6115_mdp, 130 .ctl_count = ARRAY_SIZE(sm6115_ctl), 131 .ctl = sm6115_ctl, 132 .sspp_count = ARRAY_SIZE(sm6115_sspp), 133 .sspp = sm6115_sspp, 134 .mixer_count = ARRAY_SIZE(sm6115_lm), 135 .mixer = sm6115_lm, 136 .dspp_count = ARRAY_SIZE(sm6115_dspp), 137 .dspp = sm6115_dspp, 138 .pingpong_count = ARRAY_SIZE(sm6115_pp), 139 .pingpong = sm6115_pp, 140 .intf_count = ARRAY_SIZE(sm6115_intf), 141 .intf = sm6115_intf, 142 .vbif_count = ARRAY_SIZE(sdm845_vbif), 143 .vbif = sdm845_vbif, 144 .perf = &sm6115_perf_data, 145 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 146 BIT(MDP_SSPP_TOP0_INTR2) | \ 147 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 148 BIT(MDP_INTF1_INTR) | \ 149 BIT(MDP_INTF1_TEAR_INTR), 150 }; 151 152 #endif 153