1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_6_3_SM6115_H 8 #define _DPU_6_3_SM6115_H 9 10 static const struct dpu_caps sm6115_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, 12 .max_mixer_blendstages = 0x4, 13 .qseed_type = DPU_SSPP_SCALER_QSEED4, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .max_linewidth = 2160, 17 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18 }; 19 20 static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = { 21 .ubwc_version = DPU_HW_UBWC_VER_10, 22 .highest_bank_bit = 0x1, 23 .ubwc_swizzle = 0x7, 24 }; 25 26 static const struct dpu_mdp_cfg sm6115_mdp = { 27 .name = "top_0", 28 .base = 0x0, .len = 0x494, 29 .features = 0, 30 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 31 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 32 }; 33 34 static const struct dpu_ctl_cfg sm6115_ctl[] = { 35 { 36 .name = "ctl_0", .id = CTL_0, 37 .base = 0x1000, .len = 0x1dc, 38 .features = BIT(DPU_CTL_ACTIVE_CFG), 39 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 40 }, 41 }; 42 43 static const struct dpu_sspp_cfg sm6115_sspp[] = { 44 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, 45 sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 46 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, 47 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 48 }; 49 50 static const struct dpu_lm_cfg sm6115_lm[] = { 51 LM_BLK("lm_0", LM_0, 0x44000, MIXER_QCM2290_MASK, 52 &qcm2290_lm_sblk, PINGPONG_0, 0, DSPP_0), 53 }; 54 55 static const struct dpu_dspp_cfg sm6115_dspp[] = { 56 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 57 &sdm845_dspp_sblk), 58 }; 59 60 static const struct dpu_pingpong_cfg sm6115_pp[] = { 61 PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk, 62 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 63 -1), 64 }; 65 66 static const struct dpu_intf_cfg sm6115_intf[] = { 67 INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK, 68 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 69 DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 70 DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)), 71 }; 72 73 static const struct dpu_perf_cfg sm6115_perf_data = { 74 .max_bw_low = 3100000, 75 .max_bw_high = 4000000, 76 .min_core_ib = 2400000, 77 .min_llcc_ib = 800000, 78 .min_dram_ib = 800000, 79 .min_prefill_lines = 24, 80 .danger_lut_tbl = {0xff, 0xffff, 0x0}, 81 .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, 82 .qos_lut_tbl = { 83 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 84 .entries = sc7180_qos_linear 85 }, 86 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 87 .entries = sc7180_qos_macrotile 88 }, 89 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 90 .entries = sc7180_qos_nrt 91 }, 92 /* TODO: macrotile-qseed is different from macrotile */ 93 }, 94 .cdp_cfg = { 95 {.rd_enable = 1, .wr_enable = 1}, 96 {.rd_enable = 1, .wr_enable = 0} 97 }, 98 .clk_inefficiency_factor = 105, 99 .bw_inefficiency_factor = 120, 100 }; 101 102 const struct dpu_mdss_cfg dpu_sm6115_cfg = { 103 .caps = &sm6115_dpu_caps, 104 .ubwc = &sm6115_ubwc_cfg, 105 .mdp = &sm6115_mdp, 106 .ctl_count = ARRAY_SIZE(sm6115_ctl), 107 .ctl = sm6115_ctl, 108 .sspp_count = ARRAY_SIZE(sm6115_sspp), 109 .sspp = sm6115_sspp, 110 .mixer_count = ARRAY_SIZE(sm6115_lm), 111 .mixer = sm6115_lm, 112 .dspp_count = ARRAY_SIZE(sm6115_dspp), 113 .dspp = sm6115_dspp, 114 .pingpong_count = ARRAY_SIZE(sm6115_pp), 115 .pingpong = sm6115_pp, 116 .intf_count = ARRAY_SIZE(sm6115_intf), 117 .intf = sm6115_intf, 118 .vbif_count = ARRAY_SIZE(sdm845_vbif), 119 .vbif = sdm845_vbif, 120 .perf = &sm6115_perf_data, 121 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 122 BIT(MDP_SSPP_TOP0_INTR2) | \ 123 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 124 BIT(MDP_INTF1_INTR) | \ 125 BIT(MDP_INTF1_TEAR_INTR), 126 }; 127 128 #endif 129