1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_6_3_SM6115_H 8 #define _DPU_6_3_SM6115_H 9 10 static const struct dpu_caps sm6115_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, 12 .max_mixer_blendstages = 0x4, 13 .qseed_type = DPU_SSPP_SCALER_QSEED4, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .max_linewidth = 2160, 17 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18 }; 19 20 static const struct dpu_ubwc_cfg sm6115_ubwc_cfg = { 21 .ubwc_version = DPU_HW_UBWC_VER_10, 22 .highest_bank_bit = 0x1, 23 .ubwc_swizzle = 0x7, 24 }; 25 26 static const struct dpu_mdp_cfg sm6115_mdp[] = { 27 { 28 .name = "top_0", .id = MDP_TOP, 29 .base = 0x0, .len = 0x494, 30 .features = 0, 31 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 32 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 33 }, 34 }; 35 36 static const struct dpu_sspp_cfg sm6115_sspp[] = { 37 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, 38 sm6115_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 39 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, 40 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 41 }; 42 43 static const struct dpu_perf_cfg sm6115_perf_data = { 44 .max_bw_low = 3100000, 45 .max_bw_high = 4000000, 46 .min_core_ib = 2400000, 47 .min_llcc_ib = 800000, 48 .min_dram_ib = 800000, 49 .min_prefill_lines = 24, 50 .danger_lut_tbl = {0xff, 0xffff, 0x0}, 51 .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, 52 .qos_lut_tbl = { 53 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 54 .entries = sc7180_qos_linear 55 }, 56 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 57 .entries = sc7180_qos_macrotile 58 }, 59 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 60 .entries = sc7180_qos_nrt 61 }, 62 /* TODO: macrotile-qseed is different from macrotile */ 63 }, 64 .cdp_cfg = { 65 {.rd_enable = 1, .wr_enable = 1}, 66 {.rd_enable = 1, .wr_enable = 0} 67 }, 68 .clk_inefficiency_factor = 105, 69 .bw_inefficiency_factor = 120, 70 }; 71 72 static const struct dpu_mdss_cfg sm6115_dpu_cfg = { 73 .caps = &sm6115_dpu_caps, 74 .ubwc = &sm6115_ubwc_cfg, 75 .mdp_count = ARRAY_SIZE(sm6115_mdp), 76 .mdp = sm6115_mdp, 77 .ctl_count = ARRAY_SIZE(qcm2290_ctl), 78 .ctl = qcm2290_ctl, 79 .sspp_count = ARRAY_SIZE(sm6115_sspp), 80 .sspp = sm6115_sspp, 81 .mixer_count = ARRAY_SIZE(qcm2290_lm), 82 .mixer = qcm2290_lm, 83 .dspp_count = ARRAY_SIZE(qcm2290_dspp), 84 .dspp = qcm2290_dspp, 85 .pingpong_count = ARRAY_SIZE(qcm2290_pp), 86 .pingpong = qcm2290_pp, 87 .intf_count = ARRAY_SIZE(qcm2290_intf), 88 .intf = qcm2290_intf, 89 .vbif_count = ARRAY_SIZE(sdm845_vbif), 90 .vbif = sdm845_vbif, 91 .perf = &sm6115_perf_data, 92 .mdss_irqs = IRQ_SC7180_MASK, 93 }; 94 95 #endif 96