1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_6_2_SC7180_H 8 #define _DPU_6_2_SC7180_H 9 10 static const struct dpu_caps sc7180_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0x9, 13 .qseed_type = DPU_SSPP_SCALER_QSEED4, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 17 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18 }; 19 20 static const struct dpu_ubwc_cfg sc7180_ubwc_cfg = { 21 .ubwc_version = DPU_HW_UBWC_VER_20, 22 .highest_bank_bit = 0x3, 23 }; 24 25 static const struct dpu_mdp_cfg sc7180_mdp[] = { 26 { 27 .name = "top_0", .id = MDP_TOP, 28 .base = 0x0, .len = 0x494, 29 .features = 0, 30 .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 31 .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 32 .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 33 .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 34 .clk_ctrls[DPU_CLK_CTRL_WB2] = { .reg_off = 0x3b8, .bit_off = 24 }, 35 }, 36 }; 37 38 static const struct dpu_ctl_cfg sc7180_ctl[] = { 39 { 40 .name = "ctl_0", .id = CTL_0, 41 .base = 0x1000, .len = 0x1dc, 42 .features = BIT(DPU_CTL_ACTIVE_CFG), 43 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 44 }, 45 { 46 .name = "ctl_1", .id = CTL_1, 47 .base = 0x1200, .len = 0x1dc, 48 .features = BIT(DPU_CTL_ACTIVE_CFG), 49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 50 }, 51 { 52 .name = "ctl_2", .id = CTL_2, 53 .base = 0x1400, .len = 0x1dc, 54 .features = BIT(DPU_CTL_ACTIVE_CFG), 55 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 56 }, 57 }; 58 59 static const struct dpu_sspp_cfg sc7180_sspp[] = { 60 SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK, 61 sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0), 62 SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK, 63 sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0), 64 SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK, 65 sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1), 66 SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK, 67 sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2), 68 }; 69 70 static const struct dpu_lm_cfg sc7180_lm[] = { 71 LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, 72 &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0), 73 LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, 74 &sc7180_lm_sblk, PINGPONG_1, LM_0, 0), 75 }; 76 77 static const struct dpu_dspp_cfg sc7180_dspp[] = { 78 DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK, 79 &sc7180_dspp_sblk), 80 }; 81 82 static const struct dpu_pingpong_cfg sc7180_pp[] = { 83 PP_BLK_TE("pingpong_0", PINGPONG_0, 0x70000, 0, sdm845_pp_sblk_te, -1, -1), 84 PP_BLK_TE("pingpong_1", PINGPONG_1, 0x70800, 0, sdm845_pp_sblk_te, -1, -1), 85 }; 86 87 static const struct dpu_intf_cfg sc7180_intf[] = { 88 INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 24, 25), 89 INTF_BLK("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK, MDP_SSPP_TOP0_INTR, 26, 27), 90 }; 91 92 static const struct dpu_wb_cfg sc7180_wb[] = { 93 WB_BLK("wb_2", WB_2, 0x65000, WB_SM8250_MASK, DPU_CLK_CTRL_WB2, 6, 94 VBIF_RT, MDP_SSPP_TOP0_INTR, 4096, 4), 95 }; 96 97 static const struct dpu_perf_cfg sc7180_perf_data = { 98 .max_bw_low = 6800000, 99 .max_bw_high = 6800000, 100 .min_core_ib = 2400000, 101 .min_llcc_ib = 800000, 102 .min_dram_ib = 1600000, 103 .min_prefill_lines = 24, 104 .danger_lut_tbl = {0xff, 0xffff, 0x0}, 105 .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, 106 .qos_lut_tbl = { 107 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 108 .entries = sc7180_qos_linear 109 }, 110 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 111 .entries = sc7180_qos_macrotile 112 }, 113 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 114 .entries = sc7180_qos_nrt 115 }, 116 }, 117 .cdp_cfg = { 118 {.rd_enable = 1, .wr_enable = 1}, 119 {.rd_enable = 1, .wr_enable = 0} 120 }, 121 .clk_inefficiency_factor = 105, 122 .bw_inefficiency_factor = 120, 123 }; 124 125 const struct dpu_mdss_cfg dpu_sc7180_cfg = { 126 .caps = &sc7180_dpu_caps, 127 .ubwc = &sc7180_ubwc_cfg, 128 .mdp_count = ARRAY_SIZE(sc7180_mdp), 129 .mdp = sc7180_mdp, 130 .ctl_count = ARRAY_SIZE(sc7180_ctl), 131 .ctl = sc7180_ctl, 132 .sspp_count = ARRAY_SIZE(sc7180_sspp), 133 .sspp = sc7180_sspp, 134 .mixer_count = ARRAY_SIZE(sc7180_lm), 135 .mixer = sc7180_lm, 136 .dspp_count = ARRAY_SIZE(sc7180_dspp), 137 .dspp = sc7180_dspp, 138 .pingpong_count = ARRAY_SIZE(sc7180_pp), 139 .pingpong = sc7180_pp, 140 .intf_count = ARRAY_SIZE(sc7180_intf), 141 .intf = sc7180_intf, 142 .wb_count = ARRAY_SIZE(sc7180_wb), 143 .wb = sc7180_wb, 144 .vbif_count = ARRAY_SIZE(sdm845_vbif), 145 .vbif = sdm845_vbif, 146 .reg_dma_count = 1, 147 .dma_cfg = &sdm845_regdma, 148 .perf = &sc7180_perf_data, 149 .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \ 150 BIT(MDP_SSPP_TOP0_INTR2) | \ 151 BIT(MDP_SSPP_TOP0_HIST_INTR) | \ 152 BIT(MDP_INTF0_INTR) | \ 153 BIT(MDP_INTF1_INTR), 154 }; 155 156 #endif 157